ISA-based data acquisition and control board
The hardware is a PC-based data acquisition and control board with many capabilities,It can accept up to 8 analog inputs,produce 2 analog outputs,accept up to 67 digital (switch) inputs and produce 8 digital outputs,It also offers the opportunity for expansion by providing buffered address,data and select lines,In addition,a spare AND gate and two spare NOR gates are made available,along with a small breadboarding area,
THE CIRCUIT
You will see references to PDF data sheets in the following descriptions,The data sheets might show parts with variations on the part number,but they will have the same functionality,
This section will cover parts of the circuit not covered in the experiments,
Port addresses on a typical PC Industry Standard Architecture (ISA) bus are derived from the ten address lines A0 through A9,with A9 always high,Note that all buffered lines in the schematics are prefixed with the letter B,Half of IC7,a 74LS244 buffer,is used to buffer the first three address lines and the RESET line,
Base address selection is made by three DIP switch sections connected to IC11,a 74LS688 8-bit magnitude comparator,
The main logic elements in the 74LS688 are the NXOR gates,Recall from the Boolean Logic section that an XOR gate will produce a high output if the inputs are different,The NXOR does the same thing but inverts the output,The output of one of the NXOR gates above will be low if its outputs are different,If its inputs are the same,its output will be high,Although pairs of inputs go through inverting buffers,the logic is not changed,When all of the NXOR outputs go high along with the enable input on pin 1,the 9-input NAND gate output will go low,
When a switch is closed,its input to the 74LS688 is taken low,When the switch is open,the input is pulled up by a resistor in an array,Corresponding inputs to the comparator are connected to address lines A6 through A8,If a switch is open,its corresponding address line must be high to make the output of its NXOR high,If a switch is closed,its corresponding address line must be low,A9 is also connected,with its corresponding input taken high,Similarly,the AEN (address enable) line is connected to the comparator with its corresponding input connected to ground,AEN is low with a valid port address,The three other pairs are taken high,Finally,either the I/O Read (IOR) or the I/O Write (IOW) line must be low for there to be a valid port address,The bars over IOR and IOW in the schematic mean they are active low,IOR and IOW are first buffered by using two AND gates with one side tied high in IC8,a 74LS08,then ANDed using a third,The result is a signal that will go low if either IOW or IOR goes low,This is tied to the pin 1 enable input of the 74LS688,When all conditions are satisfied,pin 19 of the 74LS688 will go low,
Following are the HEX addresses that can be selected by setting the DIP switches on (1) and off (0),and the possible conflicts that might arise (~ means "through"),
SWITCH
1 2 3
ADDRESS
POSSIBLE CONFLICTS
1 1 1
200 ~ 23F
200 ~ 20F = game port
0 1 1
240 ~ 27F
278 ~ 27F = LPT2 (OK with no spares used -- see below)
1 0 1
280 ~ 2BF
2B0 ~ 2DF = Alternate EGA
0 0 1
2C0 ~ 2FF
2B0 ~ 2DF = Alternate EGA
1 1 0
300 ~ 33F
300 ~ 31F = Some Sound Cards and The Prototype Card
0 1 0
340 ~ 37F
378 ~ 37F = LPT1 (OK with no spares used)
1 0 0
380 ~ 3BF
380 ~ 38F = bisynchronous 2
390 ~ 393 = cluster
3A0 ~ 3AF = bisynchronous 1
3B0 ~ 3BF = mono adapter and printer adapter
0 0 0
3C0 ~ 3FF
3C0 ~ 3CF = EGA
The best choices would probably be HEX 200 or 300,If the board is used on a dedicated computer however,any conflicting devices not used could be removed from the computer,
IC12,a 74LS138 3-to-8 line decoder/multiplexer,uses address lines A3 through A5 to break the above up into eight byte chunks used by devices on the board,The device selections for all possible switch settings are shown below,The first entry for each corresponds to the base address in the table above,Don't be concerned if you don't know what some of the items in the tables mean,They will be covered in the experiments,
200 ~ 207
Eight Channel Analog to Digital Converter
208 ~ 20F
Digital to Analog Converter 1
210 ~ 217
Digital to Analog Converter 2 (optional)
218 ~ 21F
Analog to Digital Converter Ready Line And 3 Digital Inputs
220 ~ 227
Programmable Peripheral Interface
228 ~ 22F
Spare Select Line
230 ~ 237
Spare Select Line
238 ~ 23F
Spare Select Line
240 ~ 247
Eight Channel Analog to Digital Converter
248 ~ 24F
Digital to Analog Converter 1
250 ~ 257
Digital to Analog Converter 2 (optional)
258 ~ 25F
Analog to Digital Converter Ready Line And 3 Digital Inputs
260 ~ 267
Programmable Peripheral Interface
268 ~ 26F
Spare Select Line
270 ~ 277
Spare Select Line
278 ~ 27F
Spare Select Line
280 ~ 287
Eight Channel Analog to Digital Converter
288 ~ 28F
Digital to Analog Converter 1
290 ~ 297
Digital to Analog Converter 2 (optional)
298 ~ 29F
Analog to Digital Converter Ready Line And 3 Digital Inputs
2A0 ~ 2A7
Programmable Peripheral Interface
2A8 ~ 2AF
Spare Select Line
2B0 ~ 2B7
Spare Select Line
2B8 ~ 2BF
Spare Select Line
2C0 ~ 2C7
Eight Channel Analog to Digital Converter
2C8 ~ 2CF
Digital to Analog Converter 1
2D0 ~ 2D7
Digital to Analog Converter 2 (optional)
2D8 ~ 2DF
Analog to Digital Converter Ready Line And 3 Digital Inputs
2E0 ~ 2E7
Programmable Peripheral Interface
2E8 ~ 2EF
Spare Select Line
2F0 ~ 2F7
Spare Select Line
2F8 ~ 2FF
Spare Select Line
300 ~ 307
Eight Channel Analog to Digital Converter
308 ~ 30F
Digital to Analog Converter 1
310 ~ 317
Digital to Analog Converter 2 (optional)
318 ~ 31F
Analog to Digital Converter Ready Line And 3 Digital Inputs
320 ~ 327
Programmable Peripheral Interface
328 ~ 32F
Spare Select Line
330 ~ 337
Spare Select Line
338 ~ 33F
Spare Select Line
340 ~ 347
Eight Channel Analog to Digital Converter
348 ~ 34F
Digital to Analog Converter 1
350 ~ 357
Digital to Analog Converter 2 (optional)
358 ~ 35F
Analog to Digital Converter Ready Line And 3 Digital Inputs
360 ~ 367
Programmable Peripheral Interface
368 ~ 36F
Spare Select Line
370 ~ 377
Spare Select Line
378 ~ 37F
Spare Select Line
380 ~ 387
Eight Channel Analog to Digital Converter
388 ~ 38F
Digital to Analog Converter 1
390 ~ 397
Digital to Analog Converter 2 (optional)
398 ~ 39F
Analog to Digital Converter Ready Line And 3 Digital Inputs
3A0 ~ 3A7
Programmable Peripheral Interface
3A8 ~ 3AF
Spare Select Line
3B0 ~ 3B7
Spare Select Line
3B8 ~ 3BF
Spare Select Line
3C0 ~ 3C7
Eight Channel Analog to Digital Converter
3C8 ~ 3CF
Digital to Analog Converter 1
3D0 ~ 3D7
Digital to Analog Converter 2 (optional)
3D8 ~ 3DF
Analog to Digital Converter Ready Line And 3 Digital Inputs
3E0 ~ 3E7
Programmable Peripheral Interface
3E8 ~ 3EF
Spare Select Line
3F0 ~ 3F7
Spare Select Line
3F8 ~ 3FF
Spare Select Line
Figure 1,Circuit,Part 1
Figure 2,Circuit,Part 2
Figure 3,Board Layout Silk Screen Print
The following are provided on the headers,
Header 1,
A,3 basic switch inputs
B,8 8-bit Analog To Digital inputs (0 through 5 volts)
C,2 8-bit Digital To Analog outputs (0 through 5 volts)
D,Pre-amp Output
E,2 grounds
Header 2,
A,2 Spare NOR gates (the spare AND is brought out to pads)
B,2 +5V and 2 grounds
Header 3,
A,24 PPI I/O lines
B,2 grounds
Header 4,
A,1 ground
B,The 14.31818 MHz oscillator divided by 2,4,8,16,32,64,128 and 256
C,3 Spare Select Lines
D,Buffered address lines BA0 through BA2
E,Buffered data lines BD0 through BD7
F,Buffered read,write and reset lines
Notice the inclusion of spare select lines and buffered data and address lines,They can be used to expand the capabilities,For example,you could add more PPIs to give you more digital I/O lines,or another digital to analog converter or two,There is also a small bread board area,
Figure 4 shows where the controls,mike input and speaker/headphone output are on the board,
The hardware is a PC-based data acquisition and control board with many capabilities,It can accept up to 8 analog inputs,produce 2 analog outputs,accept up to 67 digital (switch) inputs and produce 8 digital outputs,It also offers the opportunity for expansion by providing buffered address,data and select lines,In addition,a spare AND gate and two spare NOR gates are made available,along with a small breadboarding area,
THE CIRCUIT
You will see references to PDF data sheets in the following descriptions,The data sheets might show parts with variations on the part number,but they will have the same functionality,
This section will cover parts of the circuit not covered in the experiments,
Port addresses on a typical PC Industry Standard Architecture (ISA) bus are derived from the ten address lines A0 through A9,with A9 always high,Note that all buffered lines in the schematics are prefixed with the letter B,Half of IC7,a 74LS244 buffer,is used to buffer the first three address lines and the RESET line,
Base address selection is made by three DIP switch sections connected to IC11,a 74LS688 8-bit magnitude comparator,
The main logic elements in the 74LS688 are the NXOR gates,Recall from the Boolean Logic section that an XOR gate will produce a high output if the inputs are different,The NXOR does the same thing but inverts the output,The output of one of the NXOR gates above will be low if its outputs are different,If its inputs are the same,its output will be high,Although pairs of inputs go through inverting buffers,the logic is not changed,When all of the NXOR outputs go high along with the enable input on pin 1,the 9-input NAND gate output will go low,
When a switch is closed,its input to the 74LS688 is taken low,When the switch is open,the input is pulled up by a resistor in an array,Corresponding inputs to the comparator are connected to address lines A6 through A8,If a switch is open,its corresponding address line must be high to make the output of its NXOR high,If a switch is closed,its corresponding address line must be low,A9 is also connected,with its corresponding input taken high,Similarly,the AEN (address enable) line is connected to the comparator with its corresponding input connected to ground,AEN is low with a valid port address,The three other pairs are taken high,Finally,either the I/O Read (IOR) or the I/O Write (IOW) line must be low for there to be a valid port address,The bars over IOR and IOW in the schematic mean they are active low,IOR and IOW are first buffered by using two AND gates with one side tied high in IC8,a 74LS08,then ANDed using a third,The result is a signal that will go low if either IOW or IOR goes low,This is tied to the pin 1 enable input of the 74LS688,When all conditions are satisfied,pin 19 of the 74LS688 will go low,
Following are the HEX addresses that can be selected by setting the DIP switches on (1) and off (0),and the possible conflicts that might arise (~ means "through"),
SWITCH
1 2 3
ADDRESS
POSSIBLE CONFLICTS
1 1 1
200 ~ 23F
200 ~ 20F = game port
0 1 1
240 ~ 27F
278 ~ 27F = LPT2 (OK with no spares used -- see below)
1 0 1
280 ~ 2BF
2B0 ~ 2DF = Alternate EGA
0 0 1
2C0 ~ 2FF
2B0 ~ 2DF = Alternate EGA
1 1 0
300 ~ 33F
300 ~ 31F = Some Sound Cards and The Prototype Card
0 1 0
340 ~ 37F
378 ~ 37F = LPT1 (OK with no spares used)
1 0 0
380 ~ 3BF
380 ~ 38F = bisynchronous 2
390 ~ 393 = cluster
3A0 ~ 3AF = bisynchronous 1
3B0 ~ 3BF = mono adapter and printer adapter
0 0 0
3C0 ~ 3FF
3C0 ~ 3CF = EGA
The best choices would probably be HEX 200 or 300,If the board is used on a dedicated computer however,any conflicting devices not used could be removed from the computer,
IC12,a 74LS138 3-to-8 line decoder/multiplexer,uses address lines A3 through A5 to break the above up into eight byte chunks used by devices on the board,The device selections for all possible switch settings are shown below,The first entry for each corresponds to the base address in the table above,Don't be concerned if you don't know what some of the items in the tables mean,They will be covered in the experiments,
200 ~ 207
Eight Channel Analog to Digital Converter
208 ~ 20F
Digital to Analog Converter 1
210 ~ 217
Digital to Analog Converter 2 (optional)
218 ~ 21F
Analog to Digital Converter Ready Line And 3 Digital Inputs
220 ~ 227
Programmable Peripheral Interface
228 ~ 22F
Spare Select Line
230 ~ 237
Spare Select Line
238 ~ 23F
Spare Select Line
240 ~ 247
Eight Channel Analog to Digital Converter
248 ~ 24F
Digital to Analog Converter 1
250 ~ 257
Digital to Analog Converter 2 (optional)
258 ~ 25F
Analog to Digital Converter Ready Line And 3 Digital Inputs
260 ~ 267
Programmable Peripheral Interface
268 ~ 26F
Spare Select Line
270 ~ 277
Spare Select Line
278 ~ 27F
Spare Select Line
280 ~ 287
Eight Channel Analog to Digital Converter
288 ~ 28F
Digital to Analog Converter 1
290 ~ 297
Digital to Analog Converter 2 (optional)
298 ~ 29F
Analog to Digital Converter Ready Line And 3 Digital Inputs
2A0 ~ 2A7
Programmable Peripheral Interface
2A8 ~ 2AF
Spare Select Line
2B0 ~ 2B7
Spare Select Line
2B8 ~ 2BF
Spare Select Line
2C0 ~ 2C7
Eight Channel Analog to Digital Converter
2C8 ~ 2CF
Digital to Analog Converter 1
2D0 ~ 2D7
Digital to Analog Converter 2 (optional)
2D8 ~ 2DF
Analog to Digital Converter Ready Line And 3 Digital Inputs
2E0 ~ 2E7
Programmable Peripheral Interface
2E8 ~ 2EF
Spare Select Line
2F0 ~ 2F7
Spare Select Line
2F8 ~ 2FF
Spare Select Line
300 ~ 307
Eight Channel Analog to Digital Converter
308 ~ 30F
Digital to Analog Converter 1
310 ~ 317
Digital to Analog Converter 2 (optional)
318 ~ 31F
Analog to Digital Converter Ready Line And 3 Digital Inputs
320 ~ 327
Programmable Peripheral Interface
328 ~ 32F
Spare Select Line
330 ~ 337
Spare Select Line
338 ~ 33F
Spare Select Line
340 ~ 347
Eight Channel Analog to Digital Converter
348 ~ 34F
Digital to Analog Converter 1
350 ~ 357
Digital to Analog Converter 2 (optional)
358 ~ 35F
Analog to Digital Converter Ready Line And 3 Digital Inputs
360 ~ 367
Programmable Peripheral Interface
368 ~ 36F
Spare Select Line
370 ~ 377
Spare Select Line
378 ~ 37F
Spare Select Line
380 ~ 387
Eight Channel Analog to Digital Converter
388 ~ 38F
Digital to Analog Converter 1
390 ~ 397
Digital to Analog Converter 2 (optional)
398 ~ 39F
Analog to Digital Converter Ready Line And 3 Digital Inputs
3A0 ~ 3A7
Programmable Peripheral Interface
3A8 ~ 3AF
Spare Select Line
3B0 ~ 3B7
Spare Select Line
3B8 ~ 3BF
Spare Select Line
3C0 ~ 3C7
Eight Channel Analog to Digital Converter
3C8 ~ 3CF
Digital to Analog Converter 1
3D0 ~ 3D7
Digital to Analog Converter 2 (optional)
3D8 ~ 3DF
Analog to Digital Converter Ready Line And 3 Digital Inputs
3E0 ~ 3E7
Programmable Peripheral Interface
3E8 ~ 3EF
Spare Select Line
3F0 ~ 3F7
Spare Select Line
3F8 ~ 3FF
Spare Select Line
Figure 1,Circuit,Part 1
Figure 2,Circuit,Part 2
Figure 3,Board Layout Silk Screen Print
The following are provided on the headers,
Header 1,
A,3 basic switch inputs
B,8 8-bit Analog To Digital inputs (0 through 5 volts)
C,2 8-bit Digital To Analog outputs (0 through 5 volts)
D,Pre-amp Output
E,2 grounds
Header 2,
A,2 Spare NOR gates (the spare AND is brought out to pads)
B,2 +5V and 2 grounds
Header 3,
A,24 PPI I/O lines
B,2 grounds
Header 4,
A,1 ground
B,The 14.31818 MHz oscillator divided by 2,4,8,16,32,64,128 and 256
C,3 Spare Select Lines
D,Buffered address lines BA0 through BA2
E,Buffered data lines BD0 through BD7
F,Buffered read,write and reset lines
Notice the inclusion of spare select lines and buffered data and address lines,They can be used to expand the capabilities,For example,you could add more PPIs to give you more digital I/O lines,or another digital to analog converter or two,There is also a small bread board area,
Figure 4 shows where the controls,mike input and speaker/headphone output are on the board,
