Computer English
Chapter 2 Organization of
Computers
Chapter 2 Organization of Computers
计算机专业英语 2-2
Key points:
useful terms and organization
of computers
Difficult points:
describing the organization of
computers
Chapter 2 Organization of Computers
计算机专业英语 2-3
Requirements:
1,Terms of computer hardware
2,Organization of computers and their functions
3,掌握专业词汇的构成规律，特别是常用词缀及复合词
的构成
Chapter 2 Organization of Computers
计算机专业英语 2-4
New Words & Expressions:
instruction cycle 指令周期 decode vt.解码,译解
bus n,总线 pins n.插脚,管脚
uppermost adj.最高的； adv.在最上 address bus 地址总线
data bus 数据总线 via prep.经,通过,经由
multibit 多位 bidirectional 双向的
unidirectional 单向的 hierarchy n.层次，层级
microprocessor n.微处理器 register n.寄存器
timing n.定时；时序；时间选择 synchronize vt.使,..同步
assert vt.主张，发出 deassert vt,撤销
trigger vt.引发,引起,触发 map v.映射
port n.端口
2.1 Basic Organization of Computers
Abbreviations:
CPU(Central Processing Unit) 中央处理器
I/O(Input/Output) 输入输出 (设备 )
Chapter 2 Organization of Computers
计算机专业英语 2-5
2.1 Basic Organization of Computers
C PU
Mem ory
S u b s y s tem
I /O
D evice
I /O
D evice
…
I /O S u b s y s tem
A d d r es s Bu s
D at a Bu s
C on tr ol Bu s
Fig.2-1 Generic computer organization
Chapter 2 Organization of Computers
计算机专业英语 2-6
2.1 Basic Organization of Computers
Most computer systems,from the embedded controllers found in
automobiles and consumer appliances to personal computers
and mainframes,have the same basic organization,This
organization has three main components,the CPU,the memory
subsystem,and the I/O subsystem,The generic organization of
these components is shown in Figure 2-1.
大多数计算机系统，从汽车和日用电器中的嵌入式控制器到
个人计算机和大型主机，都具有相同的基本组成。其基本组
成包括三个主要部件,CPU、存储器子系统和 I/O子系统。这
些部件的一般组成如图 2-1所示。
Chapter 2 Organization of Computers
计算机专业英语 2-7
Physically,a bus is a set of wires,The components of the computer are
connected to the buses,To send information from one component to another,
the source component outputs data onto the bus,The destination
component then inputs this data from the bus,As the complexity of a
computer system increases,it becomes more efficient (in terms of
minimizing connections) at using buses rather than direct connections
between every pair of devices,Buses use less space on a circuit board and
require less power than a large number of direct connections,They also
require fewer pins on the chip or chips that comprise the CPU.
2.1.1 System Buses
从物理上来说，总线就是一组导线。计算机的部件就是连在总线上的。为了将信息
从一个部件传到另一个部件，源部件先将数据输出到总线上，然后目标部件再从总
线上接受这些数据。随着计算机系统复杂性的不断增长，使用总线比每个设备对之
间直接连接要有效得多（就减少连接数量而言）。与大量的直接连接相比，总线使
用较少的电路板空间，耗能更少，并且在芯片或组成 CPU的芯片组上需要较少的引
脚。
Chapter 2 Organization of Computers
计算机专业英语 2-8
The system shown in Figure 2-1 has three buses,The uppermost bus in this figure
is the address bus,When the CPU reads data or instructions from or writes data to
memory,it must specify the address of the memory location it wishes to access,It
outputs this address to the address bus; memory inputs this address from the
address bus and use it to access the proper memory location,Each I/O devices,
such as a keyboard,monitor,or disk drive,has a unique address as well,When
accessing an I/O device,the CPU places the address of the device on the address
bus,Each device can read the address off of the bus and determine whether it is
the device being accessed by the CPU,Unlike the other buses,the address bus
always receives data from the CPU; the CPU never reads the address bus.
图 2-1所示的系统包括三组总线。最上面的是地址总线。当 CPU从存储器读取数据或
指令，或写数据到存储器时，它必须指明将要访问的存储器单元地址。 CPU将地址
输出到地址总线上，而存储器从地址总线上读取地址，并且用它来访问正确的存储
单元。每个 I/O设备，比如键盘、显示器或者磁盘，同样都有一个唯一的地址。当访
问某个 I/O设备时,CPU将此设备的地址放到地址总线上。每一个设备均从总线上读
取地址并且判断自己是否就是 CPU正要访问的设备。与其他总线不同，地址总线总
是从 CPU上接收信息，而 CPU从不读取地址总线。
2.1.1 System Buses
Chapter 2 Organization of Computers
计算机专业英语 2-9
Data is transferred via the data bus,When the CPU fetches data
from memory,it first outputs the memory address on its address
bus,Then memory outputs the data onto the data bus; the CPU can
then read the data from the data bus,When writing data to memory,
the CPU first outputs the address onto the address bus,then
outputs the data onto the data bus,Memory then reads and stores
the data at the proper location,The processes for reading data from
and writing data to the I/O devices are similar.
数据是通过数据总线传送的。当 CPU从存储器中取数据时，它首先把存储器
地址输出到地址总线上，然后存储器将数据输出到数据总线上，这样 CPU就
可以从数据总线上读取数据了。当 CPU向存储器中写数据时，它首先将地址
输出到地址总线上，然后把数据输出到数据总线上，这样存储器就可以从数
据总线上读取数据并将它存储到正确的单元中。对 I/O设备读写数据的过程
与此类似。
2.1.1 System Buses
Chapter 2 Organization of Computers
计算机专业英语 2-10
The control bus is different from the other two buses,The address bus consists of
n lines,which combine to transmit one n-bit address value,Similarly,the lines of
the data bus work together to transmit a single multibit value,In contrast,the
control bus is a collection of individual control signals,These signals indicate
whether data is to be read into or written out of the CPU,whether the CPU is
accessing memory or an I/O device,and whether the I/O device or memory is
ready to transfer data,Although this bus is shown as bidirectional in Figure 2-1,it
is really a collection of (mostly) unidirectional signals,Most of these signals are
output from the CPU to the memory and I/O subsystems,although a few are
output by these subsystems to the CPU,We examine these signals in more detail
when we look at the instruction cycle and the subsystem interface.
控制总线与以上两种总线都不相同。地址总线由 n根线构成,n根线联合传送一个 n位
的地址值。类似地，数据总线的各条线合起来传输一个单独的多位值。相反，控制
总线是单根控制信号的集合。这些信号用来指示数据是要读入 CPU还是要从 CPU写
出,CPU是要访问存储器还是要访问 I/O设备，是 I/O设备还是存储器已就绪要传送
数据等等。虽然图 2-1所示的控制总线看起来是双向的，但它实际上（主要）是单向
（大多数都是）信号的集合。大多数信号是从 CPU输出到存储器与 I/O子系统的，只
有少数是从这些子系统输出到 CPU的。在介绍指令周期和子系统接口时，我们将详
细地讨论这些信号。
2.1.1 System Buses
Chapter 2 Organization of Computers
计算机专业英语 2-11
A system may have a hierarchy of buses,For example,it may use
its address,data,and control buses to access memory,and an I/O
controller,The I/O controller,in turn,may access all I/O devices
using a second bus,often called an I/O bus or a local bus,
一个系统可能具有分层次的总线。例如，它可能使用地址、数
据和控制总线来访问存储器和 I/O控制器。 I/O控制器可能依次
使用第二级总线来访问所有的 I/O设备，第二级总线通常称为
I/O总线或者局部总线。
2.1.1 System Buses
Chapter 2 Organization of Computers
计算机专业英语 2-12
The instruction cycle is the procedure a microprocessor goes through to process
an instruction,First the microprocessor fetches,or reads,the instruction from
memory,Then it decodes the instruction,determining which instruction it has
fetched,Finally,it performs the operations necessary to execute the instruction,
(Some people also include an additional element in the instruction cycle to store
results,Here,we include that operation as part of the execute function.) Each of
these functions--fetch,decode,and execute--consists of a sequence of one or
more operations.
指令周期是微处理器完成一条指令处理的步骤。首先，微处理器从存储器读
取指令，然后将指令译码，辩明它取的是哪一条指令。最后，它完成必要的
操作来执行指令（有人认为在指令周期中还要包括一个附加的步骤来存储结
果，这里我们把该操作当作执行功能的一部分）。每一个功能 —— 读取、译
码和执行都包括一个或多个操作。
2.1.2 Instruction Cycle
Chapter 2 Organization of Computers
计算机专业英语 2-13
Let's start where the computer starts,with the microprocessor
fetching the instruction from memory,First,the microprocessor
places the address of the instruction on to the address bus,The
memory subsystem inputs this address and decodes it to access the
sired memory location,(We look at how this decoding occurs
when we examine the memory subsystem in more detail later in
this chapter.)
我们从微处理器从存储器中取指令开始讲述。首先，微处理器
把指令的地址放到地址总线上，然后，存储器子系统从总线上
输入该地址并予以译码，去访问指定的存储单元。（译码是如
何进行的，我们将在后面的章节中介绍存储器子系统是更为详
细的讨论。）
2.1.2 Instruction Cycle
Chapter 2 Organization of Computers
计算机专业英语 2-14
After the microprocessor allows sufficient time for memory to decode the
address and access the requested memory location,the microprocessor asserts a
READ control signal,The READ signal is a signal on the control bus which the
microprocessor asserts when it is ready to read data from memory or an I/O
device,(Some processors have a different name for this signal,but all
microprocessors have a signal to perform this function.) Depending on the
microprocessor,the READ signal may be active high (asserted - 1) or active low
(asserted - 0).
当微处理器为存储器留出充足的时间来对地址译码和访问所需的存储单元之
后，微处理器发出一个读（ READ）控制信号。当微处理器准备好可以从存
储器或是 I/O设备读数据时，它就在控制总线上发一个读信号。（一些处理器
对于这个信号有不同的名字，但所有处理器都有这样的信号来执行这个功
能。）根据微处理器的不同，读信号可能是高电平有效（信号 =1），也可能
是低电平有效（信号 =0）。
2.1.2 Instruction Cycle
Chapter 2 Organization of Computers
计算机专业英语 2-15
When the READ signal is asserted,the memory subsystem places
the instruction code to be fetched onto the computer system's data
bus,The microprocessor then inputs this data from the bus and
stores it in one of its internal registers,At this point,the
microprocessor has fetched the instruction.
读信号发出后，存储器子系统就把要取的指令码放到计算机的
数据总线上，微处理器就从数据总线上输入该数据并且将它存
储在其内部的某个寄存器中。至此，微处理器已经取得了指令。
2.1.2 Instruction Cycle
Chapter 2 Organization of Computers
计算机专业英语 2-16
Next,the microprocessor decodes the instruction,Each instruction
may require a different sequence of operations to execute the
instruction,When the microprocessor decodes the instruction,it
determines which instruction it is in order to select the correct
sequence of operations to perform,This is done entirely within the
microprocessor; it does not use the system buses.
接下来，微处理器对这条指令译码。每一条指令可能要有不同
的操作序列来执行。当微处理器对该指令译码是，它确定处理
的是哪一条指令以便选择正确的操作序列去执行。这一步完全
在微处理器内完成，不需要使用系统总线。
2.1.2 Instruction Cycle
Chapter 2 Organization of Computers
计算机专业英语 2-17
Finally,the microprocessor executes the instruction,The sequence of operations
to execute the instruction varies from instruction to instruction,The execute
routine may read data from memory,write data to memory,read data from or
write data to an I/O device,perform only operations within the CPU,or perform
some combination of these operations,We now look at how the computer
performs these operations from a system perspective.
最后，微处理器执行该指令。指令不同，执行的操作序列也不
同。执行过程可以是从存储器读取数据，写数据到存储器，读
或写数据到 I/O设备，执行 CPU内部操作或者执行多个上述操作
的组合。下面我们从系统的角度来看计算机是怎样执行这些操
作的。
2.1.2 Instruction Cycle
Chapter 2 Organization of Computers
计算机专业英语 2-18
To read data from memory,the microprocessor performs the same
sequence of operations it uses to fetch an instruction from memory,
After all,fetching an instruction is simply reading it from memory,
Figure 2-2(a) shows the timing of the operations to read data from
memory.
微处理器从存储器读取数据所执行的操作序列，同从存储器中
去一条指令是一样的。毕竟取指令就是简单地从存储器中读取
它。图 2-2(a)显示了从存储器中读取数据的操作时序。
2.1.2 Instruction Cycle
Chapter 2 Organization of Computers
计算机专业英语 2-19
In Figure 2-2,notice the top symbol,CLK,This is the computer system clock; the
microprocessor uses the system clock to synchronize its operations,The
microprocessor places the address onto the bus at the beginning of a clock cycle,a
0/1 sequence of the system clock,One clock cycle later,to allow time for memory
to decode the address and access its data,the microprocessor asserts the READ
Signal,This causes memory to place its data onto the system data bus,During this
clock cycle,the microprocessor reads the data off the system bus and stores it in
one of its registers,At the end of the clock cycle it removes the address from the
address bus and deasserts the READ signal,Memory then removes the data from
the data bus,completing the memory read operation.
在图 2-2中，注意最上面的符号 CLK，它是计算机的系统时钟，微处理器用系统时钟
使其操作同步。在一个时钟周期（系统时钟的 0/1序列）的开始位置，微处理器将地
址放到总线上。一个时钟周期（允许存储器对地址译码和访问数据的时间）之后，
微处理器才发出读信号。这使得存储器将数据放到数据总线上。在这个时钟周期之
内，微处理器从系统总线上读取数据，并存储到它的某个寄存器中。在这个时钟周
期结束时，微处理器撤消地址总线上的地址，并撤消读信号。然后存储器从数据总
线上撤消数据，也就完成了存储器的读操作。
2.1.2 Instruction Cycle
Chapter 2 Organization of Computers
计算机专业英语 2-20
The timing of the memory write operation is shown in Figure 2-2(b),The
processor places the address and data onto the system buses during the first
clock cycle,The microprocessor then asserts a WRITE control signal (or its
equivalent) at the start of the second clock cycle,Just as the READ signal causes
memory to read data,the WRITE signal triggers memory to store data,Some
time during this cycle,memory writes the data on the data bus to the memory
location whose address is on the address bus,At the end of this cycle,the
processor completes the memory write operation by removing the address and
data from the system buses and deasserting the WRITE signal.
存储器写操作的时序如图 2-2(b)所示。在第一个时钟周期，处理器将地址和
数据放到总线上，然后在第二个时钟周期开始 时发出一个写（ WRITE）控
制信号（或与之等价的信号）。像读信号促使存储器读取数据一样，写信号
促使存储器存储数据。在这个时钟周期的某个时刻，存储器将数据总线上的
数据写入地址总线指示的存储单元内。当这个时钟周期结束，微处理器从系
统总线上撤消地址、数据及写信号后，就完成了存储器的写操作。
2.1.2 Instruction Cycle
Chapter 2 Organization of Computers
计算机专业英语 2-21
The I/O read and write operations are similar to the memory read and write
operations,A processor may use either memory mapped I/O or isolated I/O,If the
processor supports memory mapped I/O,it follows the same sequences of
operations to input or output data as to read data from or write data to memory,
the sequences shown in Figure 2-2,(Remember,in memory mapped I/O,the
processor treats an I/O port as a memory location,so it is reasonable to treat an
I/O data access the same as a memory access.) Processors that use isolated I/O
follow the same process but have a second control signal to distinguish between
I/O and memory accesses,(CPUs that use isolated I/O can have a memory
location and an I/O port with the same address,which makes this extra signal
necessary.)
I/O的读写操作与存储器的读写操作类似。处理器可以使用存储器影射 I/O或者是单
独 I/O。如果处理器支持存储器影射 I/O,则它遵循从存储器读写数据同样的操作顺序，
该顺序如图 2-2所示（记住，在存储器影射 I/O中，处理器把一个 I/O端口当作某个存
储单元，当然 I/O的数据访问同存储器的数据访问一样的）。使用单独 I/O的处理器
遵循同样的处理过程，但是另有一个控制信号用以区别是 I/O访问还是存储器访问
（使用单独 I/O的 CPU允许一个存储单元和某个 I/O端口具有相同的地址，因此需要
这一额外的信号加以区分）。
2.1.2 Instruction Cycle
Chapter 2 Organization of Computers
计算机专业英语 2-22
Finally,consider instructions that are executed entirely within the
microprocessor,The INAC instruction of the Relatively Simple
CPU,and the MOV r1,r2 instruction of the 8085 microprocessor,
can be executed without accessing memory or I/O devices,As
with instruction decoding,the execution of these instructions does
not make use of the system buses.
最后，考虑一下完全在微处理器内部执行的指令。相对简单
CPU的 INAC指令和 8085的 MOV r1,r2指令的执行都不要访问
存储器和 I/O设备。按照指令译码的结果，这些指令的执行不会
用到系统总线。
2.1.2 Instruction Cycle
Chapter 2 Organization of Computers
计算机专业英语 2-23
New Words & Expressions:
latch v.闭锁,锁存 program counter 程序计数器
instruction register 指令寄存器 operand n,操作数
increment n.增量,加 1 flag register 标志寄存器
pipeline n.流水线 microsequenced 微层序的
local bus 局部总线
Abbreviations:
ALU (Arithmetic Logic Unit) 算术逻辑单元
2.2 CPU ORGANIZATION
Chapter 2 Organization of Computers
计算机专业英语 2-24
The CPU controls the computer,It fetches instructions from memory,
supplying the address and control signals needed by memory to access its
data,The CPU decodes the instruction and controls the execution procedure,
It performs some operations internally,and supplies the address,data,and
control signals needed by memory and I/O devices to execute the instruction,
Nothing happens in the computer unless the CPU causes it to happen,
CPU控制整个计算机。它从存储器中取指令，提供存储器需要
的地址和控制信号。 CPU对指令译码并且控制整个执行过程。
它执行一些内部操作，并且为存储器和 I/O设备执行指令提供必
要的地址、数据和控制信号。除非 CPU激发，否则，计算机什
么事情都不会发生。
2.2 CPU ORGANIZATION
Chapter 2 Organization of Computers
计算机专业英语 2-25
Internally,the CPU has three sections,as shown in Figure 2-3,The register
sections,as its name implies,includes a set of registers and a bus or other
communication mechanism,The registers in a processor's instruction set
architecture are found in this section of the CPU,The system address and data
buses interact with this section of the CPU,The register section also contains
other registers that are not directly accessible by the programmer,The relatively
simple CPU includes registers to latch the address being accessed in memory and
a temporary storage register,as well as other registers that are not a part of its
instruction set architecture.
CPU内部有三大分区，如图 2-3所示。寄存器区,顾名思义，它包括一组寄存
器、一条总线或其他通信机制。微处理器指令集结构中的寄存器就属于 CPU
的这一分区。系统的地址和数据总线与寄存器交互。此分区还包括程序员不
能直接访问的一些寄存器。相对简单 CPU含有寄存器用以锁存正在访问的存
储器地址，还有暂存器以及指令集结构中没有的其他寄存器等。
2.2 CPU ORGANIZATION
Chapter 2 Organization of Computers
计算机专业英语 2-26
During the fetch portion of the instruction cycle,the processor first outputs the
address of the instruction onto the address bus,The processor has a register
called the program counter; the CPU keeps the address of the next instruction to
be fetched in this register,Before the CPU outputs the address onto the system's
address bus,it retrieves the address from the program counter register,At the
end of the instruction fetch,the CPU reads the instruction code from the system
data bus,It stores this value in an internal register,usually called the instruction
register or something similar.
在指令周期的取指阶段，处理器首先将指令的地址输出到地址总线上。处理
器有一个寄存器叫做程序计数器,CPU将下一条要取的指令的地址存放在程
序计数器中。在 CPU将地址输出到系统的地址总线之前，必须从程序计数器
中取出该地址。在指令结束前,CPU从系统时局总线上读取指令码，它把该
指令码存储在某个内部寄存器中，该寄存器通常称作指令寄存器或其他相似
的名字。
2.2 CPU ORGANIZATION
Chapter 2 Organization of Computers
计算机专业英语 2-27
The arithmetic logic unit or ALU performs most arithmetic and logical
operations,such as adding or ADDing values,It receives its operands from
the register section of the CPU and stores its results back in the register
section,Since the ALU must complete its operations within a single clock
cycle,it is constructed using only combinatorial logic,The ADD
instructions in the relatively simple CPU and the 8085 microprocessor use
the ALU during their executions.
算术逻辑单元执行大部分的算术逻辑运算，如加法、逻辑与等
运算。它从 CPU的寄存器取得操作数，然后将运算结果再存回
到寄存器区。由于必须在一个时钟周期内完成操作，因此 ALU
只采用组合逻辑构造而成。相对简单 CPU和 8085微处理器中的
ADD指令在执行中都有使用 ALU。
2.2 CPU ORGANIZATION
Chapter 2 Organization of Computers
计算机专业英语 2-28
Just as the CPU controls the computer (in addition to its other functions),the
control unit controls the CPU,This unit generates the internal control signals that
cause registers to load data,increment or clear their contents,and output their
contents,as well as cause the ALU to perform the correct function,These signals
are shown as control signals in Figure 2-3,The control unit receives some data
values from the register unit,which it uses to generate the control signals,This
data includes the instruction code and the values of some flag registers,
同 CPU控制整个计算机（除了其他功能外）一样，控制单元控制着 CPU。这
个单元产生内部控制信号，促使寄存器装载数据，自动加 1或清零，输出它
的内容，使得 ALU完成正确的操作等等。这些信号作为控制信号显示在图 2-
3中。控制单元从寄存器区取得一些数据用以产生控制信号，这些数据包括
指令码和某些标志寄存器的值。
2.2 CPU ORGANIZATION
Chapter 2 Organization of Computers
计算机专业英语 2-29
The control unit also generates the signals for the system control
bus,such as the READ,WRITE,and signals,A microprocessor
typically performs a sequence of operations to fetch,decode,and
execute an instruction,By asserting these internal and external
control signals in the proper sequence,the control unit causes the
CPU and the rest of the computer to perform the operations
needed to correctly process instructions.
2.2 CPU ORGANIZATION
控制单元也产生系统控制总线上的信号，例如 READ,WRATE,
信号等。典型的一个微处理器执行取指令、译指令和执行指令
等一系列的操作。通过以正确的顺序激发这些内部或外部控制
信号，控制单元使 CPU和计算机的其余部分完成正确处理指令
所需要的操作。
Chapter 2 Organization of Computers
计算机专业英语 2-30
This description of the CPU is incomplete,Current processors
have more complex features that improve their performance,One
such mechanism,the instruction pipeline,allows the CPU to fetch
one instruction while simultaneously executing another instruction.
2.2 CPU ORGANIZATION
以上对 CPU的描述并不完整。现在的处理器拥有更加复杂的特
征以提高其性能。这些机制中有一种是指令流水线技术，它允
许 CPU在执行一条指令的同时取出另一条指令。
Chapter 2 Organization of Computers
计算机专业英语 2-31
In this section we have introduced the CPU from a system
perspective,but we have not discussed its internal design,We
examine the registers,data paths,and control unit,all of which
act together to cause the CPU to properly fetch,decode,and
execute instructions,Microsequenced CPUs have the same
registers,ALUs and data paths as hardwired CPUs,but
completely different control units,
本节我们从系统的角度介绍了 CPU，但我们还没有讨论它的内
部设计。我们描述了 CPU的寄存器、数据通路、控制单元等，
所有部件一起工作使 CPU正确地读取、译码和执行指令。微层
序 CPU具有同硬连线 CPU一样的寄存器,ALU和数据通路，但
二者控制单元完全不同。
2.2 CPU ORGANIZATION
Chapter 2 Organization of Computers
计算机专业英语 2-32
2.3 Memory Subsystem Organization and Interfacing
New Words & Expressions:
multibyte n.多字节 MB n.兆字节
shut off n.切断,关闭 enable n..使能
tri-state 三态 tri-stated 高阻态
dimension n.尺度,维 (数 ) configuration n.构造,结构,配置
as far as 尽；就；至于 high-order 高位
low-order 低位 interleaving n.交叉,交错
contiguous adj.邻近的,接近的 assign vt.分配,指派
big endian 高位优先 little endian 低位优先
hexadecimal adj.十六进制的； n.十六进制 alignment n.对齐方式
leftmost adj.最左边的 rightmost adj.最右边的，最右面的
consecutive adj.连续的,联贯的 cache n.高速缓冲
virtual memory 虚拟存储器 buffer n.缓冲器
ROM(Read Only Memory) 只读存储器
RAM(Random Access Memory) 随机存取存贮器
RISC(Reduced Instruction Set Computer) 精简指令集计算机
Chapter 2 Organization of Computers
计算机专业英语 2-33
2.3 Memory Subsystem Organization and Interfacing
In this section we examine the construction and functions of the
memory subsystem of a computer,We review the different types of
physical memory and the internal organization of their chips,We
discuss the construction of the memory subsystem,as well as
multibyte word organizations and advanced memory organizations.
本节我们将讨论计算机中存储器子系统的结构和功能。我们将
会回顾不同类型的物理存储器及其芯片的内部组成，讨论存储
器子系统的结构，以及多字节的组织和高级存储器的组成。
Chapter 2 Organization of Computers
计算机专业英语 2-34
2.3.1 Types of Memory
The internal organizations of ROM and RAM chips are similar,To
illustrate the simplest organization,a linear organization,consider an
8?2 ROM chip,For simplicity,programming components are not
shown,This chip has three address inputs and two data outputs,and
16 bits of internal storage arranged as eight 2-bit locations.
存储器芯片有两种类型：只读存储器（ ROM）和随机存取存储器
（ RAM）。只读存储器芯片是为数据（此数据可包括程序的指令）只读
的应用而设计的。这些芯片在加入系统之前，就已经被某个外部编程器而
装好数据了。这个工作一旦完成，其数据通常不再改变。 ROM芯片总是
保存有数据，甚至在芯片断电以后。例如，一个微波炉的嵌入式控制器可
以连续运行一个不变的程序。这个程序就存储在一片 ROM上。
Chapter 2 Organization of Computers
计算机专业英语 2-35
Random Access Memory (RAM),also called read/write memory,
can be used to store data that changes,This is the type of memory
referred to as X MB of memory in ads for PCs,Unlike ROM,RAM
chips lose their data once power is shut off,Many computer systems,
including personal computers,include both ROM and RAM.
2.3.1 Types of Memory
随机访问存储器也称为读写存储器，用来存储可以改变的
数据。这就是我们在个人电脑广告上经常看到的 XX MB的
内存所指的那种类型。不像 ROM,RAM芯片一旦掉电，数
据就会丢失。许多计算机系统，包括个人电脑，都同时拥
有 ROM和 RAM。
Chapter 2 Organization of Computers
计算机专业英语 2-36
2.3.2 Internal Chip Organization
The internal organizations of ROM and RAM chips are similar,To
illustrate the simplest organization,a linear organization,consider
an 8?2 ROM chip,For simplicity,programming components are
not shown,This chip has three address inputs and two data outputs,
and 16 bits of internal storage arranged as eight 2-bit locations.
ROM和 RAM芯片的内部组成是相似的。为了说明一个最简
单的组成 —— 线性组成，我们来考虑一个 8?2的 ROM芯片。
为了简化，编成器件没有画出来。这个芯片有三个地址输入
端和两个数据输出端，以及 16位的内部存储元件，它排列成
8个单元，每个单元 2位。
Chapter 2 Organization of Computers
计算机专业英语 2-37
The three address bits are decoded to select one of the eight
locations,but only if the chip enable is active,If CE=0,the
decoder is disabled and no location is selected,The tri-state
buffers for that location's cells are enabled,allowing data to pass
to the output buffers,If both CE and OE set to 1,these buffers
are enabled and the data is output from the chip; otherwise the
outputs are tri-stated.
2.3.2 Internal Chip Organization
三个地址位经过译码，可以选择 8个中的一个，但只有芯片的使能端要有
效才行。如果 CE=0，译码器被禁止，则不选择任何单元。该单元上的三
态缓冲器是有效的，允许数据输出到缓冲器中。如果 CE=1且 OE=1，则
这些缓冲器有效，数据从芯片中输出；否则，输出是高阻态。
Chapter 2 Organization of Computers
计算机专业英语 2-38
As the number of locations increases,the size of the address decoder
needed in a linear organization becomes prohibitively large,To
remedy this problem,the memory chip can be designed using
multiple dimensions of decoding,
2.3.2 Internal Chip Organization
随着单元数量的增加，线性组成中地址译码器的规模变得相
当大。为了补救这一问题，存储器芯片可以设计成使用多维
译码方式。
Chapter 2 Organization of Computers
计算机专业英语 2-39
In larger memory chips,this savings can be significant,Consider a 4096?1
chip,The linear organization will require a 12 to 4096 decoder,the size of
which is proportional to the number of outputs,(The size of an n to 2n
decoder is thus said to be O(2n).) If the chip is organized as a 64?64 two
dimensional array instead,it will have two 6 to 64 decoders,one to select one
of the 64 rows and the other to select one of the 64 cells within the row,The
size of the decoders is proportional to 2?64,or O(2?2n/2) = O(2n/2 +1),For
this chip,the two decoders together are about 3 percent of the size of the one
larger decoder.
2.3.2 Internal Chip Organization
在大型存储器芯片中，这种节省显得至关重要。考虑一个 4096?1芯片，
其线性组成将需要一个 12— 4096译码器，译码器大小与输出的数量成正
比（假定一个 n— 2n译码器的大小是 O(2n)）。如果芯片排列成 64?64的
二维数组，它将有两个 6— 64译码器：一个用来选择 64行中的一行，另一
个用来在选定行中选择 64个单元中的一个单元，该译码器的大小正比于
2?64，或写成 O(2?2n/2)=O(2n/2+1)。对于这个芯片，两个译码器总的大
小约是那个大译码器大小的 3%。
Chapter 2 Organization of Computers
计算机专业英语 2-40
2.3.3 Memory Subsystem Configuration
It is very easy to set up a memory system that consists of a single
chip,We simply connect the address,data,and control signals from
their system buses and the job is done,However,most memory
systems require more than one chip,Following are some methods for
combining memory chips to form a memory subsystem.
构造包含一个简单芯片的存储器是非常容易的，我们只需要简
单地从系统总线上连接地址信号线、数据信号线和控制信号线
就完成了。然而。大多数的存储器系统需要多个芯片，下面是
通过存储器芯片组合来形成存储器子系统的一些方法。
Chapter 2 Organization of Computers
计算机专业英语 2-41
2.3.3 Memory Subsystem Configuration
Two or more chips can be combined to create memory with more bits per location,
This is done by connecting the corresponding address and control signals of the
chips,and connecting their data pins to different bits of the data bus,For example,
two 8?2 chips can be combined to create an 8?4 memory,as shown in Figure 2-4,
Both chips receive the same three address inputs from the bus,as well as the same
chip enable and output enable signals,(For now it is only important to know that
the signals are the same for both chips; we show the logic to generate these signals
shortly.) The data pins of the first chip are connected to bits 3 and 2 of the data bus,
and those of the other chip are connected to bits 1 and 0,
两个或多个芯片可以组合起来构造一个每单元有多位的存储器。这可以通过
连接芯片相应的地址信号线和控制信号线，并将它们的数据引脚连到数据总
线的不同位上来完成。例如,2个 8?2芯片可以组合产生一个 8?4存储器，如
图 2-4所示。两个芯片从总线上接收相同的三位地址输入，还有共同的芯片
使能信号和输出使能信号（目前，我们只要了解两个芯片使用的是同一信号
就可以了，稍后我们将说明产生这些信号的逻辑）。第一个芯片的数据引脚
连到数据总线的第 3位和第 2位，第二个芯片的数据引脚则连在第 1位和第 0位。
Chapter 2 Organization of Computers
计算机专业英语 2-42
2.3.3 Memory Subsystem Configuration
When the CPU reads data,it places the address on the address bus,Both chips
read in address bits A2,A1,and A0 and perform their internal decoding,If the CE
and OE signals are activated,the chips output their data onto the four bits of the
data bus,Since the address and enable signals are the same for both chips,either
both chips or neither chip is active at any given time,The computer never has
only one of the two active,For this reason,they act just as a single 8?4 chip,at
least as far as the CPU is concerned.
当 CPU读取数据时，它将地址放在地址总线上。两个芯片读
取地址位 A2,A1,A0，并执行内部译码操作。如果 CE和
OE信号是有效的，两个芯片则输出数据到数据总线的四位
上。因为两个芯片的地址和使能信号是相同的，因此在任一
时刻两个芯片要么同时有效，要么同时无效。正因如此，它
们的行为就像一个单一的 8?4芯片，至少就 CPU而言是这样
的。
Chapter 2 Organization of Computers
计算机专业英语 2-43
2.3.3 Memory Subsystem Configuration
Instead of creating wider words,chips can be combined to create more words,The
same two 8 ?2 chips could instead be configured as a 16?2 memory subsystem,
This is illustrated in Figure 2-5(a),The upper chip is configured as memory
locations 0 to 7 (0000 to 0111) and the lower chip as locations 8 to 15 (1000 to
1111),The upper chip always has A3 = 0 and the lower chip has A3=1,This
difference is used to select one of the two chips,When A3 =0,the upper chip is
enabled and the lower chip is disabled; when A3 = 1,the opposite occurs,(As
shown in the figure,other conditions must also occur or neither chip will be
selected.) The output enables can be connected,since only the chip that is enabled
will output data,Since both chips correspond to the same data bits,both are
connected to D1 and D0 of the data bus.
除了构造更宽的字以外，芯片组合还可以构造出更多的字。两样的两个 8?2芯片能够组
成一个 16?2存储子系统。如图 2-5所示。上面的芯片构成存储器的 0到 7（ 0000到 0111）
单元，下面的芯片作为单元 8到 15（ 1000到 1111）。上面的芯片总是设置 A3=0,而下面
的芯片 A3=1。通过这一区别来选择芯片，当 A3=0时，上面的芯片有效，而下面的芯片
无效；当 A3=1时，情况刚好相反。（如图所示。另一种情况必定会发生，否则没有芯
片被选中。）输出使能端需要连接起来，因为只有芯片有效才可以输出数据。由于两
个芯片对应相同的数据位，因此都可以连接到数据总线的 D1和 D0位上。
Chapter 2 Organization of Computers
计算机专业英语 2-44
2.3.3 Memory Subsystem Configuration
This configuration uses high-order interleaving,All memory locations within a chip
are contiguous within system memory,However,this does not have to be the case,
Consider the configuration shown in Figure 2-5(b),which uses low-order
interleaving,The upper chip is enabled when A0=0,or by addresses XXX0,in this
case 0,2,4,6,8,10,12,and 14,The lower chip is enabled when A0=1,which is
true for addresses l,3,5,7,9,11,13,and 15,Both look the same to the CPU,but
low-order interleaving can offer some speed advantages for pipelined memory
access,and for CPUs that can read data from more than one memory location
simultaneously.
这种配置使用的是高位交叉技术。同一芯片的所有存储单元在系统内存中是
连续的。然而，不一定非得如此。考虑如图 2-5(b)所示的情况，它用的是低
位交叉技术。上面的芯片当 A0=0或者当地址位为 XXX0时有效，此时，地址
为 0,2,4,6,8,10和 12；下面的芯片当 A0=1时有效，条件是地址为 1,3、
5,7,9,11,13和 15。对 CPU而言，两者是相同的。但低位交叉能为流水
线存储器访问提供速度上的优势，对于能够同时从多于一个存储器单元中读
取数据的 CPU来说，低位交叉也存在速度上的优势。
Chapter 2 Organization of Computers
计算机专业英语 2-45
2.3.3 Memory Subsystem Configuration
The next step in these designs is to develop the CE and OE input
logic,Of these,the output enable is more straightforward,The CPU
generally outputs a control signal called RD or RD',or something
similar,which it sets active when it wants to read data from
memory,This signal is sufficient to drive OE; the logic to drive CE
ensures that only the correct chip outputs data,
设计的下一步就是指制定 CE和 OE的输入逻辑。输出使能更直
接一些,CPU通常输出一个控制信号，称作 RD或 RD'或别的
什么，当它想要从主存读取数据时就将其设为有效，用此信
号驱动 OE就足够了，而驱动 CE的逻辑务必确保只有正确的芯
片方可输出数据。
Chapter 2 Organization of Computers
计算机专业英语 2-46
2.3.3 Memory Subsystem Configuration
The chip enable signal makes use of the unused address bits,To
illustrate,assume that the 8 ?4 memory of Figure 2-4 is used in a
system with 6-bit address bus,Furthermore,assume this chip
corresponds to locations 0 to 7 (00 0000 to 00 0111),Address bits
A2,A1,and A0 select a location within the memory chips; bits A5,
A4,and A3 must be 000 for the chips to be active,
芯片使能信号可利用未使用的地址位。为了说明这一点，假
设图 2-4中的 8?4存储器被用到一个 6位地址总线的系统中，
而且，进一步假设这个芯片对应的单元为 0到 7（ 00 000到 00
0111）。则地址位 A2,A1和 A0可以用于选中存储芯片中的
某个单元，而 A5,A4和 A3在芯片有效时一定要是 000。
Chapter 2 Organization of Computers
计算机专业英语 2-47
2.3.4 Multibyte Data Organization
Many data formats use more than one 8-bit byte to represent a value,
whether it is an integer,floating point number,or character string,
Most CPUs assign addresses to 8-bit memory locations,so these
values must be stored in more than one location,It is necessary for
every CPU to define the order it expects for the data in these
locations.
许多数据格式使用多个字节（一个字节 8位）来表示一个数据，
而不管此数值是整型数、浮点数还是字符串。由于大多数
CPU给 8位的存储器单元分配地址，因此这些值必须存储在多
个单元中，每个 CPU必须定义数据在这些单元中的顺序。
Chapter 2 Organization of Computers
计算机专业英语 2-48
2.3.4 Multibyte Data Organization
There are two commonly used organizations for multibyte data,big
endian and little endian,In big endian format,the most significant
byte of a value is stored in location X,the following byte in
location X+l,and so on,For example,the hexadecimal value 0102
0304H (H for hexadecimal) would be stored,starting in location
100H,as shown in Table 2-1(a).
有两种常用的多字节数据排列顺序：高位优先和低位优先。依照高位优
先格式，一个数值的最高字节存储在单元 X中，次高字节存储在单元 X+1
中，依次类推。例如，十六进制数 01020304H(H表示十六进制 )从单元
100h开始存储，则存储结果如表 2-1(a)所示。
Chapter 2 Organization of Computers
计算机专业英语 2-49
2.3.4 Multibyte Data Organization
In little endian,the order is reversed,The least significant byte is
stored in location X,the next byte in location X+1,and so on,The
same value,in little endian format,is shown in Table 2-1(b).
依照低位优先格式，顺序正好相反。最低字节存储在单
元 X中，次字节存储在单元 X+1中，依次类推。上例中的
同一值，以低位优先格式存储，如表 2-1(b)所示。
Chapter 2 Organization of Computers
计算机专业英语 2-50
2.3.4 Multibyte Data Organization
The same organizations can be used for bits within a byte,In big
endian organization,bit 0 is the rightmost bit of a byte,the left most
bit is bit 7,In little endian organization,the leftmost bit is bit 0 and
bit 7 is the rightmost bit.
同样的组织方式可用于一个字节中的不同位上。在高位优先
结构中，位 0代表字节中最右边的位，最左边的位是第 7位。
在低位优先结构中，最左边的位是 0，最右边的位是 7。
Chapter 2 Organization of Computers
计算机专业英语 2-51
2.3.4 Multibyte Data Organization
Which endian organization is used for bytes and words does not impact the
performance of the CPU and computer system,As long as the CPU is designed to
handle a specific format,neither is better than the other,The main problem comes
in transferring data between computers with different endian organizations,For
example,if a computer with little endian organization transfers the value 0102
0304H to a computer with big endian organization without converting the data,the
big endian computer will read the value as 0403 0201H,There are programs which
can convert data files from one format to the other,and some microprocessors have
special instructions to perform the conversion.
对于字节和字而言，无论使用哪一种排列组织方式都不会影响 CPU和计算机
系统的性能。只要设计 CPU处理一种特定的格式，就不存在谁比谁强的问题，
主要的问题在于具有不同排列组织方式的 CPU之间传输数据的问题，例如，
如果一个低位优先结构的计算机传输 0102 0304H的数据给一个高位优先结构
的计算机，而没有转换数据，那么该高位优先结构计算机读出的值为 0403
0201H。有程序可以将两种时局文件进行格式转换，并且某些处理器有特殊
的指令可以执行这种转换。
Chapter 2 Organization of Computers
计算机专业英语 2-52
2.3.4 Multibyte Data Organization
One other issue of concern for multibyte words is alignment,Modern
microprocessors can read in more than one byte of data at a time,For example,the
Motorola 68040 microprocessor can read in four bytes simultaneously,However,
the four bytes must be in consecutive locations that have the same address except
for the two least significant bits,This CPU could read locations 100,101,102,and
103 simultaneously,but not locations 101,102,103,and 104,This case would
require two read operations,one for locations 100 (not needed),101,102,and 103,
and the other for 104,105 (not needed),106 (not needed),and 107 (not needed).
多字节的另一个值得关注的问题是对齐问题。现代微处理器在某一时刻可以
读出多个字节。例如，摩托罗拉 68040微处理器能同时读入 4个字节的数据，
然而，这 4个字节必须在连续的单元中，它们的地址除了最低两位不同之外，
其余的位均相同。该 CPU可以同时读单元 100,101,102和 103，但不能同时
读单元 101,102,103和 104，后者需要两个读操作，一个操作读 100（不需
要的）,101,102和 103，另一个读 104,105（不需要的）,106（不需要的）
和 107（不需要的）。
Chapter 2 Organization of Computers
计算机专业英语 2-53
2.3.4 Multibyte Data Organization
Alignment simply means storing multibyte values in locations such
that they begin at a location that also begins a multibyte read block,
In this example,this means beginning multibyte values at memory
locations that have addresses evenly divisible by four,thus
guaranteeing that a four-byte value can be accessed by a single read
operation.
对齐简单地说就使存储多字节值的起始单元刚好是某个多字
节读取模块的开始单元。在这个例子中，意味着多字节值开
始存储的单元的地址要能被 4整除，这样就保证该 4字节值可
在单一的一个读操作中存取到。
Chapter 2 Organization of Computers
计算机专业英语 2-54
2.3.4 Multibyte Data Organization
Some CPUs,particularly RISC CPUs,require all data to be aligned,
Other CPUs do not; they can usually align data internally,In general,
nonaligned CPUs have more compact programs,because no
locations are left unused by alignment,However,aligned CPUs can
have better performance because they may need fewer memory read
operations to fetch data and instructions.
一些 CPU，特别是精简指令系统 CPU，需要所有的数据都对
齐。其它的 CPU不要求这样，它们通常能够在内部将数据对
齐。一般来说，不要求对齐的 CPU具有更紧凑的程序，因为
没有单元因为要对齐而闲置不用。然而，对齐的 CPU具有更
好的性能，因为他们读取指令和数据是需要更少的存储器读
操作。
Chapter 2 Organization of Computers
计算机专业英语 2-55
2.3.5 Beyond the Basics（ 基本功能的拓展 ）
The memory subsystem described in this chapter is sufficient for small,embedded
computers,Personal computers and mainframes,however,require more complex
hierarchical configurations,These computers include small,high-speed cache
memory,The computer loads data from the physical memory into the cache; the
processor can access data in the cache more quickly than it can access the same
data in physical memory,Many microprocessors include some cache memory right
on the processor chip,A computer that includes cache memory must also have a
cache controller to move data between the cache and physical memory.
本章描述的存储器子系统对于较小的、嵌入式计算机而言是足够的。然
而，个人电脑和大型主机，需要更加复杂的层次结构。这些计算机包含
体积小的、高速的高速缓冲存储器。计算机将数据从物理存储器中装载
到高速缓冲中：处理器在高速缓冲中访问数据比在物理存储器中快得多。
许多微处理器就在处理器芯片中含有一些高速缓冲存储器。含有高速缓
冲存储器的计算机同时也要有一个高速缓冲控制器，用来在高速缓冲和
物理存储器间传输数据。
Chapter 2 Organization of Computers
计算机专业英语 2-56
2.3.5 Beyond the Basics
At the other extreme,modern computers include virtual memory,
This mechanism uses a hard disk as a part of the computer's memory,
expending the memory space of the computer while minimizing cost,
since a byte of hard disk costs less than a byte of RAM,As with the
cache,virtual memory needs a controller to move data between
physical memory and the hard disk,
在另一端，现代计算机还具有一个虚拟存储器。这种机制用硬
盘充当计算机存储器的一部分，扩大了计算机的存储空间，而
且降低了价格，因为一个硬盘字节的价格比一个 RAM字节要
便宜的多。同高速缓冲一样，虚拟存储器也需要一个控制器以
便在物理存储器和虚拟存储器之间传输数据。
Chapter 2 Organization of Computers
计算机专业英语 2-57
2.4 I/O Subsystem Organization and Interfacing
New Words & Expressions：
homogeneous adj.同类的,均一的
circuitry n.电路,线路
head n.磁头
wait state 等待状态
interrupt 中断
DMA=Direct Memory Access 直接存储器访问
Chapter 2 Organization of Computers
计算机专业英语 2-58
2.4 I/O Subsystem Organization and Interfacing
The CPU treats memory as homogeneous,From the CPU's perspective,each
location is read from and written to in exactly the same way,Each memory
location performs the same function--it stores a data value or an instruction for
use by the CPU.
CPU把存储器看作是同构的。从 CPU的角度来看，每一个单元的读操作和写
操作都是一样的，每一个单元执行同样的功能，即存储 CPU使用的数据或指
令。
Input/output (I/O) devices,on the other hand,are very
different,A personal computer's keyboard and hard disk
perform vastly different functions,yet both are part of the I/O
subsystem,Fortunately for the system designer,the interfaces
between the CPU and the I/O devices are very similar.
另一方面，输入 /输出设备是很不一样的。个人电脑的键盘和硬盘执行的
是千差万别的功能，但它们同是 I/O子系统的一部分。对系统设计者而言，
幸运的是 CPU和各 I/O设备之间的接口是非常相似的。
Chapter 2 Organization of Computers
计算机专业英语 2-59
2.4 I/O Subsystem Organization and Interfacing
As shown in Figure 2-1,each I/O device is connected to the
computer system's address,data,and control buses,Each I/O
device includes I/O interface circuitry; it is actually this circuitry
that interacts with the buses,The circuitry also interacts with the
actual I/O device to transfer data.
如图 2-1所示，每一个 I/O设备与计算机系统的地址总线、数据
总线和控制总线相连接，它们都包括 I/O接口电路，与总线交
互的实际上正是这一电路，同时它与实际的 I/O设备交互来传
输数据。
Chapter 2 Organization of Computers
计算机专业英语 2-60
2.4 I/O Subsystem Organization and Interfacing
Figure 2-7 shows the generic interface circuitry for an input
device,such as a keyboard,The data from the input device goes
to the tri-state buffers,When the values on the address and
control buses are correct,the buffers are enabled and data passes
on to the data bus,The CPU can then read in this data,When the
conditions are not right,the logic block does not enable the
buffers; they are tri-stated and do not place data onto the bus.
图 2-7显示了一个输入设备（比如键盘）的一般接口电路。从
输入设备来的数据传送到三态缓冲器，当地址总线和控制总
线上的值正确时，缓冲器设为有效，数据传到数据总线上，
然后 CPU可以读取数据。当条件不正确时，逻辑块不会使缓
冲器有效，它们保持高阻态，而且不把数据传到总线上。
Chapter 2 Organization of Computers
计算机专业英语 2-61
2.4 I/O Subsystem Organization and Interfacing
The key to this design is the enable logic,Just as every memory
location has a unique address,each I/O device also has a unique
address,The enable logic must not enable the buffers unless it
receives the correct address from the address bus,It must also
get the correct control signals from the control bus,For an input
device,an RD (or RD') signal must be asserted (as well as the
IO/signal,or equivalent,in systems with isolated I/O).
这一设计的关键在于使能逻辑。正如每一个存储单元都有一个
惟一的地址一样，每一个 I/O设备也有一个惟一的地址。除非
从地址总线得到了正确的地址，否则使能逻辑不置缓冲器有效。
同时，它还必须从控制总线上得到正确的控制信号。对于一个
输入设备,RD(或者 RD')信号必须有效（在独立系统中，还有
信号，或其他等效的信号）。
Chapter 2 Organization of Computers
计算机专业英语 2-62
2.4 I/O Subsystem Organization and Interfacing
The design of the interface circuitry for an output device,such as a computer
monitor,is somewhat different than that for the input device,As shown in
Figure 2-8,the tri-state buffers are replaced by a register,The tri-state buffers
are used in input device interfaces to make sure that no more than one device
writes data to the bus at any time,Since the output devices read data from the
bus,rather that write data to it,they don't need the buffers,The data can be
made available to all output devices; only the device with the correct address
will read it in.
输出设备（如显示器）接口电路的设计与输入设备的设计有所
不同。如图 2-8所示，寄存器代替了三态缓冲器。输入设备中使
用三态缓冲器是为了确保在任何时刻都只有一个设备向总线写
数据，而输出设备是从总线读取数据，不是写数据，因此不需
要缓冲器。数据对于所有的输出设备都可获得，但只有具有正
确地址的设备才会读取它。
Chapter 2 Organization of Computers
计算机专业英语 2-63
2.4 I/O Subsystem Organization and Interfacing
The load logic plays the role of the enable logic in the input device
interface,When this logic receives the correct address and control
signals,it asserts the LD signal of the register,causing it to read data
from the system's data bus,The output device can then read the data
from the register at its leisure while the CPU performs other tasks,
装载逻辑发挥着输入设备接口中使能逻辑的作用。当此逻辑获
得正确的地址信号和控制信号后，它发出寄存器的 LD信号，
促使它从系统数据总线上读取数据。然后输出设备可以在其空
闲的时候从寄存器中读取该数据，同时 CPU可以执行其他的任
务。
Chapter 2 Organization of Computers
计算机专业英语 2-64
2.4 I/O Subsystem Organization and Interfacing
A variant of this design replaces the register with tri-state
buffers,The same logic used to load the register is used to enable
the tri-state buffers instead,Although this can work for some
designs,the output device must read in data while the buffers
are enabled,Once they are disabled,the outputs of the buffers
are tri-stated and the data is no longer available to the output
device.
该设计也可以用三态缓冲器代替寄存器。装载寄存器的逻辑同
样用于使能三态缓冲器。虽然对于某些设计这是可行的，但是
输出设备必须在缓冲器有效时读入数据。一旦缓冲器被禁止，
其输出就是三态，该数据也就不再能够供输出设备使用。
Chapter 2 Organization of Computers
计算机专业英语 2-65
2.4 I/O Subsystem Organization and Interfacing
Some devices are used for both input and output,A personal
computer's hard disk drive falls into this category,Such a device
requires a combined interface that is essentially two interfaces,one
for input and the other for output,Some logic elements,such as the
gates that check the address on the address bus,can be used to
generate both the buffer enable and register load signals
有些设备既用于输入又用于输出，个人电脑中的硬盘驱动器
就属于这一类。这样的设备需要一个组合接口，本质上是两
个接口，一个用于输入，另一个用于输出。一些逻辑元件
（比如检查地址总线上的地址是否正确的门电路）既可以用
来产生缓冲器的使能信号，有可以用来产生寄存器的装载信
号。
Chapter 2 Organization of Computers
计算机专业英语 2-66
2.4 I/O Subsystem Organization and Interfacing
I/O devices are much slower than CPUs and memory,For this
reason,they can have timing problems when interacting with the
CPU,To illustrate this,consider what happens when a CPU wants to
read data from a disk,It may take the disk drive several milliseconds
to position its heads properly to read the desired value,In this time,
the CPU could have read in invalid data and fetched,decoded,and
executed thousands of instructions.
I/O设备比 CPU和存储器慢得多。基于这个原因，当它们与
CPU交互时，就可能存在时序上的问题。为了说明这一点，
考虑当 CPU想要从硬盘中读取数据时会发生的情况，这可能
要消耗磁盘驱动器几个毫秒来正确的定位磁头，以便读取想
要的数值，而在这段时间里,CPU可能已经读入了不正确的
数据，并且读取、译解和执行了成千上万条指令。
Chapter 2 Organization of Computers
计算机专业英语 2-67
2.4 I/O Subsystem Organization and Interfacing
Most CPUs have a control input signal called READY (or something
similar),Normally this input is high,When the CPU outputs the
address of the I/O device and the correct control signals,enabling the
tri-state buffers of the I/O device interface,the I/O device sets READY
low,The CPU reads this signal and continues to output the same
address and control signals,which cause the buffers to remain enabled,
In the hard disk drive example,the drive rotates the disk and positions
its read heads until it reads the desired data,
大多数 CPU都有一个控制输入信号，叫做就绪信号（ READY）（或其他意
思相近的名称），通常它为高电平。当 CPU输出某 I/O设备的地址和正确的
控制信号，促使 I/O设备接口的三态缓冲器有效时，该 I/O设备置 READY信
号为低电平。 CPU读取这一信号，并且继续输出同样的地址信号和控制信号，
使缓冲器保持有效。在硬盘驱动器的例子中，此时驱动器旋转磁头，并且定
位读写头，直到读到想要要的数据为止。
Chapter 2 Organization of Computers
计算机专业英语 2-68
2.4 I/O Subsystem Organization and Interfacing
The CPU then reads the data from the bus and continues its
normal operation,The extra clock cycles generated by having
READY set low are called wait states,CPUs can also use the
READY signal to synchronize data transfers with the memory
subsystem.
然后它通过缓冲器将数据输出到数据总线上，并重新设置
READY为高电平。这时 CPU才从总线上读入数据，之后继续它
的正确操作。设置 READY为低电平而生成的附加时钟周期叫做
等待状态。 CPU同样也可以使用 READY信号来同步与存储器子
系统之间的数据传输。
Chapter 2 Organization of Computers
计算机专业英语 2-69
2.4 I/O Subsystem Organization and Interfacing
These I/O interfaces are fine for small computers,such as the
microwave oven controller,but they suffer from poor performance in
larger computer systems,In all but the smallest systems,it is not
acceptable for the CPU to have to wait thousands of clock cycles for
data from an I/O device,Many systems use interrupts so they can
perform useful work while waiting for the much slower I/O devices,
这些 I/O接口对于小型的计算机而言已经很好了，比如说微波
炉控制器，但是在大型的计算机系统中它们的性能则很差。
在除最小系统以外的所有系统中，让 CPU等待成千上万个时
钟周期方从 I/O设备中得到数据是不能接收的，为此，许多系
统都使用了中断机制,以便 CPU在等待慢得多的 I/O设备时，可
以执行其他有用的工作。
Chapter 2 Organization of Computers
计算机专业英语 2-70
2.4 I/O Subsystem Organization and Interfacing
These I/O interfaces are also not suited to large data transfers,In the
systems in this chapter,each byte of data transferred between an I/O
device and memory must pass through the CPU,This is inefficient
for many common operations,such as loading a program from disk
into memory,Direct memory access,DMA,is a method used to
bypass the CPU in these transfers,thus performing them much more
quickly,
这些 I/O接口也不适合大量的数据传输。在本章的系统中，
I/O设备和存储器之间传输的每一个字节都必须通过 CPU，这
对于许多常见的操作（例如从磁盘向主机存装载一个程序）
来说效率低下。直接存储器访问就是在数据传输中绕过 CPU
的一种方法，因此执行起来速度很快。
Chapter 2 Organization of Computers
计算机专业英语 2-71
计算机英语专业词汇的构成
专业词汇的构成
派生词
(derivation)
复合词
(compounding)
混成词
(blending)
前缀
缩略词
(shortening)
后缀 压缩和省略 缩写
借用词
Chapter 2 Organization of Computers
计算机专业英语 2-72
一、派生词 (derivation)
1．前缀
采用前缀构成的单词在计算机专业英语中占了很大比例，通过下面的实例可以了解
这些常用的前缀构成的单词。
multi-多 hyper-超级 super 超级
multiprogram 多道程序 hypercube 超立方 superhighway 超级公路
inter-相互、在,..间 micro-微型 tele-远程的
interface接口、界面 microprocessor 微处理器 telephone 电话
interlace 隔行扫描 microkernel 微内核 teletext 图文电视
单词前缀还有很多，其构成可以同义而不同源 (如拉丁、希腊 )，可以互换，例如：
multi,poly 相当于 many 如, multimedia多媒体,polytechnic各种工艺的
uni,mono 相当于 single 如, unicode统一的字符编码标准,monochrome单色
bi,di 相当于 twice 如, binomial 二项式,dibit双位
equi,iso 相当于 equal 如, equality等同性,isochromatic等色的,
simili,homo 相当于 same 如, similarity类似,homogeneous同类的
semi,hemi 相当于 half 如, semiconductor半导体,hemicycle半圆形
hyper,super 相当于 over 如, hypertext超文本,supercomputer超级计算机
Chapter 2 Organization of Computers
计算机专业英语 2-73
一、派生词 (derivation)
2．后缀
后缀是在单词后部加上构词结构，形成新的单词。如,
-scope 探测仪器 -meter 计量仪器 -graph 记录仪器
microscope显微镜 barometer 气压表 tomograph X线体层照相
telescope 望远镜 telemeter 测距仪 telegraph 电报
spectroscope 分光镜 spectrometer 分光仪 spectrograph 分光摄像
仪
-able可能的 -ware 件 (部件 ) -ity 性质
enable 允许、使能 hardware 硬件 reliability 可靠性
disable 禁止、不能 software 软件 availability 可用性
programmable 可编程的 firmware 固件 accountability 可核查性
portable 便携的 groupware 组件 integrity 完整性
scalable 可缩放的 freeware 赠件 confidentiality 保密性
Chapter 2 Organization of Computers
计算机专业英语 2-74
二、复合词 (compounding)
复合词是科技英语中另一大类词汇，其组成面广，通常分为复合名词、复合形容词、
复合动词等。复合词通常以小横杠,-”连接单词构成，或者采用短语构成。有的复
合词进一步发展，去掉了小横杠,并经过缩略成为另一类词类，即混成词。复合词的
实例有,
-based基于，以 …… 为基础 -centric 以 …… 为中心的
rate-based 基于速率的 client-centric 以客户为中心的
credit-based 基于信誉的 user-centric 以用户为中心的
file-based 基于文件的 host-centered 以主机为中心的
-oriented 面向 …… 的 -free 自由的，无关的
object-oriented 面向对象的 lead-free 无线的
market-oriented 市场导向 jumper-free 无跳线的
process-oriented 面向进程的 paper-free 无纸的
info-信息，与信息有关的 envent-事件的
info-channel 信息通道 envent-driven 事件驱动的
info-tree 信息、树 envent-oriented 面向事件的
info-world 信息世界 event-based 基于事件的
Chapter 2 Organization of Computers
计算机专业英语 2-75
二、复合词 (compounding)
此外，以名词 + 动词 -ing 构成的复合形容词形成了一种典型的替换关系，即可以根
据需要在结构中代入同一词类而构成新词，它们多为动宾关系。如,
man-carrying aircraft 载人飞船 earth-moving machine 推土机
time-consuming operation 耗时操作 ocean-going freighter 远洋货舱
然而，必须注意，复合词并非随意可以构造，否则会形成一种非正常的英语句子结
构。虽然上述例子给出了多个连接单词组成的复合词，但不提倡这种冗长的复合方
式。对于多个单词的非连线形式，要注意其顺序和主要针对对象。
此外还应当注意，有时加连字符的复合词与不加连字符的词汇词意是不同的，必须
通过文章的上下文推断。如,
force-feed 强迫接受（ vt.），而 force feed 则为“加压润滑”。
随着词汇的专用化，复合词中间的连接符被省略掉，形成了一个单词，例如：
videotape 录像带 fanin 扇入 fanout 扇出
online 在线 onboard 在板 login 登录
logout 撤消 pushup 拉高 popup 弹出
Chapter 2 Organization of Computers
计算机专业英语 2-76
三, 混成词 (blending)
混成词不论在公共英语还是科技英语中也大量出现，也有人将它们称为缩
合词（与缩略词区别）、融会词，它们多是名词，也有地方将其作为动词
用，对这类词汇可以通过其构词规律和词素进行理解。这类词汇将两个单
词的前部拼接、前后拼接或者将一个单词前部与另一词拼接构成新的词汇，
实例有,
brunch (breakfast + lunch) 早中饭
smog (smoke +fog) 烟雾
codec (coder+decoder) 编码译码器
compuser (computer+user) 计算机用户
transeiver (transmitter+receiver) 收发机
syscall (system+call) 系统调用
mechatronics (mechanical+electronic) 机械电子学
calputer (calculator+computer) 计算器式电脑
Chapter 2 Organization of Computers
计算机专业英语 2-77
四、缩略词 (shortening)
缩略词是将较长的英语单词取其首部或者主干构成与原词同义的短单词，或
者将组成词汇短语的各个单词的首字母拼接为一个大写字母的字符串。随着
科技发展，缩略词在文章索引、前言、摘要、文摘、电报、说明书、商标等
科技文章中频繁采用 。
1．压缩和省略
将某些太长、难拼、难记、使用频繁的单词压缩成一个短小的单词，
或取其头部、或取其关键音节。如,
f1u=influenza 流感 1ab=laboratory 实验室
math=mathematics 数学 iff=if only if 当且仅当
rhino=rhinoceros 犀牛 ad=advertisement 广告
Chapter 2 Organization of Computers
计算机专业英语 2-78
四、缩略词 (shortening)
2．缩写 (acronym)
将某些词组和单词集合中每个实意单词的第一或者首部几个字母重新组合，
组成为一个新的词汇，作为专用词汇使用。在应用中它形成三种类型，即,
1) 通常以小写字母出现，并作为常规单词
flops (floating-point Operation Per Second) 每秒浮点运算次数
spool (simultaneous peripheral operation on line) 假脱机
2) 以大写字母出现，具有主体发音音节
BASIC (Beginner's All-purpose Symbolic Instruction Code) 初学者通用符号指令代码
FORTRAN (Formula Translation) 公式翻译 (语言 )
COBOL (Common Business Oriented Language) 面向商务的通用语言
3) 以大写字母出现，没有读音音节，仅为字母头缩写
RISC (Reduced Instruction Set Computer) 精简指令集计算机
CISC (Complex Instruction Set Computer) 复杂指令集计算机
ADE (Application Development Environment) 应用开发环境
PCB (Process Control Block) 进程控制块
CGA (Color Graphics Adapter) 彩色图形适配器
Chapter 2 Organization of Computers
计算机专业英语 2-79
五、借用词
借用词一般来自厂商名、商标名、产品代号名、发明者名、地名等，它
通过将普通公共英语词汇演变成专业词意而实现。有的则是将原来已经
有的词汇赋予新的含义。例如,
woofer 低音喇叭 tweeter 高音喇叭 flag标志、状态
cache 高速缓存 semaphore 信号量 firewall 防火墙
mailbomb 邮件炸弹 scratch pad 高速缓存 fitfall 专用程序入口
在现代科技英语中借用了大量的公共英语词汇、日常生活中的常用词汇，
而且，以西方特有的幽默和结构讲述科技内容。这时，读者必须在努力
扩大自己专业词汇的同时，也要掌握和丰富自己的生活词汇，并在阅读
和翻译时正确采用适当的含义。
Chapter 2 Organization of
Computers
Chapter 2 Organization of Computers
计算机专业英语 2-2
Key points:
useful terms and organization
of computers
Difficult points:
describing the organization of
computers
Chapter 2 Organization of Computers
计算机专业英语 2-3
Requirements:
1,Terms of computer hardware
2,Organization of computers and their functions
3,掌握专业词汇的构成规律，特别是常用词缀及复合词
的构成
Chapter 2 Organization of Computers
计算机专业英语 2-4
New Words & Expressions:
instruction cycle 指令周期 decode vt.解码,译解
bus n,总线 pins n.插脚,管脚
uppermost adj.最高的； adv.在最上 address bus 地址总线
data bus 数据总线 via prep.经,通过,经由
multibit 多位 bidirectional 双向的
unidirectional 单向的 hierarchy n.层次，层级
microprocessor n.微处理器 register n.寄存器
timing n.定时；时序；时间选择 synchronize vt.使,..同步
assert vt.主张，发出 deassert vt,撤销
trigger vt.引发,引起,触发 map v.映射
port n.端口
2.1 Basic Organization of Computers
Abbreviations:
CPU(Central Processing Unit) 中央处理器
I/O(Input/Output) 输入输出 (设备 )
Chapter 2 Organization of Computers
计算机专业英语 2-5
2.1 Basic Organization of Computers
C PU
Mem ory
S u b s y s tem
I /O
D evice
I /O
D evice
…
I /O S u b s y s tem
A d d r es s Bu s
D at a Bu s
C on tr ol Bu s
Fig.2-1 Generic computer organization
Chapter 2 Organization of Computers
计算机专业英语 2-6
2.1 Basic Organization of Computers
Most computer systems,from the embedded controllers found in
automobiles and consumer appliances to personal computers
and mainframes,have the same basic organization,This
organization has three main components,the CPU,the memory
subsystem,and the I/O subsystem,The generic organization of
these components is shown in Figure 2-1.
大多数计算机系统，从汽车和日用电器中的嵌入式控制器到
个人计算机和大型主机，都具有相同的基本组成。其基本组
成包括三个主要部件,CPU、存储器子系统和 I/O子系统。这
些部件的一般组成如图 2-1所示。
Chapter 2 Organization of Computers
计算机专业英语 2-7
Physically,a bus is a set of wires,The components of the computer are
connected to the buses,To send information from one component to another,
the source component outputs data onto the bus,The destination
component then inputs this data from the bus,As the complexity of a
computer system increases,it becomes more efficient (in terms of
minimizing connections) at using buses rather than direct connections
between every pair of devices,Buses use less space on a circuit board and
require less power than a large number of direct connections,They also
require fewer pins on the chip or chips that comprise the CPU.
2.1.1 System Buses
从物理上来说，总线就是一组导线。计算机的部件就是连在总线上的。为了将信息
从一个部件传到另一个部件，源部件先将数据输出到总线上，然后目标部件再从总
线上接受这些数据。随着计算机系统复杂性的不断增长，使用总线比每个设备对之
间直接连接要有效得多（就减少连接数量而言）。与大量的直接连接相比，总线使
用较少的电路板空间，耗能更少，并且在芯片或组成 CPU的芯片组上需要较少的引
脚。
Chapter 2 Organization of Computers
计算机专业英语 2-8
The system shown in Figure 2-1 has three buses,The uppermost bus in this figure
is the address bus,When the CPU reads data or instructions from or writes data to
memory,it must specify the address of the memory location it wishes to access,It
outputs this address to the address bus; memory inputs this address from the
address bus and use it to access the proper memory location,Each I/O devices,
such as a keyboard,monitor,or disk drive,has a unique address as well,When
accessing an I/O device,the CPU places the address of the device on the address
bus,Each device can read the address off of the bus and determine whether it is
the device being accessed by the CPU,Unlike the other buses,the address bus
always receives data from the CPU; the CPU never reads the address bus.
图 2-1所示的系统包括三组总线。最上面的是地址总线。当 CPU从存储器读取数据或
指令，或写数据到存储器时，它必须指明将要访问的存储器单元地址。 CPU将地址
输出到地址总线上，而存储器从地址总线上读取地址，并且用它来访问正确的存储
单元。每个 I/O设备，比如键盘、显示器或者磁盘，同样都有一个唯一的地址。当访
问某个 I/O设备时,CPU将此设备的地址放到地址总线上。每一个设备均从总线上读
取地址并且判断自己是否就是 CPU正要访问的设备。与其他总线不同，地址总线总
是从 CPU上接收信息，而 CPU从不读取地址总线。
2.1.1 System Buses
Chapter 2 Organization of Computers
计算机专业英语 2-9
Data is transferred via the data bus,When the CPU fetches data
from memory,it first outputs the memory address on its address
bus,Then memory outputs the data onto the data bus; the CPU can
then read the data from the data bus,When writing data to memory,
the CPU first outputs the address onto the address bus,then
outputs the data onto the data bus,Memory then reads and stores
the data at the proper location,The processes for reading data from
and writing data to the I/O devices are similar.
数据是通过数据总线传送的。当 CPU从存储器中取数据时，它首先把存储器
地址输出到地址总线上，然后存储器将数据输出到数据总线上，这样 CPU就
可以从数据总线上读取数据了。当 CPU向存储器中写数据时，它首先将地址
输出到地址总线上，然后把数据输出到数据总线上，这样存储器就可以从数
据总线上读取数据并将它存储到正确的单元中。对 I/O设备读写数据的过程
与此类似。
2.1.1 System Buses
Chapter 2 Organization of Computers
计算机专业英语 2-10
The control bus is different from the other two buses,The address bus consists of
n lines,which combine to transmit one n-bit address value,Similarly,the lines of
the data bus work together to transmit a single multibit value,In contrast,the
control bus is a collection of individual control signals,These signals indicate
whether data is to be read into or written out of the CPU,whether the CPU is
accessing memory or an I/O device,and whether the I/O device or memory is
ready to transfer data,Although this bus is shown as bidirectional in Figure 2-1,it
is really a collection of (mostly) unidirectional signals,Most of these signals are
output from the CPU to the memory and I/O subsystems,although a few are
output by these subsystems to the CPU,We examine these signals in more detail
when we look at the instruction cycle and the subsystem interface.
控制总线与以上两种总线都不相同。地址总线由 n根线构成,n根线联合传送一个 n位
的地址值。类似地，数据总线的各条线合起来传输一个单独的多位值。相反，控制
总线是单根控制信号的集合。这些信号用来指示数据是要读入 CPU还是要从 CPU写
出,CPU是要访问存储器还是要访问 I/O设备，是 I/O设备还是存储器已就绪要传送
数据等等。虽然图 2-1所示的控制总线看起来是双向的，但它实际上（主要）是单向
（大多数都是）信号的集合。大多数信号是从 CPU输出到存储器与 I/O子系统的，只
有少数是从这些子系统输出到 CPU的。在介绍指令周期和子系统接口时，我们将详
细地讨论这些信号。
2.1.1 System Buses
Chapter 2 Organization of Computers
计算机专业英语 2-11
A system may have a hierarchy of buses,For example,it may use
its address,data,and control buses to access memory,and an I/O
controller,The I/O controller,in turn,may access all I/O devices
using a second bus,often called an I/O bus or a local bus,
一个系统可能具有分层次的总线。例如，它可能使用地址、数
据和控制总线来访问存储器和 I/O控制器。 I/O控制器可能依次
使用第二级总线来访问所有的 I/O设备，第二级总线通常称为
I/O总线或者局部总线。
2.1.1 System Buses
Chapter 2 Organization of Computers
计算机专业英语 2-12
The instruction cycle is the procedure a microprocessor goes through to process
an instruction,First the microprocessor fetches,or reads,the instruction from
memory,Then it decodes the instruction,determining which instruction it has
fetched,Finally,it performs the operations necessary to execute the instruction,
(Some people also include an additional element in the instruction cycle to store
results,Here,we include that operation as part of the execute function.) Each of
these functions--fetch,decode,and execute--consists of a sequence of one or
more operations.
指令周期是微处理器完成一条指令处理的步骤。首先，微处理器从存储器读
取指令，然后将指令译码，辩明它取的是哪一条指令。最后，它完成必要的
操作来执行指令（有人认为在指令周期中还要包括一个附加的步骤来存储结
果，这里我们把该操作当作执行功能的一部分）。每一个功能 —— 读取、译
码和执行都包括一个或多个操作。
2.1.2 Instruction Cycle
Chapter 2 Organization of Computers
计算机专业英语 2-13
Let's start where the computer starts,with the microprocessor
fetching the instruction from memory,First,the microprocessor
places the address of the instruction on to the address bus,The
memory subsystem inputs this address and decodes it to access the
sired memory location,(We look at how this decoding occurs
when we examine the memory subsystem in more detail later in
this chapter.)
我们从微处理器从存储器中取指令开始讲述。首先，微处理器
把指令的地址放到地址总线上，然后，存储器子系统从总线上
输入该地址并予以译码，去访问指定的存储单元。（译码是如
何进行的，我们将在后面的章节中介绍存储器子系统是更为详
细的讨论。）
2.1.2 Instruction Cycle
Chapter 2 Organization of Computers
计算机专业英语 2-14
After the microprocessor allows sufficient time for memory to decode the
address and access the requested memory location,the microprocessor asserts a
READ control signal,The READ signal is a signal on the control bus which the
microprocessor asserts when it is ready to read data from memory or an I/O
device,(Some processors have a different name for this signal,but all
microprocessors have a signal to perform this function.) Depending on the
microprocessor,the READ signal may be active high (asserted - 1) or active low
(asserted - 0).
当微处理器为存储器留出充足的时间来对地址译码和访问所需的存储单元之
后，微处理器发出一个读（ READ）控制信号。当微处理器准备好可以从存
储器或是 I/O设备读数据时，它就在控制总线上发一个读信号。（一些处理器
对于这个信号有不同的名字，但所有处理器都有这样的信号来执行这个功
能。）根据微处理器的不同，读信号可能是高电平有效（信号 =1），也可能
是低电平有效（信号 =0）。
2.1.2 Instruction Cycle
Chapter 2 Organization of Computers
计算机专业英语 2-15
When the READ signal is asserted,the memory subsystem places
the instruction code to be fetched onto the computer system's data
bus,The microprocessor then inputs this data from the bus and
stores it in one of its internal registers,At this point,the
microprocessor has fetched the instruction.
读信号发出后，存储器子系统就把要取的指令码放到计算机的
数据总线上，微处理器就从数据总线上输入该数据并且将它存
储在其内部的某个寄存器中。至此，微处理器已经取得了指令。
2.1.2 Instruction Cycle
Chapter 2 Organization of Computers
计算机专业英语 2-16
Next,the microprocessor decodes the instruction,Each instruction
may require a different sequence of operations to execute the
instruction,When the microprocessor decodes the instruction,it
determines which instruction it is in order to select the correct
sequence of operations to perform,This is done entirely within the
microprocessor; it does not use the system buses.
接下来，微处理器对这条指令译码。每一条指令可能要有不同
的操作序列来执行。当微处理器对该指令译码是，它确定处理
的是哪一条指令以便选择正确的操作序列去执行。这一步完全
在微处理器内完成，不需要使用系统总线。
2.1.2 Instruction Cycle
Chapter 2 Organization of Computers
计算机专业英语 2-17
Finally,the microprocessor executes the instruction,The sequence of operations
to execute the instruction varies from instruction to instruction,The execute
routine may read data from memory,write data to memory,read data from or
write data to an I/O device,perform only operations within the CPU,or perform
some combination of these operations,We now look at how the computer
performs these operations from a system perspective.
最后，微处理器执行该指令。指令不同，执行的操作序列也不
同。执行过程可以是从存储器读取数据，写数据到存储器，读
或写数据到 I/O设备，执行 CPU内部操作或者执行多个上述操作
的组合。下面我们从系统的角度来看计算机是怎样执行这些操
作的。
2.1.2 Instruction Cycle
Chapter 2 Organization of Computers
计算机专业英语 2-18
To read data from memory,the microprocessor performs the same
sequence of operations it uses to fetch an instruction from memory,
After all,fetching an instruction is simply reading it from memory,
Figure 2-2(a) shows the timing of the operations to read data from
memory.
微处理器从存储器读取数据所执行的操作序列，同从存储器中
去一条指令是一样的。毕竟取指令就是简单地从存储器中读取
它。图 2-2(a)显示了从存储器中读取数据的操作时序。
2.1.2 Instruction Cycle
Chapter 2 Organization of Computers
计算机专业英语 2-19
In Figure 2-2,notice the top symbol,CLK,This is the computer system clock; the
microprocessor uses the system clock to synchronize its operations,The
microprocessor places the address onto the bus at the beginning of a clock cycle,a
0/1 sequence of the system clock,One clock cycle later,to allow time for memory
to decode the address and access its data,the microprocessor asserts the READ
Signal,This causes memory to place its data onto the system data bus,During this
clock cycle,the microprocessor reads the data off the system bus and stores it in
one of its registers,At the end of the clock cycle it removes the address from the
address bus and deasserts the READ signal,Memory then removes the data from
the data bus,completing the memory read operation.
在图 2-2中，注意最上面的符号 CLK，它是计算机的系统时钟，微处理器用系统时钟
使其操作同步。在一个时钟周期（系统时钟的 0/1序列）的开始位置，微处理器将地
址放到总线上。一个时钟周期（允许存储器对地址译码和访问数据的时间）之后，
微处理器才发出读信号。这使得存储器将数据放到数据总线上。在这个时钟周期之
内，微处理器从系统总线上读取数据，并存储到它的某个寄存器中。在这个时钟周
期结束时，微处理器撤消地址总线上的地址，并撤消读信号。然后存储器从数据总
线上撤消数据，也就完成了存储器的读操作。
2.1.2 Instruction Cycle
Chapter 2 Organization of Computers
计算机专业英语 2-20
The timing of the memory write operation is shown in Figure 2-2(b),The
processor places the address and data onto the system buses during the first
clock cycle,The microprocessor then asserts a WRITE control signal (or its
equivalent) at the start of the second clock cycle,Just as the READ signal causes
memory to read data,the WRITE signal triggers memory to store data,Some
time during this cycle,memory writes the data on the data bus to the memory
location whose address is on the address bus,At the end of this cycle,the
processor completes the memory write operation by removing the address and
data from the system buses and deasserting the WRITE signal.
存储器写操作的时序如图 2-2(b)所示。在第一个时钟周期，处理器将地址和
数据放到总线上，然后在第二个时钟周期开始 时发出一个写（ WRITE）控
制信号（或与之等价的信号）。像读信号促使存储器读取数据一样，写信号
促使存储器存储数据。在这个时钟周期的某个时刻，存储器将数据总线上的
数据写入地址总线指示的存储单元内。当这个时钟周期结束，微处理器从系
统总线上撤消地址、数据及写信号后，就完成了存储器的写操作。
2.1.2 Instruction Cycle
Chapter 2 Organization of Computers
计算机专业英语 2-21
The I/O read and write operations are similar to the memory read and write
operations,A processor may use either memory mapped I/O or isolated I/O,If the
processor supports memory mapped I/O,it follows the same sequences of
operations to input or output data as to read data from or write data to memory,
the sequences shown in Figure 2-2,(Remember,in memory mapped I/O,the
processor treats an I/O port as a memory location,so it is reasonable to treat an
I/O data access the same as a memory access.) Processors that use isolated I/O
follow the same process but have a second control signal to distinguish between
I/O and memory accesses,(CPUs that use isolated I/O can have a memory
location and an I/O port with the same address,which makes this extra signal
necessary.)
I/O的读写操作与存储器的读写操作类似。处理器可以使用存储器影射 I/O或者是单
独 I/O。如果处理器支持存储器影射 I/O,则它遵循从存储器读写数据同样的操作顺序，
该顺序如图 2-2所示（记住，在存储器影射 I/O中，处理器把一个 I/O端口当作某个存
储单元，当然 I/O的数据访问同存储器的数据访问一样的）。使用单独 I/O的处理器
遵循同样的处理过程，但是另有一个控制信号用以区别是 I/O访问还是存储器访问
（使用单独 I/O的 CPU允许一个存储单元和某个 I/O端口具有相同的地址，因此需要
这一额外的信号加以区分）。
2.1.2 Instruction Cycle
Chapter 2 Organization of Computers
计算机专业英语 2-22
Finally,consider instructions that are executed entirely within the
microprocessor,The INAC instruction of the Relatively Simple
CPU,and the MOV r1,r2 instruction of the 8085 microprocessor,
can be executed without accessing memory or I/O devices,As
with instruction decoding,the execution of these instructions does
not make use of the system buses.
最后，考虑一下完全在微处理器内部执行的指令。相对简单
CPU的 INAC指令和 8085的 MOV r1,r2指令的执行都不要访问
存储器和 I/O设备。按照指令译码的结果，这些指令的执行不会
用到系统总线。
2.1.2 Instruction Cycle
Chapter 2 Organization of Computers
计算机专业英语 2-23
New Words & Expressions:
latch v.闭锁,锁存 program counter 程序计数器
instruction register 指令寄存器 operand n,操作数
increment n.增量,加 1 flag register 标志寄存器
pipeline n.流水线 microsequenced 微层序的
local bus 局部总线
Abbreviations:
ALU (Arithmetic Logic Unit) 算术逻辑单元
2.2 CPU ORGANIZATION
Chapter 2 Organization of Computers
计算机专业英语 2-24
The CPU controls the computer,It fetches instructions from memory,
supplying the address and control signals needed by memory to access its
data,The CPU decodes the instruction and controls the execution procedure,
It performs some operations internally,and supplies the address,data,and
control signals needed by memory and I/O devices to execute the instruction,
Nothing happens in the computer unless the CPU causes it to happen,
CPU控制整个计算机。它从存储器中取指令，提供存储器需要
的地址和控制信号。 CPU对指令译码并且控制整个执行过程。
它执行一些内部操作，并且为存储器和 I/O设备执行指令提供必
要的地址、数据和控制信号。除非 CPU激发，否则，计算机什
么事情都不会发生。
2.2 CPU ORGANIZATION
Chapter 2 Organization of Computers
计算机专业英语 2-25
Internally,the CPU has three sections,as shown in Figure 2-3,The register
sections,as its name implies,includes a set of registers and a bus or other
communication mechanism,The registers in a processor's instruction set
architecture are found in this section of the CPU,The system address and data
buses interact with this section of the CPU,The register section also contains
other registers that are not directly accessible by the programmer,The relatively
simple CPU includes registers to latch the address being accessed in memory and
a temporary storage register,as well as other registers that are not a part of its
instruction set architecture.
CPU内部有三大分区，如图 2-3所示。寄存器区,顾名思义，它包括一组寄存
器、一条总线或其他通信机制。微处理器指令集结构中的寄存器就属于 CPU
的这一分区。系统的地址和数据总线与寄存器交互。此分区还包括程序员不
能直接访问的一些寄存器。相对简单 CPU含有寄存器用以锁存正在访问的存
储器地址，还有暂存器以及指令集结构中没有的其他寄存器等。
2.2 CPU ORGANIZATION
Chapter 2 Organization of Computers
计算机专业英语 2-26
During the fetch portion of the instruction cycle,the processor first outputs the
address of the instruction onto the address bus,The processor has a register
called the program counter; the CPU keeps the address of the next instruction to
be fetched in this register,Before the CPU outputs the address onto the system's
address bus,it retrieves the address from the program counter register,At the
end of the instruction fetch,the CPU reads the instruction code from the system
data bus,It stores this value in an internal register,usually called the instruction
register or something similar.
在指令周期的取指阶段，处理器首先将指令的地址输出到地址总线上。处理
器有一个寄存器叫做程序计数器,CPU将下一条要取的指令的地址存放在程
序计数器中。在 CPU将地址输出到系统的地址总线之前，必须从程序计数器
中取出该地址。在指令结束前,CPU从系统时局总线上读取指令码，它把该
指令码存储在某个内部寄存器中，该寄存器通常称作指令寄存器或其他相似
的名字。
2.2 CPU ORGANIZATION
Chapter 2 Organization of Computers
计算机专业英语 2-27
The arithmetic logic unit or ALU performs most arithmetic and logical
operations,such as adding or ADDing values,It receives its operands from
the register section of the CPU and stores its results back in the register
section,Since the ALU must complete its operations within a single clock
cycle,it is constructed using only combinatorial logic,The ADD
instructions in the relatively simple CPU and the 8085 microprocessor use
the ALU during their executions.
算术逻辑单元执行大部分的算术逻辑运算，如加法、逻辑与等
运算。它从 CPU的寄存器取得操作数，然后将运算结果再存回
到寄存器区。由于必须在一个时钟周期内完成操作，因此 ALU
只采用组合逻辑构造而成。相对简单 CPU和 8085微处理器中的
ADD指令在执行中都有使用 ALU。
2.2 CPU ORGANIZATION
Chapter 2 Organization of Computers
计算机专业英语 2-28
Just as the CPU controls the computer (in addition to its other functions),the
control unit controls the CPU,This unit generates the internal control signals that
cause registers to load data,increment or clear their contents,and output their
contents,as well as cause the ALU to perform the correct function,These signals
are shown as control signals in Figure 2-3,The control unit receives some data
values from the register unit,which it uses to generate the control signals,This
data includes the instruction code and the values of some flag registers,
同 CPU控制整个计算机（除了其他功能外）一样，控制单元控制着 CPU。这
个单元产生内部控制信号，促使寄存器装载数据，自动加 1或清零，输出它
的内容，使得 ALU完成正确的操作等等。这些信号作为控制信号显示在图 2-
3中。控制单元从寄存器区取得一些数据用以产生控制信号，这些数据包括
指令码和某些标志寄存器的值。
2.2 CPU ORGANIZATION
Chapter 2 Organization of Computers
计算机专业英语 2-29
The control unit also generates the signals for the system control
bus,such as the READ,WRITE,and signals,A microprocessor
typically performs a sequence of operations to fetch,decode,and
execute an instruction,By asserting these internal and external
control signals in the proper sequence,the control unit causes the
CPU and the rest of the computer to perform the operations
needed to correctly process instructions.
2.2 CPU ORGANIZATION
控制单元也产生系统控制总线上的信号，例如 READ,WRATE,
信号等。典型的一个微处理器执行取指令、译指令和执行指令
等一系列的操作。通过以正确的顺序激发这些内部或外部控制
信号，控制单元使 CPU和计算机的其余部分完成正确处理指令
所需要的操作。
Chapter 2 Organization of Computers
计算机专业英语 2-30
This description of the CPU is incomplete,Current processors
have more complex features that improve their performance,One
such mechanism,the instruction pipeline,allows the CPU to fetch
one instruction while simultaneously executing another instruction.
2.2 CPU ORGANIZATION
以上对 CPU的描述并不完整。现在的处理器拥有更加复杂的特
征以提高其性能。这些机制中有一种是指令流水线技术，它允
许 CPU在执行一条指令的同时取出另一条指令。
Chapter 2 Organization of Computers
计算机专业英语 2-31
In this section we have introduced the CPU from a system
perspective,but we have not discussed its internal design,We
examine the registers,data paths,and control unit,all of which
act together to cause the CPU to properly fetch,decode,and
execute instructions,Microsequenced CPUs have the same
registers,ALUs and data paths as hardwired CPUs,but
completely different control units,
本节我们从系统的角度介绍了 CPU，但我们还没有讨论它的内
部设计。我们描述了 CPU的寄存器、数据通路、控制单元等，
所有部件一起工作使 CPU正确地读取、译码和执行指令。微层
序 CPU具有同硬连线 CPU一样的寄存器,ALU和数据通路，但
二者控制单元完全不同。
2.2 CPU ORGANIZATION
Chapter 2 Organization of Computers
计算机专业英语 2-32
2.3 Memory Subsystem Organization and Interfacing
New Words & Expressions:
multibyte n.多字节 MB n.兆字节
shut off n.切断,关闭 enable n..使能
tri-state 三态 tri-stated 高阻态
dimension n.尺度,维 (数 ) configuration n.构造,结构,配置
as far as 尽；就；至于 high-order 高位
low-order 低位 interleaving n.交叉,交错
contiguous adj.邻近的,接近的 assign vt.分配,指派
big endian 高位优先 little endian 低位优先
hexadecimal adj.十六进制的； n.十六进制 alignment n.对齐方式
leftmost adj.最左边的 rightmost adj.最右边的，最右面的
consecutive adj.连续的,联贯的 cache n.高速缓冲
virtual memory 虚拟存储器 buffer n.缓冲器
ROM(Read Only Memory) 只读存储器
RAM(Random Access Memory) 随机存取存贮器
RISC(Reduced Instruction Set Computer) 精简指令集计算机
Chapter 2 Organization of Computers
计算机专业英语 2-33
2.3 Memory Subsystem Organization and Interfacing
In this section we examine the construction and functions of the
memory subsystem of a computer,We review the different types of
physical memory and the internal organization of their chips,We
discuss the construction of the memory subsystem,as well as
multibyte word organizations and advanced memory organizations.
本节我们将讨论计算机中存储器子系统的结构和功能。我们将
会回顾不同类型的物理存储器及其芯片的内部组成，讨论存储
器子系统的结构，以及多字节的组织和高级存储器的组成。
Chapter 2 Organization of Computers
计算机专业英语 2-34
2.3.1 Types of Memory
The internal organizations of ROM and RAM chips are similar,To
illustrate the simplest organization,a linear organization,consider an
8?2 ROM chip,For simplicity,programming components are not
shown,This chip has three address inputs and two data outputs,and
16 bits of internal storage arranged as eight 2-bit locations.
存储器芯片有两种类型：只读存储器（ ROM）和随机存取存储器
（ RAM）。只读存储器芯片是为数据（此数据可包括程序的指令）只读
的应用而设计的。这些芯片在加入系统之前，就已经被某个外部编程器而
装好数据了。这个工作一旦完成，其数据通常不再改变。 ROM芯片总是
保存有数据，甚至在芯片断电以后。例如，一个微波炉的嵌入式控制器可
以连续运行一个不变的程序。这个程序就存储在一片 ROM上。
Chapter 2 Organization of Computers
计算机专业英语 2-35
Random Access Memory (RAM),also called read/write memory,
can be used to store data that changes,This is the type of memory
referred to as X MB of memory in ads for PCs,Unlike ROM,RAM
chips lose their data once power is shut off,Many computer systems,
including personal computers,include both ROM and RAM.
2.3.1 Types of Memory
随机访问存储器也称为读写存储器，用来存储可以改变的
数据。这就是我们在个人电脑广告上经常看到的 XX MB的
内存所指的那种类型。不像 ROM,RAM芯片一旦掉电，数
据就会丢失。许多计算机系统，包括个人电脑，都同时拥
有 ROM和 RAM。
Chapter 2 Organization of Computers
计算机专业英语 2-36
2.3.2 Internal Chip Organization
The internal organizations of ROM and RAM chips are similar,To
illustrate the simplest organization,a linear organization,consider
an 8?2 ROM chip,For simplicity,programming components are
not shown,This chip has three address inputs and two data outputs,
and 16 bits of internal storage arranged as eight 2-bit locations.
ROM和 RAM芯片的内部组成是相似的。为了说明一个最简
单的组成 —— 线性组成，我们来考虑一个 8?2的 ROM芯片。
为了简化，编成器件没有画出来。这个芯片有三个地址输入
端和两个数据输出端，以及 16位的内部存储元件，它排列成
8个单元，每个单元 2位。
Chapter 2 Organization of Computers
计算机专业英语 2-37
The three address bits are decoded to select one of the eight
locations,but only if the chip enable is active,If CE=0,the
decoder is disabled and no location is selected,The tri-state
buffers for that location's cells are enabled,allowing data to pass
to the output buffers,If both CE and OE set to 1,these buffers
are enabled and the data is output from the chip; otherwise the
outputs are tri-stated.
2.3.2 Internal Chip Organization
三个地址位经过译码，可以选择 8个中的一个，但只有芯片的使能端要有
效才行。如果 CE=0，译码器被禁止，则不选择任何单元。该单元上的三
态缓冲器是有效的，允许数据输出到缓冲器中。如果 CE=1且 OE=1，则
这些缓冲器有效，数据从芯片中输出；否则，输出是高阻态。
Chapter 2 Organization of Computers
计算机专业英语 2-38
As the number of locations increases,the size of the address decoder
needed in a linear organization becomes prohibitively large,To
remedy this problem,the memory chip can be designed using
multiple dimensions of decoding,
2.3.2 Internal Chip Organization
随着单元数量的增加，线性组成中地址译码器的规模变得相
当大。为了补救这一问题，存储器芯片可以设计成使用多维
译码方式。
Chapter 2 Organization of Computers
计算机专业英语 2-39
In larger memory chips,this savings can be significant,Consider a 4096?1
chip,The linear organization will require a 12 to 4096 decoder,the size of
which is proportional to the number of outputs,(The size of an n to 2n
decoder is thus said to be O(2n).) If the chip is organized as a 64?64 two
dimensional array instead,it will have two 6 to 64 decoders,one to select one
of the 64 rows and the other to select one of the 64 cells within the row,The
size of the decoders is proportional to 2?64,or O(2?2n/2) = O(2n/2 +1),For
this chip,the two decoders together are about 3 percent of the size of the one
larger decoder.
2.3.2 Internal Chip Organization
在大型存储器芯片中，这种节省显得至关重要。考虑一个 4096?1芯片，
其线性组成将需要一个 12— 4096译码器，译码器大小与输出的数量成正
比（假定一个 n— 2n译码器的大小是 O(2n)）。如果芯片排列成 64?64的
二维数组，它将有两个 6— 64译码器：一个用来选择 64行中的一行，另一
个用来在选定行中选择 64个单元中的一个单元，该译码器的大小正比于
2?64，或写成 O(2?2n/2)=O(2n/2+1)。对于这个芯片，两个译码器总的大
小约是那个大译码器大小的 3%。
Chapter 2 Organization of Computers
计算机专业英语 2-40
2.3.3 Memory Subsystem Configuration
It is very easy to set up a memory system that consists of a single
chip,We simply connect the address,data,and control signals from
their system buses and the job is done,However,most memory
systems require more than one chip,Following are some methods for
combining memory chips to form a memory subsystem.
构造包含一个简单芯片的存储器是非常容易的，我们只需要简
单地从系统总线上连接地址信号线、数据信号线和控制信号线
就完成了。然而。大多数的存储器系统需要多个芯片，下面是
通过存储器芯片组合来形成存储器子系统的一些方法。
Chapter 2 Organization of Computers
计算机专业英语 2-41
2.3.3 Memory Subsystem Configuration
Two or more chips can be combined to create memory with more bits per location,
This is done by connecting the corresponding address and control signals of the
chips,and connecting their data pins to different bits of the data bus,For example,
two 8?2 chips can be combined to create an 8?4 memory,as shown in Figure 2-4,
Both chips receive the same three address inputs from the bus,as well as the same
chip enable and output enable signals,(For now it is only important to know that
the signals are the same for both chips; we show the logic to generate these signals
shortly.) The data pins of the first chip are connected to bits 3 and 2 of the data bus,
and those of the other chip are connected to bits 1 and 0,
两个或多个芯片可以组合起来构造一个每单元有多位的存储器。这可以通过
连接芯片相应的地址信号线和控制信号线，并将它们的数据引脚连到数据总
线的不同位上来完成。例如,2个 8?2芯片可以组合产生一个 8?4存储器，如
图 2-4所示。两个芯片从总线上接收相同的三位地址输入，还有共同的芯片
使能信号和输出使能信号（目前，我们只要了解两个芯片使用的是同一信号
就可以了，稍后我们将说明产生这些信号的逻辑）。第一个芯片的数据引脚
连到数据总线的第 3位和第 2位，第二个芯片的数据引脚则连在第 1位和第 0位。
Chapter 2 Organization of Computers
计算机专业英语 2-42
2.3.3 Memory Subsystem Configuration
When the CPU reads data,it places the address on the address bus,Both chips
read in address bits A2,A1,and A0 and perform their internal decoding,If the CE
and OE signals are activated,the chips output their data onto the four bits of the
data bus,Since the address and enable signals are the same for both chips,either
both chips or neither chip is active at any given time,The computer never has
only one of the two active,For this reason,they act just as a single 8?4 chip,at
least as far as the CPU is concerned.
当 CPU读取数据时，它将地址放在地址总线上。两个芯片读
取地址位 A2,A1,A0，并执行内部译码操作。如果 CE和
OE信号是有效的，两个芯片则输出数据到数据总线的四位
上。因为两个芯片的地址和使能信号是相同的，因此在任一
时刻两个芯片要么同时有效，要么同时无效。正因如此，它
们的行为就像一个单一的 8?4芯片，至少就 CPU而言是这样
的。
Chapter 2 Organization of Computers
计算机专业英语 2-43
2.3.3 Memory Subsystem Configuration
Instead of creating wider words,chips can be combined to create more words,The
same two 8 ?2 chips could instead be configured as a 16?2 memory subsystem,
This is illustrated in Figure 2-5(a),The upper chip is configured as memory
locations 0 to 7 (0000 to 0111) and the lower chip as locations 8 to 15 (1000 to
1111),The upper chip always has A3 = 0 and the lower chip has A3=1,This
difference is used to select one of the two chips,When A3 =0,the upper chip is
enabled and the lower chip is disabled; when A3 = 1,the opposite occurs,(As
shown in the figure,other conditions must also occur or neither chip will be
selected.) The output enables can be connected,since only the chip that is enabled
will output data,Since both chips correspond to the same data bits,both are
connected to D1 and D0 of the data bus.
除了构造更宽的字以外，芯片组合还可以构造出更多的字。两样的两个 8?2芯片能够组
成一个 16?2存储子系统。如图 2-5所示。上面的芯片构成存储器的 0到 7（ 0000到 0111）
单元，下面的芯片作为单元 8到 15（ 1000到 1111）。上面的芯片总是设置 A3=0,而下面
的芯片 A3=1。通过这一区别来选择芯片，当 A3=0时，上面的芯片有效，而下面的芯片
无效；当 A3=1时，情况刚好相反。（如图所示。另一种情况必定会发生，否则没有芯
片被选中。）输出使能端需要连接起来，因为只有芯片有效才可以输出数据。由于两
个芯片对应相同的数据位，因此都可以连接到数据总线的 D1和 D0位上。
Chapter 2 Organization of Computers
计算机专业英语 2-44
2.3.3 Memory Subsystem Configuration
This configuration uses high-order interleaving,All memory locations within a chip
are contiguous within system memory,However,this does not have to be the case,
Consider the configuration shown in Figure 2-5(b),which uses low-order
interleaving,The upper chip is enabled when A0=0,or by addresses XXX0,in this
case 0,2,4,6,8,10,12,and 14,The lower chip is enabled when A0=1,which is
true for addresses l,3,5,7,9,11,13,and 15,Both look the same to the CPU,but
low-order interleaving can offer some speed advantages for pipelined memory
access,and for CPUs that can read data from more than one memory location
simultaneously.
这种配置使用的是高位交叉技术。同一芯片的所有存储单元在系统内存中是
连续的。然而，不一定非得如此。考虑如图 2-5(b)所示的情况，它用的是低
位交叉技术。上面的芯片当 A0=0或者当地址位为 XXX0时有效，此时，地址
为 0,2,4,6,8,10和 12；下面的芯片当 A0=1时有效，条件是地址为 1,3、
5,7,9,11,13和 15。对 CPU而言，两者是相同的。但低位交叉能为流水
线存储器访问提供速度上的优势，对于能够同时从多于一个存储器单元中读
取数据的 CPU来说，低位交叉也存在速度上的优势。
Chapter 2 Organization of Computers
计算机专业英语 2-45
2.3.3 Memory Subsystem Configuration
The next step in these designs is to develop the CE and OE input
logic,Of these,the output enable is more straightforward,The CPU
generally outputs a control signal called RD or RD',or something
similar,which it sets active when it wants to read data from
memory,This signal is sufficient to drive OE; the logic to drive CE
ensures that only the correct chip outputs data,
设计的下一步就是指制定 CE和 OE的输入逻辑。输出使能更直
接一些,CPU通常输出一个控制信号，称作 RD或 RD'或别的
什么，当它想要从主存读取数据时就将其设为有效，用此信
号驱动 OE就足够了，而驱动 CE的逻辑务必确保只有正确的芯
片方可输出数据。
Chapter 2 Organization of Computers
计算机专业英语 2-46
2.3.3 Memory Subsystem Configuration
The chip enable signal makes use of the unused address bits,To
illustrate,assume that the 8 ?4 memory of Figure 2-4 is used in a
system with 6-bit address bus,Furthermore,assume this chip
corresponds to locations 0 to 7 (00 0000 to 00 0111),Address bits
A2,A1,and A0 select a location within the memory chips; bits A5,
A4,and A3 must be 000 for the chips to be active,
芯片使能信号可利用未使用的地址位。为了说明这一点，假
设图 2-4中的 8?4存储器被用到一个 6位地址总线的系统中，
而且，进一步假设这个芯片对应的单元为 0到 7（ 00 000到 00
0111）。则地址位 A2,A1和 A0可以用于选中存储芯片中的
某个单元，而 A5,A4和 A3在芯片有效时一定要是 000。
Chapter 2 Organization of Computers
计算机专业英语 2-47
2.3.4 Multibyte Data Organization
Many data formats use more than one 8-bit byte to represent a value,
whether it is an integer,floating point number,or character string,
Most CPUs assign addresses to 8-bit memory locations,so these
values must be stored in more than one location,It is necessary for
every CPU to define the order it expects for the data in these
locations.
许多数据格式使用多个字节（一个字节 8位）来表示一个数据，
而不管此数值是整型数、浮点数还是字符串。由于大多数
CPU给 8位的存储器单元分配地址，因此这些值必须存储在多
个单元中，每个 CPU必须定义数据在这些单元中的顺序。
Chapter 2 Organization of Computers
计算机专业英语 2-48
2.3.4 Multibyte Data Organization
There are two commonly used organizations for multibyte data,big
endian and little endian,In big endian format,the most significant
byte of a value is stored in location X,the following byte in
location X+l,and so on,For example,the hexadecimal value 0102
0304H (H for hexadecimal) would be stored,starting in location
100H,as shown in Table 2-1(a).
有两种常用的多字节数据排列顺序：高位优先和低位优先。依照高位优
先格式，一个数值的最高字节存储在单元 X中，次高字节存储在单元 X+1
中，依次类推。例如，十六进制数 01020304H(H表示十六进制 )从单元
100h开始存储，则存储结果如表 2-1(a)所示。
Chapter 2 Organization of Computers
计算机专业英语 2-49
2.3.4 Multibyte Data Organization
In little endian,the order is reversed,The least significant byte is
stored in location X,the next byte in location X+1,and so on,The
same value,in little endian format,is shown in Table 2-1(b).
依照低位优先格式，顺序正好相反。最低字节存储在单
元 X中，次字节存储在单元 X+1中，依次类推。上例中的
同一值，以低位优先格式存储，如表 2-1(b)所示。
Chapter 2 Organization of Computers
计算机专业英语 2-50
2.3.4 Multibyte Data Organization
The same organizations can be used for bits within a byte,In big
endian organization,bit 0 is the rightmost bit of a byte,the left most
bit is bit 7,In little endian organization,the leftmost bit is bit 0 and
bit 7 is the rightmost bit.
同样的组织方式可用于一个字节中的不同位上。在高位优先
结构中，位 0代表字节中最右边的位，最左边的位是第 7位。
在低位优先结构中，最左边的位是 0，最右边的位是 7。
Chapter 2 Organization of Computers
计算机专业英语 2-51
2.3.4 Multibyte Data Organization
Which endian organization is used for bytes and words does not impact the
performance of the CPU and computer system,As long as the CPU is designed to
handle a specific format,neither is better than the other,The main problem comes
in transferring data between computers with different endian organizations,For
example,if a computer with little endian organization transfers the value 0102
0304H to a computer with big endian organization without converting the data,the
big endian computer will read the value as 0403 0201H,There are programs which
can convert data files from one format to the other,and some microprocessors have
special instructions to perform the conversion.
对于字节和字而言，无论使用哪一种排列组织方式都不会影响 CPU和计算机
系统的性能。只要设计 CPU处理一种特定的格式，就不存在谁比谁强的问题，
主要的问题在于具有不同排列组织方式的 CPU之间传输数据的问题，例如，
如果一个低位优先结构的计算机传输 0102 0304H的数据给一个高位优先结构
的计算机，而没有转换数据，那么该高位优先结构计算机读出的值为 0403
0201H。有程序可以将两种时局文件进行格式转换，并且某些处理器有特殊
的指令可以执行这种转换。
Chapter 2 Organization of Computers
计算机专业英语 2-52
2.3.4 Multibyte Data Organization
One other issue of concern for multibyte words is alignment,Modern
microprocessors can read in more than one byte of data at a time,For example,the
Motorola 68040 microprocessor can read in four bytes simultaneously,However,
the four bytes must be in consecutive locations that have the same address except
for the two least significant bits,This CPU could read locations 100,101,102,and
103 simultaneously,but not locations 101,102,103,and 104,This case would
require two read operations,one for locations 100 (not needed),101,102,and 103,
and the other for 104,105 (not needed),106 (not needed),and 107 (not needed).
多字节的另一个值得关注的问题是对齐问题。现代微处理器在某一时刻可以
读出多个字节。例如，摩托罗拉 68040微处理器能同时读入 4个字节的数据，
然而，这 4个字节必须在连续的单元中，它们的地址除了最低两位不同之外，
其余的位均相同。该 CPU可以同时读单元 100,101,102和 103，但不能同时
读单元 101,102,103和 104，后者需要两个读操作，一个操作读 100（不需
要的）,101,102和 103，另一个读 104,105（不需要的）,106（不需要的）
和 107（不需要的）。
Chapter 2 Organization of Computers
计算机专业英语 2-53
2.3.4 Multibyte Data Organization
Alignment simply means storing multibyte values in locations such
that they begin at a location that also begins a multibyte read block,
In this example,this means beginning multibyte values at memory
locations that have addresses evenly divisible by four,thus
guaranteeing that a four-byte value can be accessed by a single read
operation.
对齐简单地说就使存储多字节值的起始单元刚好是某个多字
节读取模块的开始单元。在这个例子中，意味着多字节值开
始存储的单元的地址要能被 4整除，这样就保证该 4字节值可
在单一的一个读操作中存取到。
Chapter 2 Organization of Computers
计算机专业英语 2-54
2.3.4 Multibyte Data Organization
Some CPUs,particularly RISC CPUs,require all data to be aligned,
Other CPUs do not; they can usually align data internally,In general,
nonaligned CPUs have more compact programs,because no
locations are left unused by alignment,However,aligned CPUs can
have better performance because they may need fewer memory read
operations to fetch data and instructions.
一些 CPU，特别是精简指令系统 CPU，需要所有的数据都对
齐。其它的 CPU不要求这样，它们通常能够在内部将数据对
齐。一般来说，不要求对齐的 CPU具有更紧凑的程序，因为
没有单元因为要对齐而闲置不用。然而，对齐的 CPU具有更
好的性能，因为他们读取指令和数据是需要更少的存储器读
操作。
Chapter 2 Organization of Computers
计算机专业英语 2-55
2.3.5 Beyond the Basics（ 基本功能的拓展 ）
The memory subsystem described in this chapter is sufficient for small,embedded
computers,Personal computers and mainframes,however,require more complex
hierarchical configurations,These computers include small,high-speed cache
memory,The computer loads data from the physical memory into the cache; the
processor can access data in the cache more quickly than it can access the same
data in physical memory,Many microprocessors include some cache memory right
on the processor chip,A computer that includes cache memory must also have a
cache controller to move data between the cache and physical memory.
本章描述的存储器子系统对于较小的、嵌入式计算机而言是足够的。然
而，个人电脑和大型主机，需要更加复杂的层次结构。这些计算机包含
体积小的、高速的高速缓冲存储器。计算机将数据从物理存储器中装载
到高速缓冲中：处理器在高速缓冲中访问数据比在物理存储器中快得多。
许多微处理器就在处理器芯片中含有一些高速缓冲存储器。含有高速缓
冲存储器的计算机同时也要有一个高速缓冲控制器，用来在高速缓冲和
物理存储器间传输数据。
Chapter 2 Organization of Computers
计算机专业英语 2-56
2.3.5 Beyond the Basics
At the other extreme,modern computers include virtual memory,
This mechanism uses a hard disk as a part of the computer's memory,
expending the memory space of the computer while minimizing cost,
since a byte of hard disk costs less than a byte of RAM,As with the
cache,virtual memory needs a controller to move data between
physical memory and the hard disk,
在另一端，现代计算机还具有一个虚拟存储器。这种机制用硬
盘充当计算机存储器的一部分，扩大了计算机的存储空间，而
且降低了价格，因为一个硬盘字节的价格比一个 RAM字节要
便宜的多。同高速缓冲一样，虚拟存储器也需要一个控制器以
便在物理存储器和虚拟存储器之间传输数据。
Chapter 2 Organization of Computers
计算机专业英语 2-57
2.4 I/O Subsystem Organization and Interfacing
New Words & Expressions：
homogeneous adj.同类的,均一的
circuitry n.电路,线路
head n.磁头
wait state 等待状态
interrupt 中断
DMA=Direct Memory Access 直接存储器访问
Chapter 2 Organization of Computers
计算机专业英语 2-58
2.4 I/O Subsystem Organization and Interfacing
The CPU treats memory as homogeneous,From the CPU's perspective,each
location is read from and written to in exactly the same way,Each memory
location performs the same function--it stores a data value or an instruction for
use by the CPU.
CPU把存储器看作是同构的。从 CPU的角度来看，每一个单元的读操作和写
操作都是一样的，每一个单元执行同样的功能，即存储 CPU使用的数据或指
令。
Input/output (I/O) devices,on the other hand,are very
different,A personal computer's keyboard and hard disk
perform vastly different functions,yet both are part of the I/O
subsystem,Fortunately for the system designer,the interfaces
between the CPU and the I/O devices are very similar.
另一方面，输入 /输出设备是很不一样的。个人电脑的键盘和硬盘执行的
是千差万别的功能，但它们同是 I/O子系统的一部分。对系统设计者而言，
幸运的是 CPU和各 I/O设备之间的接口是非常相似的。
Chapter 2 Organization of Computers
计算机专业英语 2-59
2.4 I/O Subsystem Organization and Interfacing
As shown in Figure 2-1,each I/O device is connected to the
computer system's address,data,and control buses,Each I/O
device includes I/O interface circuitry; it is actually this circuitry
that interacts with the buses,The circuitry also interacts with the
actual I/O device to transfer data.
如图 2-1所示，每一个 I/O设备与计算机系统的地址总线、数据
总线和控制总线相连接，它们都包括 I/O接口电路，与总线交
互的实际上正是这一电路，同时它与实际的 I/O设备交互来传
输数据。
Chapter 2 Organization of Computers
计算机专业英语 2-60
2.4 I/O Subsystem Organization and Interfacing
Figure 2-7 shows the generic interface circuitry for an input
device,such as a keyboard,The data from the input device goes
to the tri-state buffers,When the values on the address and
control buses are correct,the buffers are enabled and data passes
on to the data bus,The CPU can then read in this data,When the
conditions are not right,the logic block does not enable the
buffers; they are tri-stated and do not place data onto the bus.
图 2-7显示了一个输入设备（比如键盘）的一般接口电路。从
输入设备来的数据传送到三态缓冲器，当地址总线和控制总
线上的值正确时，缓冲器设为有效，数据传到数据总线上，
然后 CPU可以读取数据。当条件不正确时，逻辑块不会使缓
冲器有效，它们保持高阻态，而且不把数据传到总线上。
Chapter 2 Organization of Computers
计算机专业英语 2-61
2.4 I/O Subsystem Organization and Interfacing
The key to this design is the enable logic,Just as every memory
location has a unique address,each I/O device also has a unique
address,The enable logic must not enable the buffers unless it
receives the correct address from the address bus,It must also
get the correct control signals from the control bus,For an input
device,an RD (or RD') signal must be asserted (as well as the
IO/signal,or equivalent,in systems with isolated I/O).
这一设计的关键在于使能逻辑。正如每一个存储单元都有一个
惟一的地址一样，每一个 I/O设备也有一个惟一的地址。除非
从地址总线得到了正确的地址，否则使能逻辑不置缓冲器有效。
同时，它还必须从控制总线上得到正确的控制信号。对于一个
输入设备,RD(或者 RD')信号必须有效（在独立系统中，还有
信号，或其他等效的信号）。
Chapter 2 Organization of Computers
计算机专业英语 2-62
2.4 I/O Subsystem Organization and Interfacing
The design of the interface circuitry for an output device,such as a computer
monitor,is somewhat different than that for the input device,As shown in
Figure 2-8,the tri-state buffers are replaced by a register,The tri-state buffers
are used in input device interfaces to make sure that no more than one device
writes data to the bus at any time,Since the output devices read data from the
bus,rather that write data to it,they don't need the buffers,The data can be
made available to all output devices; only the device with the correct address
will read it in.
输出设备（如显示器）接口电路的设计与输入设备的设计有所
不同。如图 2-8所示，寄存器代替了三态缓冲器。输入设备中使
用三态缓冲器是为了确保在任何时刻都只有一个设备向总线写
数据，而输出设备是从总线读取数据，不是写数据，因此不需
要缓冲器。数据对于所有的输出设备都可获得，但只有具有正
确地址的设备才会读取它。
Chapter 2 Organization of Computers
计算机专业英语 2-63
2.4 I/O Subsystem Organization and Interfacing
The load logic plays the role of the enable logic in the input device
interface,When this logic receives the correct address and control
signals,it asserts the LD signal of the register,causing it to read data
from the system's data bus,The output device can then read the data
from the register at its leisure while the CPU performs other tasks,
装载逻辑发挥着输入设备接口中使能逻辑的作用。当此逻辑获
得正确的地址信号和控制信号后，它发出寄存器的 LD信号，
促使它从系统数据总线上读取数据。然后输出设备可以在其空
闲的时候从寄存器中读取该数据，同时 CPU可以执行其他的任
务。
Chapter 2 Organization of Computers
计算机专业英语 2-64
2.4 I/O Subsystem Organization and Interfacing
A variant of this design replaces the register with tri-state
buffers,The same logic used to load the register is used to enable
the tri-state buffers instead,Although this can work for some
designs,the output device must read in data while the buffers
are enabled,Once they are disabled,the outputs of the buffers
are tri-stated and the data is no longer available to the output
device.
该设计也可以用三态缓冲器代替寄存器。装载寄存器的逻辑同
样用于使能三态缓冲器。虽然对于某些设计这是可行的，但是
输出设备必须在缓冲器有效时读入数据。一旦缓冲器被禁止，
其输出就是三态，该数据也就不再能够供输出设备使用。
Chapter 2 Organization of Computers
计算机专业英语 2-65
2.4 I/O Subsystem Organization and Interfacing
Some devices are used for both input and output,A personal
computer's hard disk drive falls into this category,Such a device
requires a combined interface that is essentially two interfaces,one
for input and the other for output,Some logic elements,such as the
gates that check the address on the address bus,can be used to
generate both the buffer enable and register load signals
有些设备既用于输入又用于输出，个人电脑中的硬盘驱动器
就属于这一类。这样的设备需要一个组合接口，本质上是两
个接口，一个用于输入，另一个用于输出。一些逻辑元件
（比如检查地址总线上的地址是否正确的门电路）既可以用
来产生缓冲器的使能信号，有可以用来产生寄存器的装载信
号。
Chapter 2 Organization of Computers
计算机专业英语 2-66
2.4 I/O Subsystem Organization and Interfacing
I/O devices are much slower than CPUs and memory,For this
reason,they can have timing problems when interacting with the
CPU,To illustrate this,consider what happens when a CPU wants to
read data from a disk,It may take the disk drive several milliseconds
to position its heads properly to read the desired value,In this time,
the CPU could have read in invalid data and fetched,decoded,and
executed thousands of instructions.
I/O设备比 CPU和存储器慢得多。基于这个原因，当它们与
CPU交互时，就可能存在时序上的问题。为了说明这一点，
考虑当 CPU想要从硬盘中读取数据时会发生的情况，这可能
要消耗磁盘驱动器几个毫秒来正确的定位磁头，以便读取想
要的数值，而在这段时间里,CPU可能已经读入了不正确的
数据，并且读取、译解和执行了成千上万条指令。
Chapter 2 Organization of Computers
计算机专业英语 2-67
2.4 I/O Subsystem Organization and Interfacing
Most CPUs have a control input signal called READY (or something
similar),Normally this input is high,When the CPU outputs the
address of the I/O device and the correct control signals,enabling the
tri-state buffers of the I/O device interface,the I/O device sets READY
low,The CPU reads this signal and continues to output the same
address and control signals,which cause the buffers to remain enabled,
In the hard disk drive example,the drive rotates the disk and positions
its read heads until it reads the desired data,
大多数 CPU都有一个控制输入信号，叫做就绪信号（ READY）（或其他意
思相近的名称），通常它为高电平。当 CPU输出某 I/O设备的地址和正确的
控制信号，促使 I/O设备接口的三态缓冲器有效时，该 I/O设备置 READY信
号为低电平。 CPU读取这一信号，并且继续输出同样的地址信号和控制信号，
使缓冲器保持有效。在硬盘驱动器的例子中，此时驱动器旋转磁头，并且定
位读写头，直到读到想要要的数据为止。
Chapter 2 Organization of Computers
计算机专业英语 2-68
2.4 I/O Subsystem Organization and Interfacing
The CPU then reads the data from the bus and continues its
normal operation,The extra clock cycles generated by having
READY set low are called wait states,CPUs can also use the
READY signal to synchronize data transfers with the memory
subsystem.
然后它通过缓冲器将数据输出到数据总线上，并重新设置
READY为高电平。这时 CPU才从总线上读入数据，之后继续它
的正确操作。设置 READY为低电平而生成的附加时钟周期叫做
等待状态。 CPU同样也可以使用 READY信号来同步与存储器子
系统之间的数据传输。
Chapter 2 Organization of Computers
计算机专业英语 2-69
2.4 I/O Subsystem Organization and Interfacing
These I/O interfaces are fine for small computers,such as the
microwave oven controller,but they suffer from poor performance in
larger computer systems,In all but the smallest systems,it is not
acceptable for the CPU to have to wait thousands of clock cycles for
data from an I/O device,Many systems use interrupts so they can
perform useful work while waiting for the much slower I/O devices,
这些 I/O接口对于小型的计算机而言已经很好了，比如说微波
炉控制器，但是在大型的计算机系统中它们的性能则很差。
在除最小系统以外的所有系统中，让 CPU等待成千上万个时
钟周期方从 I/O设备中得到数据是不能接收的，为此，许多系
统都使用了中断机制,以便 CPU在等待慢得多的 I/O设备时，可
以执行其他有用的工作。
Chapter 2 Organization of Computers
计算机专业英语 2-70
2.4 I/O Subsystem Organization and Interfacing
These I/O interfaces are also not suited to large data transfers,In the
systems in this chapter,each byte of data transferred between an I/O
device and memory must pass through the CPU,This is inefficient
for many common operations,such as loading a program from disk
into memory,Direct memory access,DMA,is a method used to
bypass the CPU in these transfers,thus performing them much more
quickly,
这些 I/O接口也不适合大量的数据传输。在本章的系统中，
I/O设备和存储器之间传输的每一个字节都必须通过 CPU，这
对于许多常见的操作（例如从磁盘向主机存装载一个程序）
来说效率低下。直接存储器访问就是在数据传输中绕过 CPU
的一种方法，因此执行起来速度很快。
Chapter 2 Organization of Computers
计算机专业英语 2-71
计算机英语专业词汇的构成
专业词汇的构成
派生词
(derivation)
复合词
(compounding)
混成词
(blending)
前缀
缩略词
(shortening)
后缀 压缩和省略 缩写
借用词
Chapter 2 Organization of Computers
计算机专业英语 2-72
一、派生词 (derivation)
1．前缀
采用前缀构成的单词在计算机专业英语中占了很大比例，通过下面的实例可以了解
这些常用的前缀构成的单词。
multi-多 hyper-超级 super 超级
multiprogram 多道程序 hypercube 超立方 superhighway 超级公路
inter-相互、在,..间 micro-微型 tele-远程的
interface接口、界面 microprocessor 微处理器 telephone 电话
interlace 隔行扫描 microkernel 微内核 teletext 图文电视
单词前缀还有很多，其构成可以同义而不同源 (如拉丁、希腊 )，可以互换，例如：
multi,poly 相当于 many 如, multimedia多媒体,polytechnic各种工艺的
uni,mono 相当于 single 如, unicode统一的字符编码标准,monochrome单色
bi,di 相当于 twice 如, binomial 二项式,dibit双位
equi,iso 相当于 equal 如, equality等同性,isochromatic等色的,
simili,homo 相当于 same 如, similarity类似,homogeneous同类的
semi,hemi 相当于 half 如, semiconductor半导体,hemicycle半圆形
hyper,super 相当于 over 如, hypertext超文本,supercomputer超级计算机
Chapter 2 Organization of Computers
计算机专业英语 2-73
一、派生词 (derivation)
2．后缀
后缀是在单词后部加上构词结构，形成新的单词。如,
-scope 探测仪器 -meter 计量仪器 -graph 记录仪器
microscope显微镜 barometer 气压表 tomograph X线体层照相
telescope 望远镜 telemeter 测距仪 telegraph 电报
spectroscope 分光镜 spectrometer 分光仪 spectrograph 分光摄像
仪
-able可能的 -ware 件 (部件 ) -ity 性质
enable 允许、使能 hardware 硬件 reliability 可靠性
disable 禁止、不能 software 软件 availability 可用性
programmable 可编程的 firmware 固件 accountability 可核查性
portable 便携的 groupware 组件 integrity 完整性
scalable 可缩放的 freeware 赠件 confidentiality 保密性
Chapter 2 Organization of Computers
计算机专业英语 2-74
二、复合词 (compounding)
复合词是科技英语中另一大类词汇，其组成面广，通常分为复合名词、复合形容词、
复合动词等。复合词通常以小横杠,-”连接单词构成，或者采用短语构成。有的复
合词进一步发展，去掉了小横杠,并经过缩略成为另一类词类，即混成词。复合词的
实例有,
-based基于，以 …… 为基础 -centric 以 …… 为中心的
rate-based 基于速率的 client-centric 以客户为中心的
credit-based 基于信誉的 user-centric 以用户为中心的
file-based 基于文件的 host-centered 以主机为中心的
-oriented 面向 …… 的 -free 自由的，无关的
object-oriented 面向对象的 lead-free 无线的
market-oriented 市场导向 jumper-free 无跳线的
process-oriented 面向进程的 paper-free 无纸的
info-信息，与信息有关的 envent-事件的
info-channel 信息通道 envent-driven 事件驱动的
info-tree 信息、树 envent-oriented 面向事件的
info-world 信息世界 event-based 基于事件的
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二、复合词 (compounding)
此外，以名词 + 动词 -ing 构成的复合形容词形成了一种典型的替换关系，即可以根
据需要在结构中代入同一词类而构成新词，它们多为动宾关系。如,
man-carrying aircraft 载人飞船 earth-moving machine 推土机
time-consuming operation 耗时操作 ocean-going freighter 远洋货舱
然而，必须注意，复合词并非随意可以构造，否则会形成一种非正常的英语句子结
构。虽然上述例子给出了多个连接单词组成的复合词，但不提倡这种冗长的复合方
式。对于多个单词的非连线形式，要注意其顺序和主要针对对象。
此外还应当注意，有时加连字符的复合词与不加连字符的词汇词意是不同的，必须
通过文章的上下文推断。如,
force-feed 强迫接受（ vt.），而 force feed 则为“加压润滑”。
随着词汇的专用化，复合词中间的连接符被省略掉，形成了一个单词，例如：
videotape 录像带 fanin 扇入 fanout 扇出
online 在线 onboard 在板 login 登录
logout 撤消 pushup 拉高 popup 弹出
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三, 混成词 (blending)
混成词不论在公共英语还是科技英语中也大量出现，也有人将它们称为缩
合词（与缩略词区别）、融会词，它们多是名词，也有地方将其作为动词
用，对这类词汇可以通过其构词规律和词素进行理解。这类词汇将两个单
词的前部拼接、前后拼接或者将一个单词前部与另一词拼接构成新的词汇，
实例有,
brunch (breakfast + lunch) 早中饭
smog (smoke +fog) 烟雾
codec (coder+decoder) 编码译码器
compuser (computer+user) 计算机用户
transeiver (transmitter+receiver) 收发机
syscall (system+call) 系统调用
mechatronics (mechanical+electronic) 机械电子学
calputer (calculator+computer) 计算器式电脑
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四、缩略词 (shortening)
缩略词是将较长的英语单词取其首部或者主干构成与原词同义的短单词，或
者将组成词汇短语的各个单词的首字母拼接为一个大写字母的字符串。随着
科技发展，缩略词在文章索引、前言、摘要、文摘、电报、说明书、商标等
科技文章中频繁采用 。
1．压缩和省略
将某些太长、难拼、难记、使用频繁的单词压缩成一个短小的单词，
或取其头部、或取其关键音节。如,
f1u=influenza 流感 1ab=laboratory 实验室
math=mathematics 数学 iff=if only if 当且仅当
rhino=rhinoceros 犀牛 ad=advertisement 广告
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四、缩略词 (shortening)
2．缩写 (acronym)
将某些词组和单词集合中每个实意单词的第一或者首部几个字母重新组合，
组成为一个新的词汇，作为专用词汇使用。在应用中它形成三种类型，即,
1) 通常以小写字母出现，并作为常规单词
flops (floating-point Operation Per Second) 每秒浮点运算次数
spool (simultaneous peripheral operation on line) 假脱机
2) 以大写字母出现，具有主体发音音节
BASIC (Beginner's All-purpose Symbolic Instruction Code) 初学者通用符号指令代码
FORTRAN (Formula Translation) 公式翻译 (语言 )
COBOL (Common Business Oriented Language) 面向商务的通用语言
3) 以大写字母出现，没有读音音节，仅为字母头缩写
RISC (Reduced Instruction Set Computer) 精简指令集计算机
CISC (Complex Instruction Set Computer) 复杂指令集计算机
ADE (Application Development Environment) 应用开发环境
PCB (Process Control Block) 进程控制块
CGA (Color Graphics Adapter) 彩色图形适配器
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五、借用词
借用词一般来自厂商名、商标名、产品代号名、发明者名、地名等，它
通过将普通公共英语词汇演变成专业词意而实现。有的则是将原来已经
有的词汇赋予新的含义。例如,
woofer 低音喇叭 tweeter 高音喇叭 flag标志、状态
cache 高速缓存 semaphore 信号量 firewall 防火墙
mailbomb 邮件炸弹 scratch pad 高速缓存 fitfall 专用程序入口
在现代科技英语中借用了大量的公共英语词汇、日常生活中的常用词汇，
而且，以西方特有的幽默和结构讲述科技内容。这时，读者必须在努力
扩大自己专业词汇的同时，也要掌握和丰富自己的生活词汇，并在阅读
和翻译时正确采用适当的含义。
