Steady-state behavior
when output is hold on 1 or 0
Dynamic behavior
when output is changing
Electrical behavior of CMOS
The electric model for MOS transistor
Cg,gate capacitor
Cd and Cs,junction capacitors
CgCsCd 3
The electric model for basic CMOS circuit
Input capacitor,related to gates;
Output capacitor,related to junctions;
Output resistor,related to the gate area.
When state is hold,only R is considered ;
Some voltage must be fallen on R !
The electric model for basic CMOS circuit
Steady-state behavior for inverter
Ideal behavior Real behavior
The input between VIL and VIH should be avoid !
Logic level and noise margin
When load become heaver,the noise
margin become narrow !
Dynamic behavior
If the output is changed,the capacitors must
be charged or uncharged through a resistor !
The delay time is decided by RC !
How to estimate the time delay for
a single device
Problem,
R and C belong to
different devices,can
not be decided from
single device !
Solution,
Make all the output resistors a same value,
the time delay can be decided only by
capacitors of the device !
The minimal size device
Let the length be the minimal
size; all the R and C will be
decided by the width !
WR /1? WC?
Take these values as units !
For the minimal size NMOS:
0RR? 0CCg? 03CCd?
The minimal size device
The resistivity of PMOS is
larger than NMOS,to keep
R the same value,its width
must increase; For the
minimal size PMOS,
0RR?
00 2 CrCCg
063 CCgCd
2?W
For the minimal NMOS,set W=1
The minimal size device
The logic area of a transistor
WA?
Let the area of the minimal
NMOS be a unit,
0AA N M O S?
Then for the minimal PMOS:
02 AA P M O S
The time delay of a minimal
inverter
Time delay
0312 CC in
0936 CC d nC d pC o u t
C o u tC inRCRt d
00 1212 tRCt d
03 AA IN V
Time delay
Logic area
The time delay for simple logic
device
When estimate the
time delay of a
device,only take the
largest value !
Adjust the width to
keep R=1 at any
output path !
3?Cin 18?Cout
21?dt
5?Cin
18?Cout
23?dt
8?A
10?A
The time delay for simple logic
device
2442 At d 5081 At d
when output is hold on 1 or 0
Dynamic behavior
when output is changing
Electrical behavior of CMOS
The electric model for MOS transistor
Cg,gate capacitor
Cd and Cs,junction capacitors
CgCsCd 3
The electric model for basic CMOS circuit
Input capacitor,related to gates;
Output capacitor,related to junctions;
Output resistor,related to the gate area.
When state is hold,only R is considered ;
Some voltage must be fallen on R !
The electric model for basic CMOS circuit
Steady-state behavior for inverter
Ideal behavior Real behavior
The input between VIL and VIH should be avoid !
Logic level and noise margin
When load become heaver,the noise
margin become narrow !
Dynamic behavior
If the output is changed,the capacitors must
be charged or uncharged through a resistor !
The delay time is decided by RC !
How to estimate the time delay for
a single device
Problem,
R and C belong to
different devices,can
not be decided from
single device !
Solution,
Make all the output resistors a same value,
the time delay can be decided only by
capacitors of the device !
The minimal size device
Let the length be the minimal
size; all the R and C will be
decided by the width !
WR /1? WC?
Take these values as units !
For the minimal size NMOS:
0RR? 0CCg? 03CCd?
The minimal size device
The resistivity of PMOS is
larger than NMOS,to keep
R the same value,its width
must increase; For the
minimal size PMOS,
0RR?
00 2 CrCCg
063 CCgCd
2?W
For the minimal NMOS,set W=1
The minimal size device
The logic area of a transistor
WA?
Let the area of the minimal
NMOS be a unit,
0AA N M O S?
Then for the minimal PMOS:
02 AA P M O S
The time delay of a minimal
inverter
Time delay
0312 CC in
0936 CC d nC d pC o u t
C o u tC inRCRt d
00 1212 tRCt d
03 AA IN V
Time delay
Logic area
The time delay for simple logic
device
When estimate the
time delay of a
device,only take the
largest value !
Adjust the width to
keep R=1 at any
output path !
3?Cin 18?Cout
21?dt
5?Cin
18?Cout
23?dt
8?A
10?A
The time delay for simple logic
device
2442 At d 5081 At d
