Combinational logic
circuits
Chapter 3
Integrated Digital Circuit
INTRODUCTION
Components level
First IC level (SSI)
Level four
Level three
Level five
Electronic Components,e.g,transistors,
diodes,resistors,capacitors
Function Logic Units,e.g,gates,NOT,
AND,NAND,EX-OR
Function Logic Units,e.g,adders,
counters,multiplexers
More complex Function Logic Units,e.g,
microprocessor
Complex Systems,Function Units from
levels Two through Four
Third IC level (VLSI)
Second IC level
(MSI and LSI)
Level two
Level one
INTRODUCTION
The most common
transistor-transistor logic (TTL)
emitter-coupled logic (ECL)
complementary metal-oxide
semiconductor logic (CMOS),
Each of these main logic families is made up
of numerous subfamilies.
INTRODUCTION
SN54/74ALS00
SN is a prefix,The prefix indicates the manufacturer.
The number 54 indicates a military operating temperature
range and 74 indicate a commercial temperature range,
Both temperature ranges are available for most functions
and subfamilies.
The letter-number combination following the SN54/74
indicates the subfamily and the logical function of the IC.
SN74ALS00 is a commercial temperature range advanced
low-power schottky NAND gate IC manufactured by Texas
instruments.
Decoder
Decoder convert a set of input variables
representing a code into a set of variables
representing a different code,The relationship
between the input and output codes can be
expressed in a truth table.
Encoded information is presented as n inputs
producing 2n outputs,The outputs values can range
from 0 to 2n-1.
Some decoder generate outputs over a truncated
portion of possible values.
Decoder
Typical
decoder
Enable
inputs
n-data
inputs
2n
possible
outputs
Decoder
Decoder can be used as minterm or
maxterm generators.
TTL74xx138
3-to-8 decoder
multiple 3-to -8 decoders can be
cascaded to form 4-to-16 or even large
decoders,
Decoder
F(A,B,C)
=∏M(0,1,2,4,7);
F(A,B,C)
=∑m(2,4,5,7);
A
B
C
G1
G2A’
G2B’
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
74LS138
To 74LS138
Yi corresponds to Maxterm i.
Yi=Mi
Decoder
F(A,B,C) =∏M(0,1,2,4,7);
A
B
C
G1
G2A’
G2B’
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
74LS138
FAB
C
1
0
0
Decoder
F(A,B,C) =∑m(2,4,5,7)=∏M(0,1,3,6);
A
B
C
G1
G2A’
G2B’
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
74LS138
FAB
C
1
0
0
Decoder
F(A,B,C) =∑m(2,4,5,7) =m2+m4+m5+m7
=M2’+M4’+M5’+M7’
A
B
C
G1
G2A’
G2B’
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
74LS138
F
A
B
C
1
0
0
BCD Decoder
74xxx42 is a BCD to decimal decoder.
Figure 4.25
It has 4 inputs and 10 outputs.
The four-bit BCD input is decoded
to one of ten outputs
BCD to seven-segment Decoder
74xxx47 is a BCD(8421) to seven-segment
decoder driver MSI circuit.
An 8421BCD input is decoded,selecting
which of the seven output are to be low,
directly driving one of the seven-
segment display LEDs.
Inputs are provided to permit display
blanking and testing,
BCD to seven-segment Decoder
a
b
c
d
f g
a b c d e f g
1 1 1 1 1 1 0
0 1 1 0 0 0 0
1 1 0 1 1 0 1
e
BCD to seven-segment Decoder
g
c
b
a
d
e
F
Light-emitter diode (LED)
Anode seven-segment LED
display
Segment be turned on by
high level 1,
Cathode seven-segment
LED display
Segment be turned on by
low level 0.
D
C
B
A
a
b
c
d
e
f
g
BCD to seven-segment Decoder
g
c
b
a
d
e
F
Anode seven-segment
LED display
active low
0
0
1
1
1
1
1
1
0
0
1
74xxx47
D
C
B
A
a
b
c
d
e
f
g
BCD to seven-segment Decoder
g
c
b
a
d
e
F
Cathode seven-segment
LED display
active high
0
0
1
1
0
0
0
0
1
1
0
Encoder
Encoder perform a function that is the
inverse of decoders,
Encoders have more input than output
variables,It produce n outputs from 2n
inputs
74xx147
10-line to BCD encoder
74xx148
8-line to 3-line priority encoder
Encoder
Typical
encoder
Enable
inputs
n-data
outputs
2n
data
inputs
Encoder
74xx147
10-line to BCD encoder
Typical application
Encode decimal keypad or switching
panel output data into BCD
Ex,Figure 4.30
Encoder
74xx148
8-line to 3-line priority encoder
Ex,
It can be used to identify an event and
assign and transmit a code to the control
unit based on some priority.
Connect the devices to the inputs according
to priority,Device with higher priority
connects to the higher bit input port.
Multiplexer
Digital multiplexer provides the digital
equivalent of an analog selector switch,
It connects one of n inputs to a single
output line,so that the logical value of the
input is transferred to the output.
The one of n input selection is determined
by m select inputs,where n=2m.
Multiplexer
n select
inputs
2n data
inputs Y
Y ’
Multiplexer
It can be used as Boolean function generator.
N-to-1 multiplexer
D0,D1,……,Dn-1 be the data input variables
A0,A1,……,Am be the select input variables
n=2m.
It can be used to generate up to n minterms.
mi is the minterm consisting of the select
input A0,A1,……,Am.
Multiplexer
It can be used as Boolean function generator.
N-to-1 multiplexer
n=2m
Output Y= i
n －
i= 0
i Dm?∑
1
Multiplexer
If the number of variables in the
minterm is equal to the number of
select lines
To connect the function variables
directly to the select inputs.
If a minterm i exists in a function,we
assign high level 1 to the corresponding
data inputs Di,
Assign lower level 0 to the residual data
input,
Multiplexer
Select input=A,B,C,D
D0=D1=D2=D3=D5=D8=D9=D11=D14=D15=1
D4=D6=D7=D10=D12=D13=0
F(A,B,C,D)
=∑m(0,1,2,3,5,8,9,11,13,14,15)
16-to-1 multiplexer
Multiplexer
F(A,B,C,D)=∑m(0,1,2,3,5,8,9,11,13,14,15)
=A’B’C’D’ +A’B’C’D +A’B’CD’ +A’B’CD +A’BC’D +AB’C’D’
+AB’C’D+AB’CD+ABC’D+ABCD’+ABCD
16-to-1 multiplexer
ABCD are all the select inputs
Y=∑miDi (0≤i≤15)
=A’B’C’D’·D0 +A’B’C’D·D1 +A’B’CD’·D2 +A’B’CD·D3 +A’BC’D’·D4
+A’BC’D·D5 +A’BCD’·D6 +A’BCD·D7 +AB’C’D’·D8 +AB’C’D·D9
+AB’CD’·D10 +AB’CD·D11 +ABC’D’·D12+ABC’D·D13 +ABCD’·D14
+ABCD·D15
Y=F,compare two expressions
D0=1; D1=1; D2=1; D3=1; D4=0; D5=1; D6=0; D7=0;
D8=1; D9=1; D10=0; D11=1; D12=0; D13=1; D14=1; D15=1
Multiplexer
If the number of variables in the
minterm is less than the number of
select lines
F(A,B,C,D)
=∑m(0,1,2,3,5,8,9,11,13,14,15)
8-to-1 multiplexer
Multiplexer
solution
Three variable are used as select inputs.
The fourth is connected as need to the
multiplexer,
F(A,B,C,D)
=∑m(0,1,2,3,5,8,9,11,13,14,15)
8-to-1 multiplexer
Multiplexer
F(A,B,C,D)=∑m(0,1,2,3,5,8,9,11,13,14,15)
=A’B’C’D’+A’B’C’D+A’B’CD’+A’B’CD+A’BC’D +AB’C’D’
+AB’C’D +AB’CD +ABC’D +ABCD’ +ABCD
8-to-1 multiplexer
Treat ABC as the select inputs
mi consists of A,B and C.
Y=∑miDi (0≤i≤7)
=A’B’C’·D0 +A’B’C·D1 +A’BC·D2 +A’BC·D3 +AB’C’·D4 +AB’C·D5
+ABC’·D6 +ABC·D7
Y=F,compare two expressions
D0=D’+D=1; D1=D’+D=1; D2=D; D3=0;
D4=D+D’=1; D5=D; D6=D; D7=D’+D=1;
1
1
1
1
1
1
1
1
1
1
1
Multiplexer
F(A,B,C,D)=∑m(0,1,2,3,5,8,9,11,13,14,15)
00 01 11 10
AB
CD
00
01
11
10
0 4 12 8
1 5 13 9
3 7 15 11
2 6 14 10
1
1
1
1
1
1
1
1
1
1
1
Y= ∑miDi (0≤i≤7)
= A’B’C’·D0 +A’B’C·D1
+A’BC·D2 +A’BC·D3
+AB’C’·D4 +AB’C·D5
+ABC’·D6 +ABC·D7
Y=F
D0=D’+D=1; D1=D’+D=1; D2=D; D3=0;
D4=D+D’=1; D5=D; D6=D; D7=D’+D=1;
Multiplexer
F(A,B,C,D)
=∑m(0,1,2,3,5,8,9,11,13,14,15)
4-to-1 multiplexer
Multiplexer
F(A,B,C,D)=∑m(0,1,2,3,5,8,9,11,13,14,15)
=A’B’C’D’+A’B’C’D+A’B’CD’+A’B’CD
+ A’BC’D
+ AB’C’D’ +AB’C’D +AB’CD
+ ABC’D +ABCD’ +ABCD
4-to-1 multiplexer
Treat AB as the select inputs
mi consists of A and B.
Y=∑miDi (0≤i≤3)
=A’B’·D0 +A’B·D1 +AB’·D2 +AB·D3
D0=C’D’+C’D+CD’+CD=1;
D1=C’D’;
D2=C’D’+C’D+CD=D+C’;
D3=C’D+CD’+CD=D+C;
Multiplexer
F(A,B,C,D)=∑m(0,1,2,3,5,8,9,11,13,14,15)
4-to-1 multiplexer
Treat AB as the select inputs
mi consists of A and B.
Y=∑miDi (0≤i≤3)
=A’B’·D0 +A’B·D1 +AB’·D2 +AB·D3
Y=F
D0=C’D’+C’D+CD’+CD=1;
D1=C’D’;
D2=C’D’+C’D+CD=D+C’;
D3=C’D+CD’+CD=D+C;
00 01 11 10
AB
CD
00
01
11
10
0 4 12 8
1 5 13 9
3 7 15 11
2 6 14 10
1
1
1
1
1
1
1
1
1
1
1
MSI Adder
A4 A3 A2 A1 B4 B3 B2 B1
F4 F3 F2 F1
CO CI
MSI Adder
Cascading full-adders
An n-bit adder can be built by cascading
(connecting in series) n full-adders,Each carry-
out from a full-adder become the carry-in to the
next full-adder.
The carries propagate from one full-adder to the
next higher order full-adder,This type of
addition is call ripple-carry propagation.
Total delay time is the product of the sum of
stages in the adder,and the carry-in to carry-out
propagation delay time,
Parallel adder
74xx83A is a four-bit binary parallel adder
with a fast carry feature.
The look-ahead carry,or fast carry,technique
reduces propagation times through the adder.
This is accomplished by generating all the
individual carry terms need by each full-adder
in as few levels of logic as possible.
MSI Adder
MSI Adder
The carry output of any full-adder stage in a
multiple-stage is written Ci
Ci=XiYi+(Xi+Yi)Ci-1
If both of (Xi,Yi) are a 1,Ci=1
If either of (Xi,Yi) is a 1,Ci=Ci-1,
MSI Adder
Ci=XiYi+(Xi+Yi)Ci-1
let carry-propagation Pi=Xi+Yi
let carry-generate Gi= XiYi,
Ci= Gi + PiCi-1
C1= P1C0 + G1
C2= P2P1C0 + P2G1+ G2
C3= P3P2P1C0 + P3P2G1+ P3G2 +G3
C4= P4P3P2P1C0 + P4P3P2G1+ P4P3G2 +P4G3+G4
MSI Adder
Ci= Gi + PiCi-1
C1= P1C0 + G1
C2= P2P1C0 + P2G1+ G2
C3= P3P2P1C0 + P3P2G1+ P3G2 +G3
C4= P4P3P2P1C0 + P4P3P2G1+ P4P3G2 +P4G3+G4
Each carry-out need three level of logic to realize,
The adder propagation delay is constant,not
dependent on the ripple carry.
MSI Adder
Using an MIS adder as a 8421BCD to Ex-3 code
converter.
4 input variables,b8b4b2b1
4 output variables,e4e3e2e1
A4A3A2A1 B4B3B2B1
F4 F3 F2 F1
CO CI
e4 e3 e2 e1
b8b4b2b10 0 1 1
,0”
MSI Adder
Using a four-bit binary parallel adder as a four-bit
binary adder/subtracter,
Find the radix complement of the subtrahend and
add it to the minuend to produce the difference.
8 value input
a+b =a4a3a2a1+b4b3b2b1+0
a-b = a4a3a2a1-b4b3b2b1
= a4a3a2a1+b4’b3’b2’b1’+1
1 control input
M=0,a+b
M=1,a-b
MSI Adder
A4A3A2A1
A4=a4 ; A3=a3 ; A2=a2 ; A1=a1;
B4B3B2B1
M=0,Bi=bi;
M=1,Bi=bi’;
Bi=f(M,bi) =M⊕ bi;
CI
M=0,CI=0;
M=1,CI=1;
CI=f(M)=M;
MSI Adder
Peripheral
design
A4A3A2A1 B4B3B2B1
F4 F3 F2 F1
CO CI
e4 e3 e2 e1
a4a3a2a1
M
=1
=1
=1
=1
b4
b3
b2
b1
MSI Adder
Using four-bit binary parallel adders to realize a 1-bit decimal
adder represented by Ex-3 code.
(A+B)10=(JC)10=J*10+C
(C)ex-3
C4
C3
C2
C1
(A)ex-3
(B)ex-3
A4
A3
A2
A1
B4
B3
B2
B1
Logic
circuit
J
MSI Adder
8 input variables,
(A)ex-3= A4A3A2A1
(B)ex-3= B4B3B2B1
4 output variables,
(C)ex-3=C4C3C2C1
the output of MSI adder – F,Co
CoF4F3F2F1= A4A3A2A1+B4B3B2B1
Key,
find the relationship between F and (C)ex-3
(A)2=a4a3a2a1 ; (A)ex-3=(A)2+0011;
A4A3A2A1=a4a3a2a1+0011
(B)2=b4b3b2b1 ; (B)ex-3=(B)2+0011
B4B3B2B1=b4b3b2b1+0011
(C)2=c4c3c2c1 ; (C)ex-3=(C)2+0011
C4C3C2C1=c4c3c2c1+0011
CoF4F3F2F1 = (A)ex-3+ (B)ex-3
CoF4F3F2F1 = A4A3A2A1 + B4B3B2B1
= a4a3a2a1+0011+b4b3b2b1+0011
= a4a3a2a1+b4b3b2b1+0110
MSI Adder
J=0,A+B<10
A+3+B+3<16
CoF4F3F2F1=(A)EX-3+(B)EX-3<10000
Co=0
J=1,A+B>=10
A+3+B+3>=16
CoF4F3F2F1=(A)EX-3+(B)EX-3>=10000
Co=1
J=Co
MSI Adder
if (A+B)<10? J=0? A+B=C
(A)2+(B)2=(C)2
(A)ex-3+ (B)ex-3
= A4A3A2A1+B4B3B2B1
= (a4a3a2a1+b4b3b2b1)+0110
= c4c3c2c1+0110
= (c4c3c2c1+0011)+0011
= C4C3C2C1+0011
= (C)ex-3+0011
(C)ex-3= F4F3F2F1 – 0011= F4F3F2F1 +1101
MSI Adder
if (A+B)>10?J=1?A+B=10+C
C=A+B-10
(C)2=(A)2+(B)2-(10)2=(A)2+(B)2-1010
(A)ex-3+ (B)ex-3
= A4A3A2A1+B4B3B2B1
= (a4a3a2a1+b4b3b2b1)+0110
= (c4c3c2c1+1010)+0110
= c4c3c2c1+10000
= 1c4c3c2c1 = 1F4F3F2F1
(C)ex-3= F4F3F2F1 +0011
MSI Adder
circuits
Chapter 3
Integrated Digital Circuit
INTRODUCTION
Components level
First IC level (SSI)
Level four
Level three
Level five
Electronic Components,e.g,transistors,
diodes,resistors,capacitors
Function Logic Units,e.g,gates,NOT,
AND,NAND,EX-OR
Function Logic Units,e.g,adders,
counters,multiplexers
More complex Function Logic Units,e.g,
microprocessor
Complex Systems,Function Units from
levels Two through Four
Third IC level (VLSI)
Second IC level
(MSI and LSI)
Level two
Level one
INTRODUCTION
The most common
transistor-transistor logic (TTL)
emitter-coupled logic (ECL)
complementary metal-oxide
semiconductor logic (CMOS),
Each of these main logic families is made up
of numerous subfamilies.
INTRODUCTION
SN54/74ALS00
SN is a prefix,The prefix indicates the manufacturer.
The number 54 indicates a military operating temperature
range and 74 indicate a commercial temperature range,
Both temperature ranges are available for most functions
and subfamilies.
The letter-number combination following the SN54/74
indicates the subfamily and the logical function of the IC.
SN74ALS00 is a commercial temperature range advanced
low-power schottky NAND gate IC manufactured by Texas
instruments.
Decoder
Decoder convert a set of input variables
representing a code into a set of variables
representing a different code,The relationship
between the input and output codes can be
expressed in a truth table.
Encoded information is presented as n inputs
producing 2n outputs,The outputs values can range
from 0 to 2n-1.
Some decoder generate outputs over a truncated
portion of possible values.
Decoder
Typical
decoder
Enable
inputs
n-data
inputs
2n
possible
outputs
Decoder
Decoder can be used as minterm or
maxterm generators.
TTL74xx138
3-to-8 decoder
multiple 3-to -8 decoders can be
cascaded to form 4-to-16 or even large
decoders,
Decoder
F(A,B,C)
=∏M(0,1,2,4,7);
F(A,B,C)
=∑m(2,4,5,7);
A
B
C
G1
G2A’
G2B’
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
74LS138
To 74LS138
Yi corresponds to Maxterm i.
Yi=Mi
Decoder
F(A,B,C) =∏M(0,1,2,4,7);
A
B
C
G1
G2A’
G2B’
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
74LS138
FAB
C
1
0
0
Decoder
F(A,B,C) =∑m(2,4,5,7)=∏M(0,1,3,6);
A
B
C
G1
G2A’
G2B’
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
74LS138
FAB
C
1
0
0
Decoder
F(A,B,C) =∑m(2,4,5,7) =m2+m4+m5+m7
=M2’+M4’+M5’+M7’
A
B
C
G1
G2A’
G2B’
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
74LS138
F
A
B
C
1
0
0
BCD Decoder
74xxx42 is a BCD to decimal decoder.
Figure 4.25
It has 4 inputs and 10 outputs.
The four-bit BCD input is decoded
to one of ten outputs
BCD to seven-segment Decoder
74xxx47 is a BCD(8421) to seven-segment
decoder driver MSI circuit.
An 8421BCD input is decoded,selecting
which of the seven output are to be low,
directly driving one of the seven-
segment display LEDs.
Inputs are provided to permit display
blanking and testing,
BCD to seven-segment Decoder
a
b
c
d
f g
a b c d e f g
1 1 1 1 1 1 0
0 1 1 0 0 0 0
1 1 0 1 1 0 1
e
BCD to seven-segment Decoder
g
c
b
a
d
e
F
Light-emitter diode (LED)
Anode seven-segment LED
display
Segment be turned on by
high level 1,
Cathode seven-segment
LED display
Segment be turned on by
low level 0.
D
C
B
A
a
b
c
d
e
f
g
BCD to seven-segment Decoder
g
c
b
a
d
e
F
Anode seven-segment
LED display
active low
0
0
1
1
1
1
1
1
0
0
1
74xxx47
D
C
B
A
a
b
c
d
e
f
g
BCD to seven-segment Decoder
g
c
b
a
d
e
F
Cathode seven-segment
LED display
active high
0
0
1
1
0
0
0
0
1
1
0
Encoder
Encoder perform a function that is the
inverse of decoders,
Encoders have more input than output
variables,It produce n outputs from 2n
inputs
74xx147
10-line to BCD encoder
74xx148
8-line to 3-line priority encoder
Encoder
Typical
encoder
Enable
inputs
n-data
outputs
2n
data
inputs
Encoder
74xx147
10-line to BCD encoder
Typical application
Encode decimal keypad or switching
panel output data into BCD
Ex,Figure 4.30
Encoder
74xx148
8-line to 3-line priority encoder
Ex,
It can be used to identify an event and
assign and transmit a code to the control
unit based on some priority.
Connect the devices to the inputs according
to priority,Device with higher priority
connects to the higher bit input port.
Multiplexer
Digital multiplexer provides the digital
equivalent of an analog selector switch,
It connects one of n inputs to a single
output line,so that the logical value of the
input is transferred to the output.
The one of n input selection is determined
by m select inputs,where n=2m.
Multiplexer
n select
inputs
2n data
inputs Y
Y ’
Multiplexer
It can be used as Boolean function generator.
N-to-1 multiplexer
D0,D1,……,Dn-1 be the data input variables
A0,A1,……,Am be the select input variables
n=2m.
It can be used to generate up to n minterms.
mi is the minterm consisting of the select
input A0,A1,……,Am.
Multiplexer
It can be used as Boolean function generator.
N-to-1 multiplexer
n=2m
Output Y= i
n －
i= 0
i Dm?∑
1
Multiplexer
If the number of variables in the
minterm is equal to the number of
select lines
To connect the function variables
directly to the select inputs.
If a minterm i exists in a function,we
assign high level 1 to the corresponding
data inputs Di,
Assign lower level 0 to the residual data
input,
Multiplexer
Select input=A,B,C,D
D0=D1=D2=D3=D5=D8=D9=D11=D14=D15=1
D4=D6=D7=D10=D12=D13=0
F(A,B,C,D)
=∑m(0,1,2,3,5,8,9,11,13,14,15)
16-to-1 multiplexer
Multiplexer
F(A,B,C,D)=∑m(0,1,2,3,5,8,9,11,13,14,15)
=A’B’C’D’ +A’B’C’D +A’B’CD’ +A’B’CD +A’BC’D +AB’C’D’
+AB’C’D+AB’CD+ABC’D+ABCD’+ABCD
16-to-1 multiplexer
ABCD are all the select inputs
Y=∑miDi (0≤i≤15)
=A’B’C’D’·D0 +A’B’C’D·D1 +A’B’CD’·D2 +A’B’CD·D3 +A’BC’D’·D4
+A’BC’D·D5 +A’BCD’·D6 +A’BCD·D7 +AB’C’D’·D8 +AB’C’D·D9
+AB’CD’·D10 +AB’CD·D11 +ABC’D’·D12+ABC’D·D13 +ABCD’·D14
+ABCD·D15
Y=F,compare two expressions
D0=1; D1=1; D2=1; D3=1; D4=0; D5=1; D6=0; D7=0;
D8=1; D9=1; D10=0; D11=1; D12=0; D13=1; D14=1; D15=1
Multiplexer
If the number of variables in the
minterm is less than the number of
select lines
F(A,B,C,D)
=∑m(0,1,2,3,5,8,9,11,13,14,15)
8-to-1 multiplexer
Multiplexer
solution
Three variable are used as select inputs.
The fourth is connected as need to the
multiplexer,
F(A,B,C,D)
=∑m(0,1,2,3,5,8,9,11,13,14,15)
8-to-1 multiplexer
Multiplexer
F(A,B,C,D)=∑m(0,1,2,3,5,8,9,11,13,14,15)
=A’B’C’D’+A’B’C’D+A’B’CD’+A’B’CD+A’BC’D +AB’C’D’
+AB’C’D +AB’CD +ABC’D +ABCD’ +ABCD
8-to-1 multiplexer
Treat ABC as the select inputs
mi consists of A,B and C.
Y=∑miDi (0≤i≤7)
=A’B’C’·D0 +A’B’C·D1 +A’BC·D2 +A’BC·D3 +AB’C’·D4 +AB’C·D5
+ABC’·D6 +ABC·D7
Y=F,compare two expressions
D0=D’+D=1; D1=D’+D=1; D2=D; D3=0;
D4=D+D’=1; D5=D; D6=D; D7=D’+D=1;
1
1
1
1
1
1
1
1
1
1
1
Multiplexer
F(A,B,C,D)=∑m(0,1,2,3,5,8,9,11,13,14,15)
00 01 11 10
AB
CD
00
01
11
10
0 4 12 8
1 5 13 9
3 7 15 11
2 6 14 10
1
1
1
1
1
1
1
1
1
1
1
Y= ∑miDi (0≤i≤7)
= A’B’C’·D0 +A’B’C·D1
+A’BC·D2 +A’BC·D3
+AB’C’·D4 +AB’C·D5
+ABC’·D6 +ABC·D7
Y=F
D0=D’+D=1; D1=D’+D=1; D2=D; D3=0;
D4=D+D’=1; D5=D; D6=D; D7=D’+D=1;
Multiplexer
F(A,B,C,D)
=∑m(0,1,2,3,5,8,9,11,13,14,15)
4-to-1 multiplexer
Multiplexer
F(A,B,C,D)=∑m(0,1,2,3,5,8,9,11,13,14,15)
=A’B’C’D’+A’B’C’D+A’B’CD’+A’B’CD
+ A’BC’D
+ AB’C’D’ +AB’C’D +AB’CD
+ ABC’D +ABCD’ +ABCD
4-to-1 multiplexer
Treat AB as the select inputs
mi consists of A and B.
Y=∑miDi (0≤i≤3)
=A’B’·D0 +A’B·D1 +AB’·D2 +AB·D3
D0=C’D’+C’D+CD’+CD=1;
D1=C’D’;
D2=C’D’+C’D+CD=D+C’;
D3=C’D+CD’+CD=D+C;
Multiplexer
F(A,B,C,D)=∑m(0,1,2,3,5,8,9,11,13,14,15)
4-to-1 multiplexer
Treat AB as the select inputs
mi consists of A and B.
Y=∑miDi (0≤i≤3)
=A’B’·D0 +A’B·D1 +AB’·D2 +AB·D3
Y=F
D0=C’D’+C’D+CD’+CD=1;
D1=C’D’;
D2=C’D’+C’D+CD=D+C’;
D3=C’D+CD’+CD=D+C;
00 01 11 10
AB
CD
00
01
11
10
0 4 12 8
1 5 13 9
3 7 15 11
2 6 14 10
1
1
1
1
1
1
1
1
1
1
1
MSI Adder
A4 A3 A2 A1 B4 B3 B2 B1
F4 F3 F2 F1
CO CI
MSI Adder
Cascading full-adders
An n-bit adder can be built by cascading
(connecting in series) n full-adders,Each carry-
out from a full-adder become the carry-in to the
next full-adder.
The carries propagate from one full-adder to the
next higher order full-adder,This type of
addition is call ripple-carry propagation.
Total delay time is the product of the sum of
stages in the adder,and the carry-in to carry-out
propagation delay time,
Parallel adder
74xx83A is a four-bit binary parallel adder
with a fast carry feature.
The look-ahead carry,or fast carry,technique
reduces propagation times through the adder.
This is accomplished by generating all the
individual carry terms need by each full-adder
in as few levels of logic as possible.
MSI Adder
MSI Adder
The carry output of any full-adder stage in a
multiple-stage is written Ci
Ci=XiYi+(Xi+Yi)Ci-1
If both of (Xi,Yi) are a 1,Ci=1
If either of (Xi,Yi) is a 1,Ci=Ci-1,
MSI Adder
Ci=XiYi+(Xi+Yi)Ci-1
let carry-propagation Pi=Xi+Yi
let carry-generate Gi= XiYi,
Ci= Gi + PiCi-1
C1= P1C0 + G1
C2= P2P1C0 + P2G1+ G2
C3= P3P2P1C0 + P3P2G1+ P3G2 +G3
C4= P4P3P2P1C0 + P4P3P2G1+ P4P3G2 +P4G3+G4
MSI Adder
Ci= Gi + PiCi-1
C1= P1C0 + G1
C2= P2P1C0 + P2G1+ G2
C3= P3P2P1C0 + P3P2G1+ P3G2 +G3
C4= P4P3P2P1C0 + P4P3P2G1+ P4P3G2 +P4G3+G4
Each carry-out need three level of logic to realize,
The adder propagation delay is constant,not
dependent on the ripple carry.
MSI Adder
Using an MIS adder as a 8421BCD to Ex-3 code
converter.
4 input variables,b8b4b2b1
4 output variables,e4e3e2e1
A4A3A2A1 B4B3B2B1
F4 F3 F2 F1
CO CI
e4 e3 e2 e1
b8b4b2b10 0 1 1
,0”
MSI Adder
Using a four-bit binary parallel adder as a four-bit
binary adder/subtracter,
Find the radix complement of the subtrahend and
add it to the minuend to produce the difference.
8 value input
a+b =a4a3a2a1+b4b3b2b1+0
a-b = a4a3a2a1-b4b3b2b1
= a4a3a2a1+b4’b3’b2’b1’+1
1 control input
M=0,a+b
M=1,a-b
MSI Adder
A4A3A2A1
A4=a4 ; A3=a3 ; A2=a2 ; A1=a1;
B4B3B2B1
M=0,Bi=bi;
M=1,Bi=bi’;
Bi=f(M,bi) =M⊕ bi;
CI
M=0,CI=0;
M=1,CI=1;
CI=f(M)=M;
MSI Adder
Peripheral
design
A4A3A2A1 B4B3B2B1
F4 F3 F2 F1
CO CI
e4 e3 e2 e1
a4a3a2a1
M
=1
=1
=1
=1
b4
b3
b2
b1
MSI Adder
Using four-bit binary parallel adders to realize a 1-bit decimal
adder represented by Ex-3 code.
(A+B)10=(JC)10=J*10+C
(C)ex-3
C4
C3
C2
C1
(A)ex-3
(B)ex-3
A4
A3
A2
A1
B4
B3
B2
B1
Logic
circuit
J
MSI Adder
8 input variables,
(A)ex-3= A4A3A2A1
(B)ex-3= B4B3B2B1
4 output variables,
(C)ex-3=C4C3C2C1
the output of MSI adder – F,Co
CoF4F3F2F1= A4A3A2A1+B4B3B2B1
Key,
find the relationship between F and (C)ex-3
(A)2=a4a3a2a1 ; (A)ex-3=(A)2+0011;
A4A3A2A1=a4a3a2a1+0011
(B)2=b4b3b2b1 ; (B)ex-3=(B)2+0011
B4B3B2B1=b4b3b2b1+0011
(C)2=c4c3c2c1 ; (C)ex-3=(C)2+0011
C4C3C2C1=c4c3c2c1+0011
CoF4F3F2F1 = (A)ex-3+ (B)ex-3
CoF4F3F2F1 = A4A3A2A1 + B4B3B2B1
= a4a3a2a1+0011+b4b3b2b1+0011
= a4a3a2a1+b4b3b2b1+0110
MSI Adder
J=0,A+B<10
A+3+B+3<16
CoF4F3F2F1=(A)EX-3+(B)EX-3<10000
Co=0
J=1,A+B>=10
A+3+B+3>=16
CoF4F3F2F1=(A)EX-3+(B)EX-3>=10000
Co=1
J=Co
MSI Adder
if (A+B)<10? J=0? A+B=C
(A)2+(B)2=(C)2
(A)ex-3+ (B)ex-3
= A4A3A2A1+B4B3B2B1
= (a4a3a2a1+b4b3b2b1)+0110
= c4c3c2c1+0110
= (c4c3c2c1+0011)+0011
= C4C3C2C1+0011
= (C)ex-3+0011
(C)ex-3= F4F3F2F1 – 0011= F4F3F2F1 +1101
MSI Adder
if (A+B)>10?J=1?A+B=10+C
C=A+B-10
(C)2=(A)2+(B)2-(10)2=(A)2+(B)2-1010
(A)ex-3+ (B)ex-3
= A4A3A2A1+B4B3B2B1
= (a4a3a2a1+b4b3b2b1)+0110
= (c4c3c2c1+1010)+0110
= c4c3c2c1+10000
= 1c4c3c2c1 = 1F4F3F2F1
(C)ex-3= F4F3F2F1 +0011
MSI Adder
