Flip-flops
Chapter4
Flip-flops
Flip-flops are digital devices that have
the ability to store binary information
after the excitation input has changed.
They are considered to be the basic
memory cell for the majority of
electronic binary data storage
applications.
This section explores the flip-flop from
a functional perspective.
R S
QQ’
Two output Q and Q’,And Q’ is the complement of
Q.
Two stable state,either a 0 or a 1.,Q=1” is the
state-1 and,Q=0” is the state-0,The state would
be remained without the changing of input
variables,
By the excitation of certain input variables,flip-
flop changes from one stable state to another
stable state,The state prior to the excitation of
input is present-state,represented by symbol
“Qn(Q)”,the state after the excitation of input is
next-state,represented by symbol,Qn+1”.
Four types of flip-flops are commonly
considered,JK,SR,D and T.
Each store binary data but have a unique
set of input variables.
Each flip-flop can be described in terms
of input and output characteristics by
writing special truth table,called an
excitation table.
A characteristics equation can be
generated from the excitation tables.
Flip-flops vs Latches
The names flip-flops and latches are
sometimes used interchangeably;
Flip-flops are clocked and latch are not,
The term,flip-flop” is more appropriately
associated with devices change state only
on a clock edge or pulse,whereas latches
change state without being clocked.
R-S NAND Latch
Analysis
R=1,S=1 Qn+1=(SQ’)’=Q;
Qn+1’=(RQ)’=Q’;
R=1,S=0 Qn+1=1;
Qn+1’=0;
R=0,S=1 Qn+1=0;
Qn+1’=1;
R=0,S=0 Qn+1=1;
Qn+1’=1;
R S
QQ’
R
S
Q’
Q
&a &b
'Q Q
R S
R=0,S=1 10 ='= QQ
1
1
0
0
1
0 1
0
Output next state 10 ='= QQ
Present state
&a &b
'Q Q
R S
R=0,S=1 01 ='= QQ
0
1
1
1
1
0 1
0
Output next state 10 ='= QQ
Present state
R=1,S=0 10 ='= QQ
1 0
1 01
0
1
1
Output next state 01 ='= QQ
&a &b
'Q Q
R S
Present state
01 ='= QQ
0
0
1
1
0
1 0
1
&a &b
'Q Q
R S
Present stateR=1,S=0
Output next state 01 ='= QQ
R=1,S=1
10
1 11
0
0
1
&a &b
'Q Q
R S
Present state 01 ='= QQ
Output next state 01 ='= QQ
01
1 10
1
1
0
&a &b
'Q Q
R S
R=1,S=1 Present state 10 ='= QQ
Output next state 10 ='= QQ
R=0,S=0
0 0
1 1
&a &b
'Q Q
R S
Present state
Output next state 11 ='= QQ
R-S NAND Latch
Analysis
R=1,S=1 Qn+1=(SQ’)’=Q;
Qn+1’=(RQ)’=Q’;
R=1,S=0 Qn+1=1;
Qn+1’=0;
R=0,S=1 Qn+1=0;
Qn+1’=1;
R=0,S=0 Qn+1=1;
Qn+1’=1;
R S
QQ’
R
S
Q’
Q
R-S NAND Latch
By definition,Q can never be equal to Q’
because one is the inverse of the other.
when RS=00,the circuit will cause Q=Q’,It
creates an undefined condition for Q and Q’
output.
Therefore,the case when RS=00 is illegal and
not allow for the NAND latch.
00
R=0,S=0
1 1
R=1,S=1
11 1 1
0
0R S
QQ’
G1 G2
TG1>TG2
Output next state 10 ='= QQ
00
R=0,S=0
1 1
R=1,S=1
11 1 1
0
0R S
QQ’
G1 G2
TG1<TG2
Output next state 01 ='= QQ
00
R=0,S=0
1 1
R=1,S=1
11 1 1
0 0
R S
QQ’
G1 G2
TG1=TG2
No stable output,Oscillate
0 0
1
1
R-S NOR Latch
Analysis
R=0,S=0 Qn+1=Q;
Qn+1’=Q’;
R=1,S=0 Qn+1=0;
Qn+1’=1;
R=0,S=1 Qn+1=1;
Qn+1’=0;
R=1,S=1 Qn+1=0;
Qn+1’=0;
S R
QQ’
S
R
Q’
Q
R-S NOR Latch
By definition,Q can never be equal to Q’
because one is the inverse of the other.
when RS=11,the circuit will cause Q=Q’,It
creates an undefined condition for Q and Q’
output.
Therefore,the case when RS=11 is illegal and
not allow for the NOR latch.
R-S clocked FLIP-FLOPS
R
S
Q’
Q
C
R’ S’
QQ’
R S
CP
R-S clocked FLIP-FLOPS
R’ S’
QQ’
R S
CP
R S
QQ’
R-S NAND Latch
R=1,S=1 Qn+1=Q;
R=1,S=0 Qn+1=1;
R=0,S=1 Qn+1=0;
R=0,S=0
R-S clocked FLIP-FLOPS
Analysis
CP=1
R=0,S=0 Qn+1=(SQ’)’=Q;
Qn+1’=(RQ)’=Q’;
R=0,S=1 Qn+1=1; Qn+1’=0;
R=1,S=0 Qn+1=0; Qn+1’=1;
R=1,S=1 Qn+1=1; Qn+1’=1;
CP=0
Qn+1=(SQ’)’=Q;
Qn+1’=(RQ)’=Q’;
R’ S’
QQ’
R S
CP
R-S clocked FLIP-FLOP
Excitation table
Characteristics
equation
Qn+1=S+R’Q
R?S=0 (limitation)
RS=00,remain same
RS=01/10,Qn+1=S
RS=11,indeterminate
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
d
d
R S Qn Qn+1
0
0
1
1
0
0
1
1
00 01 11 10
0
1
0
1
2
3
6
7
4
5
RSQ
1
1
1
d
d
D clocked FLIP-FLOPS
D
Q’
Q
CR’ S’
QQ’
R S
CPCP
R’ S’
QQ’
D
D’
D clocked FLIP-FLOPS
R’ S’
QQ’
R S
CP
CP
R’ S’
QQ’
D
D’ (S)(R)
S=R’,Qn+1=S=D
RS=00,remain same
RS=01/10,Qn+1=S
RS=11,indeterminate
D clocked FLIP-FLOPS
Analysis
CP=1
D=0 Qn+1=0;
Qn+1’=1;
D=1 Qn+1=1;
Qn+1’=0;
CP=0
Qn+1=Q;
Qn+1’=Q’;
CP
R’ S’
QQ’
D
D’
D clocked FLIP-FLOPS
Excitation table
Characteristics
equation
Qn+1=S+R’Q
=D+D’Q
=D
Qn+1=D
0
0
1
1
0
1
0
1
0
0
1
1
D Qn Qn+1
J-K clocked FLIP-FLOPS
K
J
Q’
QCR’ S’
QQ’
K J
CP
Analysis
CP=1
J=0,K=0
Qn+1=Q;
Qn+1’ =Q’;
R’ S’
QQ’
K J
CP
0 0
1 1
R-S NAND Latch
R=1,S=1 Qn+1=(SQ’)’=Q; Qn+1’=(RQ)’=Q’;
Analysis
CP=1
J=1,K=0,Q=1
Qn+1=1;
Qn+1’ =0;
R’ S’
QQ’
K J
CP
0 1
1 1
R-S NAND Latch
R=1,S=1 Qn+1=(SQ’)’=Q; Qn+1’=(RQ)’=Q’;
10 10
R’ S’
QQ’
K J
CP
0 1
1 0
R-S NAND Latch
R=1,S=0 Qn+1=1; Qn+1’=1;
01 10? Analysis
CP=1
J=1,K=0,Q=0
Qn+1=1;
Qn+1’ =0;
R’ S’
QQ’
K J
CP
0 1
10? Analysis
CP=1
J=1,K=0
Qn+1=1;
Qn+1’ =0;
R’ S’
QQ’
K J
CP
1 0
01? Analysis
CP=1
J=0,K=1
Qn+1=0;
Qn+1’ =1;
R-S NAND Latch
R=0,S=1 Qn+1=0; Qn+1’=1;
Analysis
CP=1
J=1,K=1,Q=0
Qn+1=1;
Qn+1’ =0;
R’ S’
QQ’
K J
CP
1 1
0 1
10
01
R-S NAND Latch
R=1,S=0 Qn+1=1; Qn+1’=0;
Analysis
CP=1
J=1,K=1,Q=0
Qn+1=1;
Qn+1’ =0;
R’ S’
QQ’
K J
CP
1 1
1 0
01
10
R’ S’
QQ’
K J
CP
1 1
Qn’Qn? Analysis
CP=1
J=1,K=1
Qn+1=Q’;
Qn+1’ =Q;
J-K clocked FLIP-FLOPS
Analysis
CP=1
J=0,K=0 Qn+1=Q; Qn+1’ =Q’;
J=1,K=0 Qn+1=1; Qn+1’=0;
J=0,K=1 Qn+1=0; Qn+1’=1;
J=1,K=1 Qn+1=Q’; Qn+1’=Q;
CP=0
Qn+1=Q;
Qn+1’=Q’; K
J
Q’
QC
R’ S’
QQ’
K J
CP
J-K clocked FLIP-FLOPS
Excitation table
Characteristics
equation
Qn+1=JQ’+K’Q
JK=00,remain same
JK=01/10,Qn+1=J
JK=11,toggle
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
0
J K Qn Qn+1
0
0
1
1
0
0
1
1
00 01 11 10
0
1
0
1
2
3
6
7
4
5
JKQ
1
1
1
1
T clocked FLIP-FLOPS
Analysis
CP=1
T=1 Qn+1=Q’;
Qn+1=Q;
T=0 Qn+1=Q;
Qn+1’=Q’;
CP=0
Qn+1=Q;
Qn+1’=Q’;
R’ S’
QQ’
T
CP
T
Q’
Q
C
T clocked FLIP-FLOPS
Excitation table
Characteristics
equation
Qn+1=TQ’+T’Q
T=0,remain same
T=1,toggle
0
0
1
1
0
1
0
1
0
1
1
0
T Qn Qn+1
Master-slave
FLIP-FLOPS
Consider the following timing diagram
CLK
D
Q Hazard 1
J-k Clocked
Flip-Flops
CP=1
J=0,K=0
Qn+1=Q; Qn+1’ =Q’;
J=1,K=0
Qn+1=1; Qn+1’=0;
J=0,K=1
Qn+1=0; Qn+1’=1;
J=1,K=1
Qn+1=Q’; Qn+1’=Q;
R’ S’
QQ’
K J
CP
Consider the following timing diagram
CLK
J
K
Q
Master-slave FLIP-FLOPS
M-s flip-flops are constructed by
connecting two flip-flips in a cascade.
To protect a flip-flop’s output from
inadvertent changes caused by glitches
on the input.
Master-slave flip-flops are used in
applications where glitches may be
prevalent on input.
S
R
R-S flip-flop
S
R
Basic core is a RS latch
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
Q
G1
G2
&
&
G3
G4
G9
MQ’ Q’
MQ
When CP goes
from 1 to 0，
master be locked,
slave toggled
according to the
master-state,
Toggle be achieved by two steps
When CP＝ 1,slave be
locked,master accept
the excitations,set
the corresponded
master-state while
slave-states remain
same,
The basic core is a RS latch.
Toggle be achieved by two steps
When CP＝ 1,slave be locked,master
accept the excitations,set the
corresponded master-state while slave-
states remain same,
When CP goes from 1 to 0,master be
locked,slave toggled according to the
master-state,
RS flip-flop
RS=00,remain same;
RS=01/10,Qn+1=S;
RS=11,indeterminate
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
Q
G1
G2
&
&
G3
G4
G9
MQ’ Q’
MQ
RS latch
RS=11,remain same;
RS=01/10,Qn+1=R;
RS=00,indeterminate;
S
S
R
R
MQ ≠ MQ’;
RS=01/10,Qn+1=S=MQ;
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
Q
G1
G2
&
&
G3
G4
G9
MQ’ Q’
MQ
S
S
R
R
CP=1->0
master be locked
Slave toggled
Qn+1=MQ
CP=0
master be locked
Slave R-S flip-flop
Qn+1=MQ
master slave
&
&
K
J
G5
G6
&
&
G7
G8
CP
&
&
Q
G1
G2
&
&
G3
G4
G9
Q’
MQ’
MQ
CP
X X
X’
R
S
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
Q’
01
0
0
1
1
MQ’
MQ
CP=0,Q=MQ;
Q=MQ=x
x
x’
x
x’
S
R
J=0,K=0,CP=1
G7(CP,J,Qn’)=1,G8(CP,K,Qn) =1,MQn+1=MQ=x ;
J=0,K=0,CP=1->0,
MQ=x,Qn+1=MQ=x=Qn;
R
S
R
S &
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
MQ’ Q’
MQ
CP=0,Q=MQ;
J=0,K=0,CP=1,G7(CP,J,Qn’),G8(CP,K,Qn)
Qn’=1,Qn=0,G7(1,0,1)=1,G8(1,0,0)=1,MQn+1=MQn ;
Qn’=0,Qn=1,G7(1,0,0)=1,G8(1,0,1)=1,MQn+1=MQn ;
J=0,K=0,CP=1->0
Qn+1=MQn+1=MQn=Qn;
0
0
J=0,K=0,CP=1->0
Qn+1=Qn
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
MQ’ Q’
MQ
R
R
S S0
0
R
S
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
Q’
01
0
1
1
0
CP=0,Q=MQ;
Q=MQ=1
1
0
1
0
S
R
J=0,K=1,CP=1->0,
Qn+1=MQn+1=0;
J=0,K=1,CP=1
G7(CP,J,Qn’)=1,G8(CP,K,Qn) =0,MQn+1=0 ;
MQ
MQ’
0
1
0
1
R
S
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
Q’
01
0
1
1
1
CP=0,Q=MQ;
Q=MQ=0
0
1
0
1
S
R
J=0,K=1,CP=1->0,
Qn+1=MQn+1=0;
J=0,K=1,CP=1
G7(CP,J,Qn’)=1,G8(CP,K,Qn) =1,MQn+1=0 ;
MQ
MQ’
J=0,K=1,CP=1->0
Qn+1=MQn+1=0;
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
MQ’ Q’
MQ
R
R
S S0
1
CP=0,Q=MQ;
J= 1,K=0,CP=1,G7(CP,J,Qn’),G8(CP,K,Qn)
Qn’=1,Qn=0,G7(1,1,1)=0,G8(1,0,0)=1,MQn+1=1 ;
Qn’=0,Qn=1,G7(1,1,0)=1,G8(1,0,1)=1,MQn+1=MQn=Qn=1;
J=1,K=0,CP=1->0
Qn+1=MQn+1=1;
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
MQ’ Q’
MQ
R
R
S S1
0
J=1,K=0,CP=1->0
Qn+1=1
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
MQ’ Q’
MQ
R
R
S S
R
S
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
Q’
01
1
1
1
0
CP=0,Q=MQ;
Q=MQ=1
1
0
1
0
S
R
J=0,K=1,CP=1->0,
Qn+1=MQn+1=0;
J=1,K=1,CP=1
G7(CP,J,Qn’)=1,G8(CP,K,Qn) =0,MQn+1=0 ;
MQ
MQ’
0
1
0
1
R
S
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
Q’
01
1
1
0
1
CP=0,Q=MQ;
Q=MQ=0
0
1
0
1
S
R
J=0,K=1,CP=1->0,
Qn+1=MQn+1=1;
J=1,K=1,CP=1
G7(CP,J,Qn’)=0,G8(CP,K,Qn) =1,MQn+1=1 ;
MQ
MQ’
1
0
1
0
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
MQ’ Q’
MQ
J= 1,K=1,CP=1,G7(CP,J,Qn’),G8(CP,K,Qn)
Qn’=1,Qn=0,G7(1,1,1)=0,G8(1,1,0)=1,MQn+1=1 ;
Qn’=0,Qn=1,G7(1,1,0)=1,G8(1,1,1)=0,MQn+1=0;
J=1,K=1,CP=1->0
Qn+1=MQn+1=1 (Qn=0); Qn+1=MQn+1=0(Qn=1);
R
R
S S1
1
J=1,K=1,CP=1->0
Qn+1= Qn’
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
MQ’ Q’
MQ
R
R
S S
1
1
J=1,K=1,Qn+1= Qn’
J=0,K=1,Qn+1= 0
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
MQ’ Q’
MQ
R
R
S S
J=0,K=0,Qn+1= Qn
J=1,K=0,Qn+1= 1
Master-slave FLIP-FLOPS
J
K
Q
CP
Q’
Edge triggered
FLIP-FLOPS
Consider the following timing diagram
CLK
J
K
Q
To solute the oscillation of the output
Edge triggered flip-flops initiate Q
output changes on the rising or falling
edge of the clock input.
Many problems attributed to improper
triggering of latches or gated latch
are eliminated.
Positive edge triggered flip-flop
Negative edge triggered flip-flop
CLK &
&
CLK-Edge
DEL-CLK
DEL-CLK=(CLK)’
CLK-Edge=CLK · DEL-CLK =CLK · (CLK)’ =0
CLK
DEL-CLK
CLK-Edge
Propagation delay
delay(DEL-CLK)=t
delay(CLK-Edge)=2t
Momentary 1 glitch
Glitch pulse width is t
Edge triggered FLIP-FLOPS
JK flip-flop
JK=00,Qn+1=Qn;
JK=01/10,Qn+1=J;
JK=11,Qn+1=Qn’,toggle
J
CP
&
&
QG1
G2
&
&
G3
G4
Q’
&& G7 G6
K
Positive edge triggered
JK flip-flops
Edge triggered FLIP-FLOPS
J
CP
&
&
QG1
G2
&
&
G3
G4
Q’
&& G7 G6
K
Positive edge triggered
JK flip-flops
K
J
Q’
QC
Edge triggered FLIP-FLOPS
JK flip-flop
JK=00,Qn+1=Qn;
JK=01/10,Qn+1=J;
JK=11,Qn+1=Qn’,toggle
negative edge triggered
JK flip-flops
J
CP
&
&
QG1
G2
&
&
G3
G4
Q’
&&
G6
G5
K
& G7
Edge triggered FLIP-FLOPS
negative edge triggered
JK flip-flops
J
CP
&
&
QG1
G2
&
&
G3
G4
Q’
&&
G6
G5
K
& G7
K
J
Q’
QC
Positive Edge Triggered Flip-flops
J
K
Q
CP
Q’
Negative edge triggered flip-flops
J
K
Q
CP
Q’
Flip-flop timing specifications
Pulse width
Setup time
The time that the excitation inputs to a
flip-flop device must remain stable prior to
the arrival of the clock edge that triggers
the device.
Hold time
The time that the excitation inputs must
remain stable after the clock edge has
occurred.
Chapter4
Flip-flops
Flip-flops are digital devices that have
the ability to store binary information
after the excitation input has changed.
They are considered to be the basic
memory cell for the majority of
electronic binary data storage
applications.
This section explores the flip-flop from
a functional perspective.
R S
QQ’
Two output Q and Q’,And Q’ is the complement of
Q.
Two stable state,either a 0 or a 1.,Q=1” is the
state-1 and,Q=0” is the state-0,The state would
be remained without the changing of input
variables,
By the excitation of certain input variables,flip-
flop changes from one stable state to another
stable state,The state prior to the excitation of
input is present-state,represented by symbol
“Qn(Q)”,the state after the excitation of input is
next-state,represented by symbol,Qn+1”.
Four types of flip-flops are commonly
considered,JK,SR,D and T.
Each store binary data but have a unique
set of input variables.
Each flip-flop can be described in terms
of input and output characteristics by
writing special truth table,called an
excitation table.
A characteristics equation can be
generated from the excitation tables.
Flip-flops vs Latches
The names flip-flops and latches are
sometimes used interchangeably;
Flip-flops are clocked and latch are not,
The term,flip-flop” is more appropriately
associated with devices change state only
on a clock edge or pulse,whereas latches
change state without being clocked.
R-S NAND Latch
Analysis
R=1,S=1 Qn+1=(SQ’)’=Q;
Qn+1’=(RQ)’=Q’;
R=1,S=0 Qn+1=1;
Qn+1’=0;
R=0,S=1 Qn+1=0;
Qn+1’=1;
R=0,S=0 Qn+1=1;
Qn+1’=1;
R S
QQ’
R
S
Q’
Q
&a &b
'Q Q
R S
R=0,S=1 10 ='= QQ
1
1
0
0
1
0 1
0
Output next state 10 ='= QQ
Present state
&a &b
'Q Q
R S
R=0,S=1 01 ='= QQ
0
1
1
1
1
0 1
0
Output next state 10 ='= QQ
Present state
R=1,S=0 10 ='= QQ
1 0
1 01
0
1
1
Output next state 01 ='= QQ
&a &b
'Q Q
R S
Present state
01 ='= QQ
0
0
1
1
0
1 0
1
&a &b
'Q Q
R S
Present stateR=1,S=0
Output next state 01 ='= QQ
R=1,S=1
10
1 11
0
0
1
&a &b
'Q Q
R S
Present state 01 ='= QQ
Output next state 01 ='= QQ
01
1 10
1
1
0
&a &b
'Q Q
R S
R=1,S=1 Present state 10 ='= QQ
Output next state 10 ='= QQ
R=0,S=0
0 0
1 1
&a &b
'Q Q
R S
Present state
Output next state 11 ='= QQ
R-S NAND Latch
Analysis
R=1,S=1 Qn+1=(SQ’)’=Q;
Qn+1’=(RQ)’=Q’;
R=1,S=0 Qn+1=1;
Qn+1’=0;
R=0,S=1 Qn+1=0;
Qn+1’=1;
R=0,S=0 Qn+1=1;
Qn+1’=1;
R S
QQ’
R
S
Q’
Q
R-S NAND Latch
By definition,Q can never be equal to Q’
because one is the inverse of the other.
when RS=00,the circuit will cause Q=Q’,It
creates an undefined condition for Q and Q’
output.
Therefore,the case when RS=00 is illegal and
not allow for the NAND latch.
00
R=0,S=0
1 1
R=1,S=1
11 1 1
0
0R S
QQ’
G1 G2
TG1>TG2
Output next state 10 ='= QQ
00
R=0,S=0
1 1
R=1,S=1
11 1 1
0
0R S
QQ’
G1 G2
TG1<TG2
Output next state 01 ='= QQ
00
R=0,S=0
1 1
R=1,S=1
11 1 1
0 0
R S
QQ’
G1 G2
TG1=TG2
No stable output,Oscillate
0 0
1
1
R-S NOR Latch
Analysis
R=0,S=0 Qn+1=Q;
Qn+1’=Q’;
R=1,S=0 Qn+1=0;
Qn+1’=1;
R=0,S=1 Qn+1=1;
Qn+1’=0;
R=1,S=1 Qn+1=0;
Qn+1’=0;
S R
QQ’
S
R
Q’
Q
R-S NOR Latch
By definition,Q can never be equal to Q’
because one is the inverse of the other.
when RS=11,the circuit will cause Q=Q’,It
creates an undefined condition for Q and Q’
output.
Therefore,the case when RS=11 is illegal and
not allow for the NOR latch.
R-S clocked FLIP-FLOPS
R
S
Q’
Q
C
R’ S’
QQ’
R S
CP
R-S clocked FLIP-FLOPS
R’ S’
QQ’
R S
CP
R S
QQ’
R-S NAND Latch
R=1,S=1 Qn+1=Q;
R=1,S=0 Qn+1=1;
R=0,S=1 Qn+1=0;
R=0,S=0
R-S clocked FLIP-FLOPS
Analysis
CP=1
R=0,S=0 Qn+1=(SQ’)’=Q;
Qn+1’=(RQ)’=Q’;
R=0,S=1 Qn+1=1; Qn+1’=0;
R=1,S=0 Qn+1=0; Qn+1’=1;
R=1,S=1 Qn+1=1; Qn+1’=1;
CP=0
Qn+1=(SQ’)’=Q;
Qn+1’=(RQ)’=Q’;
R’ S’
QQ’
R S
CP
R-S clocked FLIP-FLOP
Excitation table
Characteristics
equation
Qn+1=S+R’Q
R?S=0 (limitation)
RS=00,remain same
RS=01/10,Qn+1=S
RS=11,indeterminate
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
d
d
R S Qn Qn+1
0
0
1
1
0
0
1
1
00 01 11 10
0
1
0
1
2
3
6
7
4
5
RSQ
1
1
1
d
d
D clocked FLIP-FLOPS
D
Q’
Q
CR’ S’
QQ’
R S
CPCP
R’ S’
QQ’
D
D’
D clocked FLIP-FLOPS
R’ S’
QQ’
R S
CP
CP
R’ S’
QQ’
D
D’ (S)(R)
S=R’,Qn+1=S=D
RS=00,remain same
RS=01/10,Qn+1=S
RS=11,indeterminate
D clocked FLIP-FLOPS
Analysis
CP=1
D=0 Qn+1=0;
Qn+1’=1;
D=1 Qn+1=1;
Qn+1’=0;
CP=0
Qn+1=Q;
Qn+1’=Q’;
CP
R’ S’
QQ’
D
D’
D clocked FLIP-FLOPS
Excitation table
Characteristics
equation
Qn+1=S+R’Q
=D+D’Q
=D
Qn+1=D
0
0
1
1
0
1
0
1
0
0
1
1
D Qn Qn+1
J-K clocked FLIP-FLOPS
K
J
Q’
QCR’ S’
QQ’
K J
CP
Analysis
CP=1
J=0,K=0
Qn+1=Q;
Qn+1’ =Q’;
R’ S’
QQ’
K J
CP
0 0
1 1
R-S NAND Latch
R=1,S=1 Qn+1=(SQ’)’=Q; Qn+1’=(RQ)’=Q’;
Analysis
CP=1
J=1,K=0,Q=1
Qn+1=1;
Qn+1’ =0;
R’ S’
QQ’
K J
CP
0 1
1 1
R-S NAND Latch
R=1,S=1 Qn+1=(SQ’)’=Q; Qn+1’=(RQ)’=Q’;
10 10
R’ S’
QQ’
K J
CP
0 1
1 0
R-S NAND Latch
R=1,S=0 Qn+1=1; Qn+1’=1;
01 10? Analysis
CP=1
J=1,K=0,Q=0
Qn+1=1;
Qn+1’ =0;
R’ S’
QQ’
K J
CP
0 1
10? Analysis
CP=1
J=1,K=0
Qn+1=1;
Qn+1’ =0;
R’ S’
QQ’
K J
CP
1 0
01? Analysis
CP=1
J=0,K=1
Qn+1=0;
Qn+1’ =1;
R-S NAND Latch
R=0,S=1 Qn+1=0; Qn+1’=1;
Analysis
CP=1
J=1,K=1,Q=0
Qn+1=1;
Qn+1’ =0;
R’ S’
QQ’
K J
CP
1 1
0 1
10
01
R-S NAND Latch
R=1,S=0 Qn+1=1; Qn+1’=0;
Analysis
CP=1
J=1,K=1,Q=0
Qn+1=1;
Qn+1’ =0;
R’ S’
QQ’
K J
CP
1 1
1 0
01
10
R’ S’
QQ’
K J
CP
1 1
Qn’Qn? Analysis
CP=1
J=1,K=1
Qn+1=Q’;
Qn+1’ =Q;
J-K clocked FLIP-FLOPS
Analysis
CP=1
J=0,K=0 Qn+1=Q; Qn+1’ =Q’;
J=1,K=0 Qn+1=1; Qn+1’=0;
J=0,K=1 Qn+1=0; Qn+1’=1;
J=1,K=1 Qn+1=Q’; Qn+1’=Q;
CP=0
Qn+1=Q;
Qn+1’=Q’; K
J
Q’
QC
R’ S’
QQ’
K J
CP
J-K clocked FLIP-FLOPS
Excitation table
Characteristics
equation
Qn+1=JQ’+K’Q
JK=00,remain same
JK=01/10,Qn+1=J
JK=11,toggle
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
0
J K Qn Qn+1
0
0
1
1
0
0
1
1
00 01 11 10
0
1
0
1
2
3
6
7
4
5
JKQ
1
1
1
1
T clocked FLIP-FLOPS
Analysis
CP=1
T=1 Qn+1=Q’;
Qn+1=Q;
T=0 Qn+1=Q;
Qn+1’=Q’;
CP=0
Qn+1=Q;
Qn+1’=Q’;
R’ S’
QQ’
T
CP
T
Q’
Q
C
T clocked FLIP-FLOPS
Excitation table
Characteristics
equation
Qn+1=TQ’+T’Q
T=0,remain same
T=1,toggle
0
0
1
1
0
1
0
1
0
1
1
0
T Qn Qn+1
Master-slave
FLIP-FLOPS
Consider the following timing diagram
CLK
D
Q Hazard 1
J-k Clocked
Flip-Flops
CP=1
J=0,K=0
Qn+1=Q; Qn+1’ =Q’;
J=1,K=0
Qn+1=1; Qn+1’=0;
J=0,K=1
Qn+1=0; Qn+1’=1;
J=1,K=1
Qn+1=Q’; Qn+1’=Q;
R’ S’
QQ’
K J
CP
Consider the following timing diagram
CLK
J
K
Q
Master-slave FLIP-FLOPS
M-s flip-flops are constructed by
connecting two flip-flips in a cascade.
To protect a flip-flop’s output from
inadvertent changes caused by glitches
on the input.
Master-slave flip-flops are used in
applications where glitches may be
prevalent on input.
S
R
R-S flip-flop
S
R
Basic core is a RS latch
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
Q
G1
G2
&
&
G3
G4
G9
MQ’ Q’
MQ
When CP goes
from 1 to 0，
master be locked,
slave toggled
according to the
master-state,
Toggle be achieved by two steps
When CP＝ 1,slave be
locked,master accept
the excitations,set
the corresponded
master-state while
slave-states remain
same,
The basic core is a RS latch.
Toggle be achieved by two steps
When CP＝ 1,slave be locked,master
accept the excitations,set the
corresponded master-state while slave-
states remain same,
When CP goes from 1 to 0,master be
locked,slave toggled according to the
master-state,
RS flip-flop
RS=00,remain same;
RS=01/10,Qn+1=S;
RS=11,indeterminate
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
Q
G1
G2
&
&
G3
G4
G9
MQ’ Q’
MQ
RS latch
RS=11,remain same;
RS=01/10,Qn+1=R;
RS=00,indeterminate;
S
S
R
R
MQ ≠ MQ’;
RS=01/10,Qn+1=S=MQ;
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
Q
G1
G2
&
&
G3
G4
G9
MQ’ Q’
MQ
S
S
R
R
CP=1->0
master be locked
Slave toggled
Qn+1=MQ
CP=0
master be locked
Slave R-S flip-flop
Qn+1=MQ
master slave
&
&
K
J
G5
G6
&
&
G7
G8
CP
&
&
Q
G1
G2
&
&
G3
G4
G9
Q’
MQ’
MQ
CP
X X
X’
R
S
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
Q’
01
0
0
1
1
MQ’
MQ
CP=0,Q=MQ;
Q=MQ=x
x
x’
x
x’
S
R
J=0,K=0,CP=1
G7(CP,J,Qn’)=1,G8(CP,K,Qn) =1,MQn+1=MQ=x ;
J=0,K=0,CP=1->0,
MQ=x,Qn+1=MQ=x=Qn;
R
S
R
S &
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
MQ’ Q’
MQ
CP=0,Q=MQ;
J=0,K=0,CP=1,G7(CP,J,Qn’),G8(CP,K,Qn)
Qn’=1,Qn=0,G7(1,0,1)=1,G8(1,0,0)=1,MQn+1=MQn ;
Qn’=0,Qn=1,G7(1,0,0)=1,G8(1,0,1)=1,MQn+1=MQn ;
J=0,K=0,CP=1->0
Qn+1=MQn+1=MQn=Qn;
0
0
J=0,K=0,CP=1->0
Qn+1=Qn
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
MQ’ Q’
MQ
R
R
S S0
0
R
S
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
Q’
01
0
1
1
0
CP=0,Q=MQ;
Q=MQ=1
1
0
1
0
S
R
J=0,K=1,CP=1->0,
Qn+1=MQn+1=0;
J=0,K=1,CP=1
G7(CP,J,Qn’)=1,G8(CP,K,Qn) =0,MQn+1=0 ;
MQ
MQ’
0
1
0
1
R
S
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
Q’
01
0
1
1
1
CP=0,Q=MQ;
Q=MQ=0
0
1
0
1
S
R
J=0,K=1,CP=1->0,
Qn+1=MQn+1=0;
J=0,K=1,CP=1
G7(CP,J,Qn’)=1,G8(CP,K,Qn) =1,MQn+1=0 ;
MQ
MQ’
J=0,K=1,CP=1->0
Qn+1=MQn+1=0;
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
MQ’ Q’
MQ
R
R
S S0
1
CP=0,Q=MQ;
J= 1,K=0,CP=1,G7(CP,J,Qn’),G8(CP,K,Qn)
Qn’=1,Qn=0,G7(1,1,1)=0,G8(1,0,0)=1,MQn+1=1 ;
Qn’=0,Qn=1,G7(1,1,0)=1,G8(1,0,1)=1,MQn+1=MQn=Qn=1;
J=1,K=0,CP=1->0
Qn+1=MQn+1=1;
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
MQ’ Q’
MQ
R
R
S S1
0
J=1,K=0,CP=1->0
Qn+1=1
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
MQ’ Q’
MQ
R
R
S S
R
S
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
Q’
01
1
1
1
0
CP=0,Q=MQ;
Q=MQ=1
1
0
1
0
S
R
J=0,K=1,CP=1->0,
Qn+1=MQn+1=0;
J=1,K=1,CP=1
G7(CP,J,Qn’)=1,G8(CP,K,Qn) =0,MQn+1=0 ;
MQ
MQ’
0
1
0
1
R
S
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
Q’
01
1
1
0
1
CP=0,Q=MQ;
Q=MQ=0
0
1
0
1
S
R
J=0,K=1,CP=1->0,
Qn+1=MQn+1=1;
J=1,K=1,CP=1
G7(CP,J,Qn’)=0,G8(CP,K,Qn) =1,MQn+1=1 ;
MQ
MQ’
1
0
1
0
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
MQ’ Q’
MQ
J= 1,K=1,CP=1,G7(CP,J,Qn’),G8(CP,K,Qn)
Qn’=1,Qn=0,G7(1,1,1)=0,G8(1,1,0)=1,MQn+1=1 ;
Qn’=0,Qn=1,G7(1,1,0)=1,G8(1,1,1)=0,MQn+1=0;
J=1,K=1,CP=1->0
Qn+1=MQn+1=1 (Qn=0); Qn+1=MQn+1=0(Qn=1);
R
R
S S1
1
J=1,K=1,CP=1->0
Qn+1= Qn’
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
MQ’ Q’
MQ
R
R
S S
1
1
J=1,K=1,Qn+1= Qn’
J=0,K=1,Qn+1= 0
&
&
K
J G5
G6
&
&
G7
G8
CP master slave
&
&
QG1
G2
&
&
G3
G4
G9
MQ’ Q’
MQ
R
R
S S
J=0,K=0,Qn+1= Qn
J=1,K=0,Qn+1= 1
Master-slave FLIP-FLOPS
J
K
Q
CP
Q’
Edge triggered
FLIP-FLOPS
Consider the following timing diagram
CLK
J
K
Q
To solute the oscillation of the output
Edge triggered flip-flops initiate Q
output changes on the rising or falling
edge of the clock input.
Many problems attributed to improper
triggering of latches or gated latch
are eliminated.
Positive edge triggered flip-flop
Negative edge triggered flip-flop
CLK &
&
CLK-Edge
DEL-CLK
DEL-CLK=(CLK)’
CLK-Edge=CLK · DEL-CLK =CLK · (CLK)’ =0
CLK
DEL-CLK
CLK-Edge
Propagation delay
delay(DEL-CLK)=t
delay(CLK-Edge)=2t
Momentary 1 glitch
Glitch pulse width is t
Edge triggered FLIP-FLOPS
JK flip-flop
JK=00,Qn+1=Qn;
JK=01/10,Qn+1=J;
JK=11,Qn+1=Qn’,toggle
J
CP
&
&
QG1
G2
&
&
G3
G4
Q’
&& G7 G6
K
Positive edge triggered
JK flip-flops
Edge triggered FLIP-FLOPS
J
CP
&
&
QG1
G2
&
&
G3
G4
Q’
&& G7 G6
K
Positive edge triggered
JK flip-flops
K
J
Q’
QC
Edge triggered FLIP-FLOPS
JK flip-flop
JK=00,Qn+1=Qn;
JK=01/10,Qn+1=J;
JK=11,Qn+1=Qn’,toggle
negative edge triggered
JK flip-flops
J
CP
&
&
QG1
G2
&
&
G3
G4
Q’
&&
G6
G5
K
& G7
Edge triggered FLIP-FLOPS
negative edge triggered
JK flip-flops
J
CP
&
&
QG1
G2
&
&
G3
G4
Q’
&&
G6
G5
K
& G7
K
J
Q’
QC
Positive Edge Triggered Flip-flops
J
K
Q
CP
Q’
Negative edge triggered flip-flops
J
K
Q
CP
Q’
Flip-flop timing specifications
Pulse width
Setup time
The time that the excitation inputs to a
flip-flop device must remain stable prior to
the arrival of the clock edge that triggers
the device.
Hold time
The time that the excitation inputs must
remain stable after the clock edge has
occurred.
