ASICs...THE COURSE (1 WEEK) 1 FLOORPLANNING AND PLACEMENT Key terms and concepts: The input to floorplanning is the output of system partitioning and design entry—a netlist. The output of the placement step is a set of directions for the routing tools. The starting point for floorplanning and placement for the Viterbi decoder (standard cells). 16 2 SECTION 16 FLOORPLANNING AND PLACEMENT ASICS... THE COURSE The Viterbi decoder after floorplanning and placement. ASICs... THE COURSE 16.1 Floorplanning 3 16.1 Floorplanning Key terms and concepts: Interconnect and gate delay both decrease with feature size—but at different rates ? Interconnect capacitance bottoms out at 2pFcm–1 for a minimum-width wire, but gate delay continues to decrease ? Floorplanning predicts interconnect delay by estimating inter- connect length 16.1.1 Floorplanning Goals and Objectives Key terms and concepts: Floorplanning is a mapping between the logical description (the netlist) and the physical description (the floorplan). Goals of floorplanning: ? arrange the blocks on a chip, ? decide the location of the I/O pads, ? decide the location and number of the power pads, ? decide the type of power distribution, and ? decide the location and type of clock distribution. Objectives of floorplanning are: ? to minimize the chip area, and ? minimize delay. 16.1.2 Measurement of Delay in Floorplanning Key terms and concepts: To predict performance before we complete routing we need to answer “How long does it takes to get from Russia to China?” ? In floorplanning we may even move Russia and China ? We don’t yet know the parasitics of the interconnect capacitance ? We Interconnect and gate delays. As feature sizes decrease, both average interconnect delay and average gate delay decrease— but at different rates. This is because interconnect ca- pacitance tends to a limit that is independent of scaling. Interconnect delay now domi- nates gate delay. 0.1 1.0 interconnectdelay gate delay delay /ns 1.0 0.5 0.25 minimum featuresize/ μm 4 SECTION 16 FLOORPLANNING AND PLACEMENT ASICS... THE COURSE know only the fanout (FO) of a net and the size of the block ? We estimate interconnect length from predicted-capacitance tables (wire-load tables) Predicted capacitance. (a) Interconnect lengths as a function of fanout (FO) and circuit-block size. (b) Wire-load table. There is only one capacitance value for each fanout (typically the average value). (c) The wire-load table predicts the capacitance and delay of a net (with a considerable er- ror). Net A and net B both have a fanout of 1, both have the same predicted net delay, but net B in fact has a much greater delay than net A in the actual layout (of course we shall not know what the actual layout is until much later in the design process). 100 100 100 100 100 % of nets FO=1 FO=2 FO=3 FO=4 FO=5 0 0.25 0.5 0.75 1.0 0 0.01 0.02 0.03 0.04 0 1 2 3 4 delay/ ns capacitance/pF standard loads fanout block size(k-gate) 1 0.9 1.2 1.9 32 2.4 4 3.0 5 201030 40 FO=1 FO=4 logic cells average netcapacitance row-based ASIC flexible block(20k-gate) 0.9 standardloads=0.009 pF (a) (b) (c) 0.03 pF net A net B net C 0.03pF 1 standard load=0.01pF predicted capacitance(standard loads) as afunction of fanout (FO) and block size (k-gate) fanout (FO) net B net C net A ASICs... THE COURSE 16.1 Floorplanning 5 16.1.3 Floorplanning Tools Key terms and concepts: we start with a random floorplan generated by a floorplanning tool ? flexible blocks and fixed blocks ? seeding ? seed cells ? wildcard symbol ? hard seed ? soft seed ? seed connectors ? rat's nest ? bundles ? flight lines ? congestion ? aspect ratio ? die A wire-load table showing average interconnect lengths (mm). Fanout Array (available gates) Chip size (mm) 1 2 4 3k 3.45 0.56 0.85 1.46 11k 5.11 0.84 1.34 2.25 105k 12.50 1.75 2.70 4.92 Worst-case interconnect delay. As we scale circuits, but avoid scaling the chip size, the worst- case interconnect de- lay increases. 1.0 0.5 0.25 interconnectdelay/ ns ± 1 sigmaspread featuresize/ μm 0.1 ns fromwire-loadtable 0.1 100% interconnectdelay /ns1.0 ns 1.0 average isdecreasing worst case isincreasing 6 SECTION 16 FLOORPLANNING AND PLACEMENT ASICS... THE COURSE cavity ? congestion map ? routability ? interconnect channels ? channel capacity ? channel density Congestion analysis. (a) The initial floorplan with a 2:1.5 die aspect ratio. (b) Altering the floorplan to give a 1:1 chip aspect ratio. (c) A trial floorplan with a congestion map. Blocks A and C have been placed so that we know the terminal positions in the channels. Shading indicates the ratio of channel density to the channel capacity. Dark areas show regions that cannot be routed because the channel congestion exceeds the estimated capacity. (d) Resizing flexible blocks A and C alleviates congestion. A 2 1.5A B C E FD B C E FD D B 1.75 1.75 B F D F (a) (b) (c) (d) 1.75 A E A EC C100%200% 50% Routing congestion 1.75 ASICs... THE COURSE 16.1 Floorplanning 7 Floorplanning a cell-based ASIC. (a) Initial floorplan generated by the floorplanning tool. Two of the blocks are flexible (A and C) and contain rows of standard cells (unplaced). A pop-up window shows the status of block A. (b) An estimated placement for flexible blocks A and C. The connector positions are known and a rat’s nest display shows the heavy congestion be- low block B. (c) Moving blocks to improve the floorplan. (d) The updated display shows the reduced congestion after the changes. (d)F E D A B C(b) D E F A B C E.in D E F A B C (c) D E F A B C (a) flexible standard-cell blocks(not yet placed) terminal, pin, orport location flightlinebundle line mirror aboutx-axis move down swap B.in B.in E.in D.out D.out fixed blocks center ofgravity coreboundary nets inbundleBlock statusBlock name: AType: flexibleContents: 200 cellsSeed file: A.seed flexible standard-cell blocks(with estimated placement) 3221441 17 8 SECTION 16 FLOORPLANNING AND PLACEMENT ASICS... THE COURSE Routing a T-junction between two channels in two-level metal. The dots represent logic cell pins. (a) Routing channel A (the stem of the T) first allows us to adjust the width of channel B. (b) If we route channel B first (the top of the T), this fixes the width of channel A. We have to route the stem of a T-junction before we route the top. block 1 block 2 block 3 block 1 block 2 block 3channel B channel B (a) (b) T-pin 1 12 Adjustchannel Afirst. Now we canadjust channel B. Adjust channel Bfirst. Now wecannotadjustchannel A.2 m1 m2 blockpin ASICs... THE COURSE 16.1 Floorplanning 9 16.1.4 Channel Definition Key terms and concepts: channel definition or channel allocation ? channel ordering ? slicing floorplan ? cyclic constraint ? switch box ? merge ? selective flattening ? routing order Defining the channel routing order for a slicing floorplan using a slicing tree. (a) Make a cut all the way across the chip between circuit blocks. Continue slicing until each piece contains just one circuit block. Each cut divides a piece into two without cutting through a circuit block. (b) A sequence of cuts: 1, 2, 3, and 4 that successively slices the chip until only circuit blocks are left. (c) The slicing tree corresponding to the sequence of cuts gives the order in which to route the channels: 4, 3, 2, and finally 1. 1 2 3 AB CD1AB D D C A B 1 2 3 (a) (b) (c)E 4 E4 slice CE cutline circuitblock routingchannel cutnumber routechannelsin thisorder 10 SECTION 16 FLOORPLANNING AND PLACEMENT ASICS... THE COURSE Cyclic constraints. (a) A nonslicing floorplan with a cyclic constraint that prevents channel routing. (b) In this case it is difficult to find a slicing floorplan without increasing the chip area. (c) This floorplan may be sliced (with initial cuts 1 or 2) and has no cyclic constraints, but it is inefficient in area use and will be very difficult to route. Channel definition and ordering. (a) We can eliminate the cyclic constraint by merging the blocks A and C. (b) A slicing structure. 1 2 3 4A BC D E E C BDA E DA CB 1 2 (a) (b) (c) DD B F 123 57 8 9 F Bcyclic constraint:1, 2, 3, 4 1 3 4 5 78 6 E (a) (b) mergestandardcell areasA and CE A C 10 4 11 AC 2 channelnumber(in routingorder) ASICs... THE COURSE 16.1 Floorplanning 11 16.1.5 I/O and Power Planning Key terms and concepts: die ? chip carrier ? package ? bonding ? pads ? lead frame ? package pins ? core ? pad ring ? pad-limited die ? core-limited die ? pad-limited pads ? core-limited pads ? power pads ? power buses (or power rails) ? power ring ? dirty power ? clean power ? electrostatic discharge (ESD) ? chip cavity ? substrate connection ? down bond (or drop bond) ? pad seed ? double bond ? multiple-signal pad ? oscillator pad ? clock pad. ? corner pad ? edge pads ? two- pad corner cell ? bond-wire angle design rules ? simultaneously switching outputs (SSOs) ? pad mapping ? logical pad ? physical pad ? pad library. ? pad-format changer or hybrid corner pad. ? global power nets ? mixed power supplies ? multiple power supplies ? stagger-bond ? area- bump ? ball-grid array (BGA) ? pad slot (or pad site) ? I/O-cell pitch ? pad pitch ? channel spine ? preferred layer ? preferred direction Pad-limited and core-limited die. (a) A pad-limited die. The number of pads determines the die size. (b) A core-limited die: The core logic determines the die size. (c) Using both pad-limited pads and core-limited pads for a square die. (a) corner pad (b) VDD(I/O)VSS(I/O) VDD(core)VSS(core) VSS (core)power pad I/O pads (pad-limited) bonding pad I/O circuit corepadring (c) I/O power pad I/O pad(core-limited) I/O pad (pad-limited) m1jumperI/O pad(core-limited) m1jumper m2 power ring 12 SECTION 16 FLOORPLANNING AND PLACEMENT ASICS... THE COURSE Bonding pads. (a) This chip uses both pad-limited and core-limited pads. (b) A hybrid corner pad. (c) A chip with stagger-bonded pads. (d) An area-bump bonded chip (or flip-chip). The chip is turned upside down and solder bumps connect the pads to the lead frame. two-pad corner padformat changer:core-limited topad-limited pad-limited I/O pad core-limitedI/O pad core powerringVDD (core) VSS (core) core-limited VDDcore-power pad pad-cellbounding box bondingpad VSS (pad ring) I/O pad power ring VDD (pad ring)southeast corner pad-limited VSScore-power pad I/O circuit andESDprotectioncore-limitedpad pitch pad-limitedpad pitch (a) (b) bond-wireangle bond wire package pinlead frame package-pin spacing staggerbond (c) off-grid pads minimumlead-frame pitch solder bump (notshown on all pads)(d) chip die outline ofchip core lead-framewires (notall shown) ASICs... THE COURSE 16.1 Floorplanning 13 Gate-array I/O pads. (a) Cell-based ASICs may contain pad cells of different sizes and widths. (b) A corner of a gate-array base. (c) A gate-array base with different I/O cell and pad pitches. pad cell 2× 4mA outputdriver cells inparallel empty padslot I/O cellslot output cellpitch I/O-cellpitch 4mA outputpad 8mA outputpad 4mA outputdriver cell (a) (b) (c) cell-based ASICcustom I/O pad gate-arraypads arefixed I/Ocircuits bondingpad bonding pad I/O circuit(not shownfor all slots) 14 SECTION 16 FLOORPLANNING AND PLACEMENT ASICS... THE COURSE Power distribution. (a) Power distributed using m1 for VSS and m2 for VDD. This helps minimize the number of vias and layer crossings needed but causes problems in the routing channels. (b) In this floorplan m1 is run parallel to the longest side of all channels, the channel spine. This can make automatic routing easier but may increase the number of vias and layer crossings. (c) An expanded view of part of a channel (interconnect is shown as lines). If power runs on different layers along the spine of a channel, this forces signals to change layers. (d) A closeup of VDD and VSS buses as they cross. Changing layers requires a large number of via contacts to reduce resistance. D F B E layercrossingD F B E m2m1 verticalchannel All power rails run in m1 parallel to spine. horizontalchannel standard-cell area (a) (b) m2 m1 (c) (d) VDD(m2) signals need tochange layers signal(m2) VSS(m1) VDD(m1) VSS(m1) m1 m2 m1/m2 via A A ASICs... THE COURSE 16.1 Floorplanning 15 16.1.6 Clock Planning Key terms and concepts: clock spine ? clock skew ? clock latency ? taper ? hot-electron wearout ? phase-locked loop (PLL) is an electronic flywheel ? jitter Clock distribution. (a) A clock spine for a gate array. (b) A clock spine for a cell-based ASIC (typical chips have thousands of clock nets). (c) A clock spine is usually driven from one or more clock-driver cells. Delay in the driver cell is a function of the number of stages and the ratio of output to input capacitance for each stage (taper). (d) Clock latency and clock skew. We would like to minimize both latency and skew. (a) (b) (c) (d) clock-drivercell A1 B1 B2D1 D2 D3 E1 E2 F1 CLK m2 m1 base cellsclockspine clock spine CLK clock-drivercellm2 m1 1 2 F.1 A.1 A.2main branchside branchesskew F.2 blockconnector CL CLK A1, B1, B2D1, D2, E1 D3, E2, F1 clock-driver cellbuffer chain clockspine1 2 nC1 CnC2taper latency skew CLKD2 F1 16 SECTION 16 FLOORPLANNING AND PLACEMENT ASICS... THE COURSE A clock tree. (a) Minimum delay is achieved when the taper of successive stages is about 3. (b) Using a fanout of three at successive nodes. (c) A clock tree for a cell-based ASIC We have to balance the clock arrival times at all of the leaf nodes to minimize clock skew. CLK B1, B2D1, D2, E1 D3, E2I/O pad A1 F1 F.2F.1 clock-buffer cell clock tree inside block F (a) (c) C1 C2C1 (b) 1 234 5 6 89 10 1 234 insideflip-flop A.2 A.1 clock spineinside block A 7 taper taper CL flip-flop D CLK' CLKA.2 Q 7 ASICs... THE COURSE 16.2 Placement 17 16.2 Placement Key terms and concepts: Placement is more suited to automation than floorplanning. Thus we need measurement techniques and algorithms. 16.2.1 Placement Terms and Definitions Key terms and concepts: row-based ASICs ? over-the-cell routing (OTC routing) ? channel capacity ? feedthroughs ? vertical track (or just track) ? uncommitted feedthrough (also built-in feedthrough, implicit feedthrough, or jumper) ? double-entry cells ? electrically equivalent connectors (or equipotential connectors) ? feedthrough cell (or crosser cell) ? feedthrough pin or feedthrough terminal ? spacer cell ? alternative connectors ? must-join connectors ? logically equivalent connectors ? logically equivalent connector groups ? fixed-resource ASICs Interconnect structure. (a) A two-level metal CBIC floorplan. (b) A channel from the flexible block A. This channel has a channel height equal to the maximum channel density of 7 (there is room for seven interconnects to run horizontally in m1). (c) A channel that uses OTC (over-the-cell) routing in m2. feedthrough cell(vertical capacity=1)feedthrough usinglogic cell channelheight=15 channeldensity=7 (a) (b) (c)over-the-cell routing in m2 m2 m1 A 18 SECTION 16 FLOORPLANNING AND PLACEMENT ASICS... THE COURSE Gate-array interconnect. (a) A small two-level metal gate array (about 4.6k-gate). (b) Routing in a block. (c) Channel routing showing channel density and channel capacity. The channel height on a gate array may only be increased in increments of a row. If the in- terconnect does not use up all of the channel, the rest of the space is wasted. The intercon- nect in the channel runs in m1 in the horizontal direction with m2 in the vertical direction. (a) 16 8 (b) 2-row-high channel(horizontal capacity=14) single row channel(horizontal capacity =7) row column unused space logic cells (macros) feedthrough (vertical capacity= 3) channelrouting base cells fixed channel height logic cell channel A (density=10) channel B (density=5) channel C (density=7) (c) m2 m1 gate-array base= 36 blocks by 128 sites= 4608 sites 1 block = 128 sites site or base cell 3 columns ASICs... THE COURSE 16.2 Placement 19 16.2.2 Placement Goals and Objectives Key terms and concepts: Goals: (1) Guarantee the router can complete the routing step ? (2) Minimize all the critical net delays ? (3) Make the chip as dense as possible ? Objectives: (1) Minimize power dissipation ? (2) Minimize crosstalk between signals 16.2.3 Measurement of Placement Goals and Objectives Key terms and concepts: trees on graphs (or just trees) ? Steiner trees ? rectilinear routing ? Manhattan routing ? Euclidean distance ? Manhattan distance ? minimum rectilinear Steiner tree (MRST) ? complete graph ? complete-graph measure ? bounding box ? half-perimeter measure (or bounding-box measure) ? meander factor ? interconnect congestion ? maximum cut line ? cut size ? timing-driven placement ? metal usage 20 SECTION 16 FLOORPLANNING AND PLACEMENT ASICS... THE COURSE Placement using trees on graphs. (a) A floorplan. (b) An expanded view of the flexible block A showing four rows of standard cells for place- ment (typical blocks may contain thousands or tens of thousands of logic cells). We want to find the length of the net shown with four terminals, W through Z, given the placement of four logic cells (labeled: A.211, A.19, A.43, A.25). (c) The problem for net (W, X, Y, Z) drawn as a graph. The shortest connection is the minimum Steiner tree. (d) The minimum rectilinear Steiner tree using Manhattan routing. The rectangular (Manhattan) interconnect-length measures are shown for each tree. 1 2 3 4 5 6 7 (d) 6 8 Steinerpoint L=151214 1042 minimumrectilinearSteiner tree (a) expanded view of part of flexible block AA rows ofstandardcells Z W XY A.19 cell instance name terminal name terminal A.211 A.43 A.25 (b) (c) L=16 X Z W X Z Y 50 λ 50 λ 250λ 50 λ 134 765 2W Y channels ASICs... THE COURSE 16.2 Placement 21 Interconnect-length measures. (a) Complete-graph measure. (b) Half-perimeter measure. Interconnect congestion for a cell-based ASIC. (a) Measurement of congestion. (b) An expanded view of flexible block A shows a maximum cut line. (b) L=28/ 2= 14 204 6 2 2628 2224 108 1412 1816 (a) L=44/2=22 204 6 2 2628 2224 108 1412 1816 complete-graph measure half-perimeter measure 42 4044 39 343630 (a) 37357 753 expanded view of part of flexible block A rows of standardcells (b) cutsize= 5 channelheight =channel capacity A D B terminals terminal maximumcut line feedthroughcells built-infeedthrough channels channel 4 row 1 row 3row 2row 4 22 SECTION 16 FLOORPLANNING AND PLACEMENT ASICS... THE COURSE 16.2.4 Placement Algorithms Key terms and concepts: constructive placement method ? variations on the min-cut algorithm ? eigenvalue method ? seed placements ? min-cut placement ? bins ? eigenvalue placement algorithm ? connectivity matrix (spectral methods) ? quadratic placement ? disconnection matrix (also called the Laplacian) ? characteristic equation ? eigenvectors and eigenvalues ASICs... THE COURSE 16.2 Placement 23 16.2.5 Eigenvalue Placement Example Eigenvalue placement. (a) An example network. (b) The one-dimensional placement. The small black squares represent the centers of the logic cells. (c) The two-dimensional placement. The eigenvalue method takes no account of the logic cell sizes or actual location of logic cell connectors. (d) A complete layout. We snap the logic cells to valid locations, leaving room for the routing in the channel. 1 2 3 (a) (b)4 -0.6-0.4 -0.20 0.20.4 0.6 1 2 3 4-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 (c) -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.83 2 4 1 AB C AB C B A C (d) cellabutmentbox logiccell cell 3 cell 1 cell 2 cell 4 cell abutment box connector m2m1channelB C A 24 SECTION 16 FLOORPLANNING AND PLACEMENT ASICS... THE COURSE 16.2.6 Iterative Placement Improvement Key terms and concepts: iterative placement improvement ? interchange or iterative exchange ? pairwise-interchange algorithm ? λ-optimum ? neighborhood exchange algorithm ? neighborhood ? ε-neighborhood ? force-directed placement methods ? Hooke’s law ? force-directed interchange ? force-directed relaxation ? force-directed pairwise relaxation Interchange. (a) Swapping the source logic cell with a destination logic cell in pairwise interchange. (b) Sometimes we have to swap more than two logic cells at a time to reach an optimum placement, but this is expensive in computation time. Limiting the search to neighborhoods reduces the search time. Logic cells within a distance ε of a logic cell form an ε-neighborhood. (c) A one-neighborhood. (d) A two-neighborhood. trial destination module 1 42 35 86 7 9 1210 1113 1614 15 (a) (b) 1 42 35 86 7 9 1210 1113 1614 15 6 (c) 1 42 35 87 9 1210 1113 1614 15 6 (d) 1 42 35 87 9 1210 1113 1614 15 2-neighborhood ofmodule 11-neighborhood ofmodule 1λ =3 swap λ=2 swap sourcemodule ASICs... THE COURSE 16.2 Placement 25 Force-directed placement. (a) A network with nine logic cells. (b) We make a grid (one logic cell per bin). (c) Forces are calculated as if springs were attached to the centers of each logic cell for each connection. The two nets connecting logic cells A and I correspond to two springs. (d) The forces are proportional to the spring extensions. Force-directed iterative placement improvement. (a) Force-directed interchange. (b) Force-directed relaxation. (c) Force-directed pairwise relaxation. A H I A B CD E F G H I (–1 , 0) (–2, 2) (–2, 2)(–5, 4) I(a) (b) (c) (d) springA BD E CF G H I (a) P forcevector Trial swap P with nearestneighbors in direction of forcevector. (b) Move P tolocationthat minimizesforcevector. Repeat process,forming a chain. (c) Move P tolocationthat minimizesforcevector Swap is accepted ifdestination module movesto ε-neighborhood of P. A DB CE HF G I LJ KM PN O A DB CE HF G I LJ KM PN O A DB CE HF G I LJ KM PN O 26 SECTION 16 FLOORPLANNING AND PLACEMENT ASICS... THE COURSE 16.2.7 Placement Using Simulated Annealing Key terms and concepts: 1. Select logic cells for a trial interchange, usually at random. 2. Evaluate the objective function E for the new placement. 3. If ?E is negative or zero, then exchange the logic cells. If ?E is positive, then exchange the logic cells with a probability of exp(–?E/T). 4. Go back to step 1 for a fixed number of times, and then lower the temperature T according to a cooling schedule: Tn+1=0.9Tn, for example. 16.2.8 Timing-Driven Placement Methods Key terms and concepts: zero-slack algorithm primary inputs ? arrival times ? actual times ? required times ? primary outputs ? slack time ASICs... THE COURSE 16.2 Placement 27 The zero-slack algorithm. (a) The circuit with no net delays. (b) The zero-slack algorithm adds net delays (at the outputs of each gate, equivalent to increasing the gate delay) to reduce the slack times to zero. A X B Y C Z 1 1 1 2 3 4 0/1/1 1/2/1 3/4/1 4/6/2 7/10/31 2 2 12 10/1/1 0/3/3 1/2/1 1/4/3 3/6/3 5/8/3 7/10/3 9/10/12/4/2 5/6/1 gate delayarrival/required/slack primaryoutputprimaryinput A X B Y C Z 1+0.5 1+ 0.5 1+1.5 2+0.5 3+1 4+0 0/0/0 1.5/1.5/0 4/4/0 6/6/2 10/10/01+1 2+0 2+0 1+02+1.5 1+1.50/0/0 0/0/0 1.5/1.5/0 2.5/2.5/0 6/6/0 8/8/0 10/10/0 10/10/04/4/0 6/6/0 gate delay + net delayarrival/required/slack primaryoutputprimaryinput (a) (b) critical path 28 SECTION 16 FLOORPLANNING AND PLACEMENT ASICS... THE COURSE 16.2.9 A Simple Placement Example 16.3 Physical Design Flow Key terms and concepts: Because interconnect delay now dominates gate delay, the trend is to include placement within a floorplanning tool and use a separate router. 1. Design entry. The input is a logical description with no physical information. Placement example. (a) An example network. (b) In this placement, the bin size is equal to the logic cell size and all the logic cells are assumed equal size. (c) An alternative placement with a lower total routing length. (d) A layout that might result from the placement shown in b. The channel densities correspond to the cut-line sizes. Notice that the logic cells are not all the same size (which means there are errors in the interconnect-length estimates we made during place- ment). (a) (b) (c) A B C D E F G H I A B EC D F H I G maximumcut line (y) =4 capacity ofeach binedge=2 C D EA G F B H I cut line=2cut line=1wirelength= 1 routing length =7maximum cut (x and y) =2 total routing length=8 cell abutmentbox cellconnector m2m1 cell A cell B cell E cell C cell D cell F cell H cell I cell G (d) channeldensity=2 channeldensity=1 ASICs... THE COURSE 16.3 Physical Design Flow 29 2. Initial synthesis. The initial synthesis contains little or no information on any interconnect loading.The output of the synthesis tool (typically an EDIF netlist) is the input to the floorplan- ner. 3. Initial floorplan. From the initial floorplan interblock capacitances are input to the synthesis tool as load constraints and intrablock capacitances are input as wire-load tables. 4. Synthesis with load constraints. At this point the synthesis tool is able to resynthesize the logic based on estimates of the interconnect capacitance each gate is driving. The synthesis tool produces a forward annotation file to constrain path delays in the placement step. 5. Timing-driven placement. After placement using constraints from the synthesis tool, the location of every logic cell on the chip is fixed and accurate estimates of interconnect delay can be passed back to the synthesis tool. 6. Synthesis with in-place optimization (IPO).The synthesis tool changes the drive strength of gates based on the accurate interconnect delay estimates from the floorplanner without altering the netlist structure. 7. Detailed placement. The placement information is ready to be input to the routing step. Timing-driven floorplanning and placement design flow. design entry detailed placement VHDL/Verilognetlist A chip wire loadssynthesis with load constraints A B A BC1 C2 C2 C 3 x8A.inv1A.nand1 A A B A B synthesiswith in-placeoptimization C3 C4 increasingaccuracy ofwire-loadestimatesA initial synthesis initial floorplan interconnectload timing-driven placement block7 1 6 45 32 error0 C2 C3 C1 C4 30 SECTION 16 FLOORPLANNING AND PLACEMENT ASICS... THE COURSE 16.4 Information Formats 16.4.1 SDF for Floorplanning and Placement Key terms and concepts: standard delay format (SDF)? back-annotation ? forward-annotation ? timing constraints (INSTANCE B) (DELAY (ABSOLUTE (INTERCONNECT A.INV8.OUT B.DFF1.Q (:0.6:) (:0.6:)))) (TIMESCALE 100ps) (INSTANCE B) (DELAY (ABSOLUTE (NETDELAY net1 (0.6))) (TIMESCALE 100ps) (INSTANCE B.DFF1) (DELAY (ABSOLUTE (PORT CLR (16:18:22) (17:20:25)))) (TIMESCALE 100ps) (INSTANCE B) (TIMINGCHECK (PATHCONSTRAINT A.AOI22_1.O B.ND02_34.O (0.8) (0.8))) (TIMESCALE 100ps) (INSTANCE B) (TIMINGCHECK (SUM (AOI22_1.O ND02_34.I1) (ND02_34.O ND02_35.I1) (0.8))) (TIMESCALE 100ps) (INSTANCE B) (TIMINGCHECK (DIFF (A.I_1.O B.ND02_1.I1) (A.I_1.O.O B.ND02_2.I1) (0.1))) (TIMESCALE 100ps) (INSTANCE B) (TIMINGCHECK (SKEWCONSTRAINT (posedge clk) (0.1))) 16.4.2 PDEF Key terms and concepts: physical design exchange format (PDEF) (CLUSTERFILE (PDEFVERSION "1.0") (DESIGN "myDesign") (DATE "THU AUG 6 12:00 1995") ASICs... THE COURSE 16.5 Summary 31 (VENDOR "ASICS_R_US") (PROGRAM "PDEF_GEN") (VERSION "V2.2") (DIVIDER .) (CLUSTER (NAME "ROOT") (WIRE_LOAD "10mm x 10mm") (UTILIZATION 50.0) (MAX_UTILIZATION 60.0) (X_BOUNDS 100 1000) (Y_BOUNDS 100 1000) (CLUSTER (NAME "LEAF_1") (WIRE_LOAD "50k gates") (UTILIZATION 50.0) (MAX_UTILIZATION 60.0) (X_BOUNDS 100 500) (Y_BOUNDS 100 200) (CELL (NAME L1.RAM01) (CELL (NAME L1.ALU01) ) ) ) 16.4.3 LEF and DEF Key terms and concepts: library exchange format (LEF) ? design exchange format (DEF) 16.5 Summary Key terms and concepts: Interconnect delay now dominates gate delay ? Floorplanning is a mapping between logical and physical design ? Floorplanning is the center of design operations for all types of ASIC ? Timing-driven floorplanning is an essential ASIC design tool ? Placement is an automated function 32 SECTION 16 FLOORPLANNING AND PLACEMENT ASICS... THE COURSE