ASICs...THE COURSE (1 WEEK) 1 ROUTING Key terms and concepts: Routing is usually split into global routing followed by detailed routing. Suppose the ASIC is North America and some travelers in California need to drive from Stanford (near San Francisco) to Caltech (near Los Angeles). The floorplanner decides that California is on the left (west) side of the ASIC and the placement tool has put Stanford in Northern California and Caltech in Southern California. Floorplanning and placement define the roads and freeways. There are two ways to go: the coastal route (Highway 101) or the inland route (Interstate I5–usually faster). The global router specifies the coastal route because the travelers are not in a hurry and I5 is congested (the global router knows this because it has already routed onto I5 many other travelers that are in a hurry today). Next, the detailed router looks at a map and gives indications from Stanford onto Highway 101 south through San Jose, Monterey, and Santa Barbara to Los Angeles and then off the freeway to Caltech in Pasadena. 17.1 Global Routing Key terms and concepts: Global routing differs slightly between CBICs, gate arrays, and FPGAs, but the principles are the same ? A global router does not make any connections, it just plans them ? We typically global route the whole chip (or large pieces) before detail routing ? There are two types of areas to global route: inside the flexible blocks and between blocks 17.1.1 Goals and Objectives Key terms and concepts: Goal: provide complete instructions to the detailed router ? Objectives: Minimize the total interconnect length ? Maximize the probability that the detailed router can complete the routing ? Minimize the critical path delay 17 2 SECTION 17 ROUTING ASICS... THE COURSE The core of the Viterbi decoder chip after placement. You can see the rows of standard cells; the widest cells are the D flip-flops. ASICs... THE COURSE 17.1 Global Routing 3 The core of the Viterbi decoder chip after the completion of global and detailed routing. This chip uses two-level metal. Although you cannot see the difference, m1 runs in the horizontal direction and m2 in the vertical direction. 4 SECTION 17 ROUTING ASICS... THE COURSE 17.1.2 Measurement of Interconnect Delay Key terms and concepts: lumped-delay model ? lumped capacitance ? as interconnect delay becomes more important other, more complex models, are used 17.1.3 Global Routing Methods Key terms and concepts: sequential routing ? order-independent routing ? order dependent routing ? hierarchical routing (top-down or bottom-up) 17.1.4 Global Routing Between Blocks Key terms and concepts: use of the channel-intersection graph Measuring the delay of a net. (a) A simple circuit with an inverter A driving a net with a fanout of two. Voltages V1, V2, V3, and V4 are the voltages at intermediate points along the net. (b) The layout showing the net segments (pieces of interconnect). (c) The RC model with each segment replaced by a capacitance and resistance. The ideal switch and pull-down resistance Rpd model the inverter A. i1 V2 V4(a) (c) A B C (b) A B V1 V2 V3 m2 t =0 Rpd R1 pull-downresistance ofinverter A resistance ofinterconnectsegments CV41mm 2mm 0.1mm 0.1mm 4X 1X 1X V0 Vd Vd Vd V3 V1 R2 V1 V2 V3R3C2 C3C1 i3 i2 i4C4 R4 V4 ASICs... THE COURSE 17.1 Global Routing 5 17.1.5 Global Routing Inside Flexible Blocks Key terms and concepts: track ? landing pad ? pick-up point, connector, terminal, pin, or port ? area pick-up point? horizontal tracks? routing bins (or just bins, also called global routing cells or GRCs) 17.1.6 Timing-Driven Methods Key terms and concepts: use of timing engine ? path or node based 17.1.7 Back-annotation Key terms and concepts: RC information ? huge files ? database problem Global routing for a cell-based ASIC formulated as a graph problem. (a) A cell-based ASIC with numbered channels. (b) The channels form the edges of a graph. (c) The channel-intersection graph. Each channel corresponds to an edge on a graph whose weight corresponds to the channel length. (a) (b) (c) D F B 12 4 5 6 78 9 EA 1511 16 411 116 26 5 6 16111516 65 6 SECTION 17 ROUTING ASICS... THE COURSE Finding paths in global routing. (a) A cell-based ASIC showing a single net with a fanout of four (five terminals). We have to order the numbered channels to complete the interconnect path for terminals A1 through F1. (b) The terminals are projected to the center of the nearest channel, forming a graph. A minimum-length tree for the net that uses the channels and takes into account the channel capacities. (c) The minimum-length tree does not necessarily correspond to minimum delay. If we wish to minimize the delay from terminal A1 to D1, a different tree might be better. (c)(b) A1B1 E1 D1 F1 8 9 D1 F1 B1 12 4 5 6 7E1 A1 (a)terminal minimum-length tree A1B1 E1 D1 F1 minimum delayfrom A1 to D1 ASICs... THE COURSE 17.1 Global Routing 7 Gate-array global routing. (a) A small gate array. (b) An enlarged view of the routing. The top channel uses three rows of gate-array base cells; the other channels use only one. (c) A further enlarged view showing how the routing in the channels connects to the logic cells. (d) One of the logic cells, an inverter. (e) There are seven horizontal wiring tracks available in one row of gate-array base cells— the channel capacity is thus 7. (a) (b) (c) connector feedthrough base-celloutline electricallyequivalentconnectors pitch of verticaltracks (m2) pitch of horizontaltracks (m1) (d) (e) sea-of-gates array block basecells one block base cells base cell used forroutingbase cell used bymacro (logic cell) channel routing fixed channel height 12 34 56 7 one column m1 m2 m1 invertermacro 8 SECTION 17 ROUTING ASICS... THE COURSE A gate-array inverter (a) An oxide-isolated gate-array base cell, showing the diffusion and polysilicon layers. (b) The metal and contact layers for the inverter in a 2LM (two-level metal) process. (c) The router’s view of the cell in a 3LM process. (a) (b) polypdiff ndiff abutmentbox via1 stackedover contact connector VDD GND input output feedthrough m1 m2via1 contact contact VDD GNDinput m1 (c) abutmentboxoutput connector connector ASICs... THE COURSE 17.1 Global Routing 9 Global routing a gate array. (a) A single global-routing cell (GRC or routing bin) containing 2-by-4 gate-array base cells. For this choice of routing bin the maximum horizontal track capacity is 14, the maximum vertical track capacity is 12. The routing bin labeled C3 contains three logic cells, two of which have feedthroughs marked 'f'. This results in the edge capacities shown. (b) A view of the top left-hand corner of the gate array showing 28 routing bins. The global router uses the edge capacities to find a sequence of routing bins to connect the nets. southtracks=12capacity=4 1 1 AB CD 1 2 3 54 6 7 global celledgeB5-east & B6-west easttracks =14capacity=7westtracks =14capacity=7 northtracks =12capacity=4 global route for net 1:C3-north; B3-east; B4-east; B5-east 1 2 53 4 76 1 2 3 4 76 f f f f f f f f (a) (b)vertical feedthroughs vertical feedthroughs channel logic cells base cells routing binsor globalrouting cells (GRC)connectors 10 SECTION 17 ROUTING ASICS... THE COURSE 17.2 Detailed Routing Key terms and concepts: routing pitch (track pitch, track spacing, or just pitch) ? via-to-via (VTV) pitch (or spacing) ? via-to-line (VTL or line-to-via) pitch ? line-to-line (LTL) pitch. ? stitch? waffle via ? stacked via ? Manhattan routing ? preferred direction ? preferred metal layer ? phantom ? blockage map ? on-grid ? off-grid ? trunks ? branches ? doglegs ? pseudoterminals ? tracks (like railway tracks) ? horizontal track spacing ? track spacing ? column ? column spacing (or vertical track spacing) The metal routing pitch. (a) An example of λ-based metal design rules for m1 and via1 (m1/m2 via). (b) Via-to-via pitch for adjacent vias. (c) Via-to-line (or line-to-via) pitch for nonadjacent vias. (d) Line-to-line pitch with no vias. (b) via-to-via pitch 7 λ via-to-line orline-to-viapitch 6.5 λ (c) line-to-line pitch 6λ (d) m1 (a) 3 λ 3 λ 4 λvia1 ASICs... THE COURSE 17.2 Detailed Routing 11 Vias (a) A large m1 to m2 via. The black squares represent the holes (or cuts) that are etched in the insulating material between the m1 and 2 layers. (b) A m1 to m2 via (a via1). (c) A contact from m1 to diffusion or polysilicon (a contact). (d) A via1 placed over (or stacked over) a contact. (e) A m2 to m3 via (a via2). (f) A via2 stacked over a via1 stacked over a contact. Notice that the black square in parts b–c do not represent the actual location of the cuts. The black squares are offset so you can recognize stacked vias and contacts. via cut m2 m1 (a) (b) (c) m2 m2 m2 m2 m1 m1 via1 via2contact stackedcontact andvia1 stackedcontact, via1,and via2 (d) (f)(e) m3 m1 12 SECTION 17 ROUTING ASICS... THE COURSE An expanded view of part of a cell-based ASIC. (a) Both channel 4 and channel 5 use m1 in the horizontal direction and m2 in the vertical direction. If the logic cell connectors are on m2 this requires vias to be placed at every logic cell connector in channel 4. (b) Channel 4 and 5 are routed with m1 along the direction of the channel spine (the long direction of the channel). Now vias are required only for nets 1 and 2, at the intersection of the channels. (b)(a) 1 1 1 2 2 2 2 1 1 1 2 2 2 2 m2 m1 m2 m1 viavias E F channel 5 channel 4 E F channel 5 channel 4 m2 m1 m1 m2 ASICs... THE COURSE 17.2 Detailed Routing 13 The different types of connections that can be made to a cell. This cell has connectors at the top and bottom of the cell (normal for cells intended for use with a two-level metal process) and internal connectors (normal for logic cells intended for use with a three-level metal process). The interconnect and connections are drawn to scale. 9. routinggrid 4. internalconnector 5. track location blockedby m2 inside cell 7. connectorwith noequivalent6. off-grid connector 8. feedthroughbetweenequivalent connectorswith internal jog 1. electricallyequivalent connectors;router can connect to top or bottom and useconnectors as afeedthrough 2. equivalentconnectors; router canconnect to top or bottom but cannot useas a feedthrough 3. must-join connectors,router must connectto top and bottom 10. cellabutment box m2 m2 14 SECTION 17 ROUTING ASICS... THE COURSE Terms used in channel routing. (a) A channel with four horizontal tracks. (b) An expanded view of the left-hand portion of the channel showing (approximately to scale) how the m1 and m2 layers connect to the logic cells on either side of the channel. (c) The construction of a via1 (m1/m2 via). 0 3 0 2 5 4 7 5 8 6 3 10 10 70 0 0 6 0 6 0 8 9 0 9 4 horizontaltracks horizontal trackpitch=8 λ 2 0 1 41 2 0 11cellabutment box connector,terminal, port,or pinm2via1 m1 branch unusedterminal trunk orsegment netexitingchannelpseudo-terminal m1m2(a) (b) expandedview ofchannel 4λ 4λ m2m1 logic cell = + +via1 m1 m2 contact (c) via1 0 vacantterminal vertical trackpitch=8 λ ASICs... THE COURSE 17.2 Detailed Routing 15 17.2.1 Goals and Objectives Key terms and concepts: Goal: to complete all the connections between logic cells ? Objectives: The total interconnect length and area ? The number of layer changes that the connections have to make ? The delay of critical paths 17.2.2 Measurement of Channel Density Key terms and concepts: local density ? global density ? channel density 17.2.3 Algorithms Key terms and concepts: restricted channel-routing problem 17.2.4 Left-Edge Algorithm Key terms and concepts: left-edge algorithm (LEA) 17.2.5 Constraints and Routing Graphs Key terms and concepts: vertical constraint ? vertical-constraint graph ? directed graph ? horizontal constraint ? horizontal-constraint graph ? vertical-constraint cycle (or cyclic constraint) ? dogleg router ? overlap ? overlap capacitance ? coupling capacitance ? overlap capacitance ? channel-routing compaction The definitions of local channel density and global channel density. Lines represent the m1 and m2 interconnect in the channel to simplify the drawing. 0 3 0 2 5 4 7 5 8 6 3 10 10 70 0 0 6 0 6 0 8 9 0 92 0 1 41 local density=3local density=2 local density=1 local density=global density orchannel density=4 m2 m1 4 λvia1 16 SECTION 17 ROUTING ASICS... THE COURSE Left-edge algorithm. (a) Sorted list of segments. (b) Assignment to tracks. (c) Completed channel route (with m1 and m2 interconnect represented by lines). 31 2 4 5 6 7 8 910 0 3 0 2 5 4 7 5 8 6 3 10 10 70 0 0 6 0 6 0 8 9 0 92 0 1 41 (a) (c) Segments sortedby their left edge. 1 4 6 92 5 8 103 7(b) Left edge of segment 6connects to bottomof channel. Left edge of segment 7connects to topof channel. Segments assigned to tracks by their left edges. Net 6 has 3 terminals. m2 m1 4 λvia1 ASICs... THE COURSE 17.2 Detailed Routing 17 Routing graphs. (a) Channel with a global density of 4. (b) The vertical constraint graph. If two nets occupy the same column, the net at the top of the channel imposes a vertical constraint on the net at the bottom. For example, net 2 im- poses a vertical constraint on net 4. Thus the interconnect for net 4 must use a track above net 2. (c) Horizontal-constraint graph. If the segments of two nets overlap, they are connected in the horizontal-constraint graph. This graph determines the global channel density. The addition of a dogleg, an extra trunk, in the wiring of a net can resolve cyclic vertical constraints. 0 3 0 2 5 4 7 5 8 6 3 10 10 70 0 0 6 0 6 0 8 9 0 92 0 1 41 8 3 10 9 6 72 4 (a) (b) (c) Thus, the global channel density=4. The set of 4 nodes,(3, 6, 5, 7), is thelargest completely connected loop. 1 2 3 4 5 6 7 8 9 10 m2 m1 4λvia1 1 21 0 12 dogleg—morethan one trunkper net1 21 0 12 (b) 1 2(a) (c) m2m1 via1 18 SECTION 17 ROUTING ASICS... THE COURSE 17.2.6 Area-Routing Algorithms Key terms and concepts: grid-expansion ? maze-running ? line-search ? Lee maze-running algorithm? wave propagation ? Hightower algorithm ? line-search algorithm (or line- probe algorithm) ? escape line ? escape point 17.2.7 Multilevel Routing Key terms and concepts: two-layer routing ? 2.5-layer routing ? three-layer routing ? reserved-layer routing ? unreserved-layer routing ? HVH routing ? VHV routing ? multilevel routing ? cell porosity The Lee maze-running algorithm. The algorithm finds a path from source (X) to target (Y) by emitting a wave from both the source and the target at the same time. Successive outward moves are marked in each bin. Once the target is reached, the path is found by backtracking (if there is a choice of bins with equal labeled values, we choose the bin that avoids changing direction). (The original form of the Lee algorithm uses a single wave.) Hightower area-routing algorithm. (a) Escape lines are constructed from source (X) and target (Y) toward each other until they hit obstacles. (b) An escape point is found on the escape line so that the next escape line perpendicu- lar to the original misses the next obstacle. The path is complete when escape lines from source and target meet. 1X 212 Y 2 34 4 332 444 4 4 34 3 5 134 234 4 3 1 32 23 34 4 2 1 Y X Y Xescape line escapepoint (a) (b) source escape line target intersectionof escape lines ASICs... THE COURSE 17.3 Special Routing 19 17.2.8 Timing-Driven Detailed Routing Key terms and concepts: the global router has already set the path the interconnect will follow and little can be done to improve timing ? reduce the number of vias ? alter the interconnect width to optimize delay ? minimize overlap capacitance ? gains are small ? high-frequency clock nets are chamfered (rounded) to match impedances at branches and control reflections at corners. 17.2.9 Final Routing Steps Key terms and concepts: unroutes ? rip-up and reroute? engineering change orders (ECO)? via removal? routing compaction 17.3 Special Routing Key terms and concepts: clock and power nets Three-level channel routing. In this diagram the m2 and m3 routing pitch is set to twice the m1 routing pitch. Routing density can be increased further if all the routing pitches can be made equal—a dif- ficult process challenge. 0 3 5 7 5 8 3 10 10 78λ 642 0 6 0 6 8 9 0 92 1 41 = + +via1 m1 m2 contact = + +via2 m2 m3 contact = +via1 via2 m2 m1 andm3 m1routingpitch 16λ m3routingpitch interconnect tochannel above logic-cellabutment box connectorexitingchannel 16λm2 routing pitch 20 SECTION 17 ROUTING ASICS... THE COURSE 17.3.1 Clock Routing Key terms and concepts: clock-tree synthesis ? clock-buffer insertion ? activity-induced clock skew Clock routing. (a) A clock network for a cell-based ASIC. (b) Equalizing the interconnect segments between CLK and all destinations (by including jogs if necessary) minimizes clock skew. A1B1 B2 D1 D2 D3 E1 E2 F1 CLK (b) A1B1B2 D1D2 D3 E1 E2 F1 CLK (a) jog ASICs... THE COURSE 17.4 Circuit Extraction and DRC 21 17.3.2 Power Routing Key terms and concepts: power-bus sizing ? metal electromigration ? power simulation ? mean time to failure (MTTF) ? metallization reliability rules ? maximum metal-width rules (fat-metal rules) ? die attach ? power grid ? end-cap cells ? routing bias ? flip and abut 17.4 Circuit Extraction and DRC Key terms and concepts: circuit-extraction ? design-rule check ? Dracula deck ? design rule viola- tions Metallization reliability rules for a typical 0.5 micron (λ=0.25μm) CMOS process. Layer/contact/via Current limit Metal thickness Resistance m1 1mA μm–1 7000? 95m?/square m2 1mA μm–1 7000? 95m?/square m3 2 mA μm–1 12,000? 48m?/square 0.8μm square m1 contact to diffusion 0.7 mA 11? 0.8μm square m1 contact to poly 0.7mA 16? 0.8μm square m1/m2 via (via1) 0.7mA 3.6? 0.8μm square m2/m3 via (via2) 0.7mA 3.6? 22 SECTION 17 ROUTING ASICS... THE COURSE 17.4.1 SPF, RSPF, and DSPF Key terms and concepts: standard parasitic format (SPF) ? regular SPF ? reduced SPF ? detailed SPF #Design Name : EXAMPLE1 #Date : 6 August 1995 #Time : 12:00:00 #Resistance Units : 1 ohms #Capacitance Units : 1 pico farads #Syntax : #N <netName> #C <capVal> # F <from CompName> <fromPinName> # GC <conductance> # | # REQ <res> # GRC <conductance> # T <toCompName> <toPinName> RC <rcConstant> A <value> # | Parasitic capacitances for a typical 1μm (λ=0.5μm) three-level metal CMOS process. Element Area/fFμm–2 Fringing/fFμm–1 poly (over gate oxide) to substrate 1.73 NA poly (over field oxide) to substrate 0.058 0.043 m1 to diffusion or poly 0.055 0.049 m1 to substrate 0.031 0.044 m2 to diffusion 0.019 0.038 m2 to substrate 0.015 0.035 m2 to poly 0.022 0.040 m2 to m1 0.035 0.046 m3 to diffusion 0.011 0.034 m3 to substrate 0.010 0.033 m3 to poly 0.012 0.034 m3 to m1 0.016 0.039 m3 to m2 0.035 0.049 n+ junction (at 0V bias) 0.36 NA p+ junction (at 0V bias) 0.46 NA ASICs... THE COURSE 17.4 Circuit Extraction and DRC 23 # RPI <res> # C1 <cap> # C2 <cap> The regular and reduced standard parasitic format (SPF) models for interconnect. (a) An example of an interconnect network with fanout. The driving-point admittance of the interconnect network is Y(s). (b) The SPF model of the interconnect. (c) The lumped-capacitance interconnect model. (d) The lumped-RC interconnect model. (e) The PI segment interconnect model (notice the capacitor nearest the output node is la- beled C2 rather than C1). The values of C, R, C1, and C2 are calculated so that Y1(s), Y2(s), and Y3(s) are the first-, second-, and third-order Taylor-series approximations to Y(s). RAB CA CB RBC CCY(s)A B C (a) C_1 B_1A_1 BB_1 CC_1+ + V(A_1) V(A_1) Y1(s), Y2(s), orY3(s) A A_1 (b) R3 R4 C3 C4 C Y1(s) Alumped-C (c) R C2 C1 Y3(s) API segment (e) R C Y2(s) Alumped-RC (d) 24 SECTION 17 ROUTING ASICS... THE COURSE # GPI <conductance> # T <toCompName> <toPinName> RC <rcConstant> A <value> # TIMING.ADMITTANCE.MODEL = PI # TIMING.CAPACITANCE.MODEL = PP N CLOCK C 3.66 F ROOT Z RPI 8.85 C1 2.49 C2 1.17 GPI = 0.0 T DF1 G RC 22.20 T DF2 G RC 13.05 * Design Name : EXAMPLE1 * Date : 6 August 1995 * Time : 12:00:00 * Resistance Units : 1 ohms * Capacitance Units : 1 pico farads *| RSPF 1.0 *| DELIMITER "_" .SUBCKT EXAMPLE1 OUT IN *| GROUND_NET VSS * TIMING.CAPACITANCE.MODEL = PP *|NET CLOCK 3.66PF *|DRIVER ROOT_Z ROOT Z *|S (ROOT_Z_OUTP1 0.0 0.0) R2 ROOT_Z ROOT_Z_OUTP1 8.85 C1 ROOT_Z_OUTP1 VSS 2.49PF C2 ROOT_Z VSS 1.17PF *|LOAD DF2_G DF1 G *|S (DF1_G_INP1 0.0 0.0) E1 DF1_G_INP1 VSS ROOT_Z VSS 1.0 R3 DF1_G_INP1 DF1_G 22.20 C3 DF1_G VSS 1.0PF *|LOAD DF2_G DF2 G *|S (DF2_G_INP1 0.0 0.0) E2 DF2_G_INP1 VSS ROOT_Z VSS 1.0 R4 DF2_G_INP1 DF2_G 13.05 C4 DF2_G VSS 1.0PF *Instance Section XDF1 DF1_Q DF1_QN DF1_D DF1_G DF1_CD DF1_VDD DF1_VSS DFF3 XDF2 DF2_Q DF2_QN DF2_D DF2_G DF2_CD DF2_VDD DF2_VSS DFF3 XROOT ROOT_Z ROOT_A ROOT_VDD ROOT_VSS BUF ASICs... THE COURSE 17.4 Circuit Extraction and DRC 25 .ENDS .END .SUBCKT BUFFER OUT IN * Net Section *|GROUND_NET VSS *|NET IN 3.8E-01PF *|P (IN I 0.0 0.0 5.0) *|I (INV1:A INV A I 0.0 10.0 5.0) C1 IN VSS 1.1E-01PF C2 INV1:A VSS 2.7E-01PF R1 IN INV1:A 1.7E00 *|NET OUT 1.54E-01PF *|S (OUT:1 30.0 10.0) *|P (OUT O 0.0 30.0 0.0) *|I (INV:OUT INV1 OUT O 0.0 20.0 10.0) C3 INV1:OUT VSS 1.4E-01PF C4 OUT:1 VSS 6.3E-03PF C5 OUT VSS 7.7E-03PF R2 INV1:OUT OUT:1 3.11E00 R3 OUT:1 OUT 3.03E00 *Instance Section XINV1 INV:A INV1:OUT INV .ENDS 17.4.2 Design Checks Key terms and concepts: design-rule check (DRC)? phantom-level DRC? hard layout? Dracula deck ? layout versus schematic (LVS) 17.4.3 Mask Preparation Key terms and concepts: maskwork symbol (M inside a circle) ? copyright symbol (C inside a circle)? kerf ? scribe lines ? edge-seal structures? Caltech Intermediate Format (CIF, a public domain text format) ? GDSII Stream (Calma Stream, Cadence Stream)? fab? mask shop? grace value? sizing or mask tooling? tooling specification? mask bias? bird’s beak effect? glass masks or reticles ? spot size ? critical layers ? optical proximity correction (OPC) 26 SECTION 17 ROUTING ASICS... THE COURSE 17.5 Summary Key terms and concepts: ? Routing is divided into global and detailed routing. ? Routing algorithms should match the placement algorithms. ? Routing is not complete if there are unroutes. ? Clock and power nets are handled as special cases. ? Clock-net widths and power-bus widths must usually be set by hand. ? DRC and LVS checks are needed before a design is complete. The detailed standard parasitic format (DSPF) for interconnect representation. (a) An example network with two m2 paths connected to a logic cell, INV1. The grid shows the coordinates. (b) The equivalent DSPF circuit corresponding to the DSPF file in the text. (0,0) (0,10) (10,0) (20,0) (30,0)AIN OUT INV1 OUT:1OUT OUTIN A OUT INV1 C1 C2 R1 R2 C3 C4 C5 R3INV1:OUT OUT:1INV1:A (a) (b) m2 instancename subnodeinstancepin namepinname netname