Maddy, S.L., “Phase-Locked Loop” The Electrical Engineering Handbook Ed. Richard C. Dorf Boca Raton: CRC Press LLC, 2000 76 Phase-Locked Loop 76.1 Introduction 76.2 Loop Filter 76.3 Noise 76.4 PLL Design Procedures 76.5 Components 76.6 Applications 76.1 Introduction A phase-locked loop (PLL) is a system that uses feedback to maintain an output signal in a specific phase relationship with a reference signal. PLLs are used in many areas of electronics to control the frequency and/or phase of a signal. These applications include frequency synthesizers, analog and digital modulators and demod- ulators, and clock recovery circuits. Figure 76.1 shows the block diagram of a basic PLL system. The phase detector consists of a device that produces an output voltage proportional to the phase difference of the two input signals. The VCO (voltage-controlled oscillator) is a circuit that produces an ac output signal whose frequency is proportional to the input control voltage. The divide by N is a device that produces an output signal whose frequency is an integer (denoted by N) division of the input signal frequency. The loop filter is a circuit that is used to control the PLL dynamics and therefore the performance of the system. The F(s) term is used to denote the Laplace transfer function of this filter. Servo theory can now be used to derive the equations for the output signal phase relative to the reference input signal phase. Because the VCO control voltage sets the frequency of the oscillation (rather than the phase), this will produce a pure integration when writing this expression. Several of the components of the PLL have a fixed gain associated with them. These are the VCO control voltage to output frequency conversion gain (K v ), the phase detector input signal phase difference to output voltage conversion gain (K f ), and the feedback division ratio (N). These gains can be combined into a single factor called the loop gain (K). This loop gain is calculated using Eq. (76.1) and is then used in the following equations to calculate the loop transfer function. (76.1) The closed-loop transfer function [H(s)] can now be written and is shown in Eq. (76.2). This function is typically used to examine the frequency or time-domain response of a PLL and defines the relationship of the phase of the VCO output signal (u o ) to the phase of the reference input (u i ). It also describes the relationship of a change in the output frequency to a change in the input frequency. This function is low-pass in nature. (76.2) K KK N v = ′ f Hs s s KFs sKFs o i () () () () () == + q q Steven L. Maddy RLM Research ? 2000 by CRC Press LLC The loop error function, shown in Eq. (76.3), describes the difference between the VCO phase and the reference phase and is typically used to examine the performance of PLLs that are modulated. This function is high-pass in nature. (76.3) The open-loop transfer function [G(s)] is shown in Eq. (76.4). This function describes the operation of the loop before the feedback path is completed. It is useful during the design of the system in determining the gain and phase margin of the PLL. These are indications of the stability of a PLL when the feedback loop is connected. (76.4) These functions describe the performance of the basic PLL and can now be used to derive synthesis equations. The synthesis equations will be used to calculate circuit components that will give a desired performance characteristic. These characteristics usually involve the low-pass corner frequency and shape of the closed-loop response characteristic [Eq. (76.2)] and determine such things as the loop lock-up time, the ability to track the input signal, and the output signal noise characteristics. 76.2 Loop Filter The loop filter is used to shape the overall response of the PLL to meet the design goals of the system. There are two implementations of the loop filter that are used in the vast majority of PLLs: the passive lag circuit shown in Fig. 76.2 and the active circuit shown in Fig. 76.3. These two circuits both produce a PLL with a second-order response characteristic. The transfer functions of these loop filter circuits may now be derived and are shown in Eqs. (76.5) for the passive circuit (Fig. 76.2) and (76.6) for the active circuit (Fig. 76.3). (76.5) FIGURE 76.1 PLL block diagram. FIGURE 76.2 Passive loop filter. FIGURE 76.3 Active loop filter. qq q q q io i e i ss s s s s sKFs () () () () () () - == + Gs KFs s () () = Fs sCR sR RC p () () = + ++ 12 121 1 1 ? 2000 by CRC Press LLC (76.6) These loop filter equations may now be substituted into Eq. (76.2) to form the closed-loop transfer functions of the PLL. These are shown as Eqs. (76.7) for the case of the passive filter and (76.8) for the active. (76.7) (76.8) These closed-loop equations can also be written in the forms shown below to place the function in terms of the damping factor (z) and the loop natural frequency (v n ). It will be shown later that these are very useful parameters in specifying PLL performance. Equation (76.9) is the form used for the PLL with a passive loop filter, and Eq. (76.10) is used for the active loop filter case. (76.9) (76.10) Solving Eqs. (76.7) and (76.9) for R 1 and R 2 in terms of the loop parameters z and v n , we now obtain the synthesis equations for a PLL with a passive loop filter. These are shown as Eqs. (76.11) and (76.12). (76.11) (76.12) To maintain resistor values that are positive the passive loop filter PLL must meet the constraint shown in Eq. (76.13). (76.13) Fs sRC sRC a ()= + 21 11 1 Hs s KR RR K RRC ss RRC KR RR K RRC p ()= 2 12121 2 121 2 12 121 1 + + + + + + + é ? ê ê ù ? ú ú + + () () () Hs s KR R K RC ss KR R K RC a ()= 2 11 2 2 11 + ++ Hs sK ss p nn n nn ()= / 22 2 [()]2 2 2 zw w w zw w -+ ++ Hs s ss a nn nn ()= 2 2 2 2 2 zw w zw w + ++ R CKC n 2 = 21z w - R K C R n 1 = w 2 2 - z w > n K2 ? 2000 by CRC Press LLC For the active loop filter case Eqs. (76.8) and (76.10) are solved and yield the synthesis equations shown in Eqs. (76.14) and (76.15). It can be seen that no constraints on the loop damping factor exist in this case. (76.14) (76.15) A typical design procedure for these loop filters would be, first, to select the loop damping factor and natural frequency based on the system requirements. Next, all the loop gain parameters are determined. A convenient capacitor value may then be selected. The remaining resistors can now be computed from the synthesis equations presented above. Figure 76.4 shows the closed-loop frequency response of a PLL with an active loop filter [Eq. (76.10)] for various values of damping factor. The loop natural frequency has been normalized to 1 Hz for all cases. Substituting Eq. (76.6) into (76.3) will give the loop error response in terms of damping factor. This function is shown plotted in Fig. 76.5. These plots may be used to select the PLL performance parameters that will give a desired frequency response shape. The time response of a PLL with an active loop filter to a step in input phase was also computed and is shown plotted in Fig. 76.6. 76.3 Noise An important design aspect of a PLL is the noise content of the output. The dominant resultant noise will appear as phase noise (jitter) on the output signal from the VCO. Due to the dynamics of the PLL some of these noise sources will be filtered by the loop transfer function [Eq. (76.2)] that is a low-pass characteristic. FIGURE 76.4 Closed-loop second-order type-2 PLL error response for various damping factors. R K C n 1 2 = w R C n 2 = 2z w ? 2000 by CRC Press LLC Others will be processed by the loop error function [Eq. (76.3)] that is a high-pass characteristic. Table 76.1 shows the major sources of noise in a PLL and the effect of the loop dynamics on this noise. All these factors must be combined to evaluate the complete noise performance of a PLL. Often it will be found that one particular noise source will be dominant and the PLL performance can then be adjusted to minimize the output noise. FIGURE 76.5 Closed-loop second-order type-2 PLL step response for various damping factors. FIGURE 76.6 Closed-loop PLL response for various damping factors. ? 2000 by CRC Press LLC A PLL is frequently used to enhance the noise performance of an oscillator by taking advantage of these noise-filtering properties. For example, a crystal oscillator typically has very good low-frequency noise charac- teristics, and a free-running LC oscillator can be designed with very good high-frequency noise performance but will exhibit poor low-frequency noise characteristics. By phase-locking an LC oscillator to a crystal oscillator and setting the loop response corner frequency to the noise crossover point between the two oscillators, the desirable characteristics of both oscillators are realized. When designing frequency synthesizers using PLLs, care must be taken to prevent noise from the PLL components from introducing excessive noise. The divider ratio (N) used in the feedback of the loop has the effect of multiplying any noise that appears at the input or output of the phase detector by this factor. Frequently, a large value of N is required to achieve the desired output frequencies. This can cause excessive output noise. All these effects must be taken into account to achieve a PLL design with optimum noise performance. 76.4 PLL Design Procedures The specific steps used to design a PLL depend on the intended application. Typically the architecture of the loop will be determined by the output frequency agility required (frequency synthesizer) and the reference sources available. Other requirements such as size and cost play important factors, as well as available standard components. Once the topology has been determined, then the desired loop transfer function must be synthe- sized. This may be dictated by noise requirements as discussed above or other factors such as loop lock-up time or input signal tracking ability. The design Eqs. (76.11) through (76.15) may then be used to determine the component values required in the loop filter. Frequently several of these factors must be balanced or traded off to obtain an acceptable design. A design that requires high performance in several of these areas usually can be realized at the expense of design complexity or increased component cost. 76.5 Components The development of large-scale integrated circuits over the past several years has made the design and implementation of PLLs and frequency synthesizers much cheaper and easier. Several major manufacturers (Motorola, Signetics, National, Plessey, etc.) currently supply a wide range of components for PLL implemen- tation. The most complex of these are the synthesizer circuits that provide a programmable reference divider, programmable divide by N, and a phase detector. Several configurations of these circuits are available to suit most applications. Integrated circuits are also available to implement most of the individual blocks shown in Fig. 76.1. A wide variety of phase detector circuits are available, and the optimum type will depend on the circuit requirements. An analog multiplier (or mixer) may be used and is most common in applications where the comparison frequency must be very high. This type of phase detector produces an output that is the multipli- cation of the two input signals. If the inputs are sine waves, the output will consist of a double-frequency component as well as a dc component that is proportional to the cosine of the input phase difference. The double-frequency component can be removed with a low-pass filter, leaving only the dc component. The analog multiplier has a somewhat limited phase range of ±90 degrees. The remainder of the phase detector types discussed here are digital in nature and operate using digital edges or transitions of the signals to be compared. TABLE 76.1 PLL Noise Sources Noise Source Filter Function Reference oscillator phase noise Low pass Phase detector noise Low pass Active loop filter input noise Low pass Digital divider noise Low pass Active loop filter output noise High pass VCO free-running phase noise High pass ? 2000 by CRC Press LLC The sample-and-hold phase detector is widely used where optimum noise performance is required. This circuit operates by using one of the phase detector inputs to sample the voltage on the other input. This latter input is usually converted to a triangle wave to give a linear phase detector characteristic. Once the input is sampled, its voltage is held using a capacitor. The good noise performance is achieved since most of the time the phase detector output is simply a stored charge on this capacitor. The phase range of the sample-and-hold phase detector depends on the type of waveform shaping used and can range from ±90 to ±180 degrees. One of the simplest types of phase detectors to implement uses an exclusive OR gate to digitally multiply the two signals together. The output must then be low-pass filtered to extract only the dc component. The main drawback to this circuit is the large component that exists in the output at twice the input frequency. This requires a large amount of low-pass filtering and may restrict the PLL design. The phase range of this type of circuit is ±90 degrees. One of the main drawbacks of all the above types of phase detectors is that they only provide an output that is proportional to phase and not to a frequency difference in the input signals. For many applications the PLL input signals are initially not on the same frequency. Several techniques have been used in the past to resolve this such as sweeping the VCO or using separate circuitry to first acquire the input frequency. The sequential (sometimes called phase/frequency) phase detector has become the most commonly used solution due to its wide availability in integrated form. This type of phase detector produces pulses with the width of the pulses indicating the phase difference of the inputs. It also has the characteristic of providing the correct output to steer the VCO to the correct frequency. The noise characteristic of this type of phase detector is also quite good since either no or very narrow pulses are produced when the inputs are in phase with each other. The phase range of this type of circuit is ±360 degrees. Digital dividers are widely available and may either have programmable or fixed division ratios depending on the application. For optimum noise performance a synchronous type of divider should be used. When a programmable divider is required to operate at a high frequency (>50 MHz), a dual modulus circuit is normally used. This circuit uses a technique called pulse swallowing to extend the range of normal programmable divider integrated circuits by using a dual modulus prescaler (usually ECL). The dual modulus prescaler is a high- frequency divider that can be programmed to divide by only two sequential values. A second programmable divider section is then used to control the prescaler. Further details of this type of divider are available from component manufacturers’ data sheets as well as in the references. The voltage-controlled oscillator is typically the most critical circuit in determining the overall noise per- formance of a PLL. For this reason it is often implemented using discrete components, especially at the higher frequencies. Some digital integrated circuits exist for lower-frequency VCOs, and microwave integrated circuit VCOs are now available for use to several gigahertz. The major design parameters for a VCO include the operating frequency, tuning range, tuning linearity, and phase noise performance. Further information on the design of VCOs is contained in the references. Loop filters used in PLLs may be either active or passive depending on the specific application. Active filters are normally used in more critical applications when superior control of loop parameters and reference frequency suppression is required. The loop filter is typically followed by a low-pass filter to remove any residual reference frequency component from the phase detector. This low-pass filter will affect the calculated loop response and will typically appear to reduce the loop damping factor as its corner frequency is brought closer to the loop natural frequency. To avoid this degradation the corner frequency of this filter should be approxi- mately one order of magnitude greater than the loop natural frequency. In some cases a notch filter may be used to reduce the reference frequency when it is close to the reference frequency. 76.6 Applications Phase-locked loops are used in many applications including frequency synthesis, modulation, demodulation, and clock recovery. A frequency synthesizer is a PLL that uses a programmable divider in the feedback. By selecting various values of division ratio, several output frequencies may be obtained that are integer multiples of the reference frequency (Fref). Frequency synthesizers are widely used in radio communications equipment to obtain a stable frequency source that may be tuned to a desired radio channel. Since the output frequency is an integer multiple of the reference frequency, this will determine the channel spacing obtained. The main ? 2000 by CRC Press LLC design parameters for a synthesizer are typically determined by the required channel change time and output noise. Transmitting equipment for radio communications frequently uses PLLs to obtain frequency modulation (FM) or phase modulation (PM). A PLL is first designed to generate a radio frequency signal. The modulation signal (i.e., voice) is then applied to the loop. For FM the modulating signal is added to the output of the loop filter. The PLL will maintain the center frequency of the VCO, while the modulation will vary the VCO frequency about this center. The frequency response of the FM input will exhibit a high-pass response and is described by the error function shown in Eq. (76.3). Phase modulation is obtained by adding the modulation signal to the input of the loop filter. The modulation will then vary the phase of the VCO output signal. The frequency response of the PM input will be a low-pass characteristic described by the closed-loop transfer function shown in Eq. (76.2). A communications receiver must extract the modulation from a radio frequency carrier. A PLL may be used by phase locking a VCO to the received input signal. The loop filter output will then contain the extracted FM signal, and the loop filter input will contain the PM signal. In this case the frequency response of the FM output will be a low-pass function described by the closed-loop transfer function and the PM output response will be a high-pass function described by the error function. In digital communications (modems) it is frequently necessary to extract a coherent clock signal from an input data stream. A PLL is often used for this task by locking a VCO to the input data. Depending on the type of data encoding that is used, the data may first need to be processed before connecting the PLL. The VCO output is then used as the clock to extract the data bits from the input signal. Defining Terms Capture range: The range of input frequencies over which the PLL can acquire phase lock. Damping factor: A measure of the ability of the PLL to track an input signal step. Usually used to indicate the amount of overshoot present in the output to a step perturbation in the input. Free-run frequency: The frequency at which the VCO will oscillate when no input signal is presented to the PLL. Sometimes referred to as the rest frequency. Lock range: The range of input frequencies over which the PLL will remain in phase lock once acquisition has occurred. Loop filter: The filter function that follows the phase detector and determines the system dynamic perfor- mance. Loop gain: The combination of all dc gains in the PLL. Low-pass filter: A filter that usually follows the loop filter and is used to remove the reference frequency components generated by the phase detector. Natural frequency: The characteristic frequency of the PLL dynamic performance. The frequency of the closed-loop transfer function dominant pole. Phase detector gain: The ratio of the dc output voltage of the phase detector to the input phase difference. This is usually expressed in units of volts/radian. VCO gain: The ratio of the VCO output frequency to the dc control input level. This is usually expressed in units of radians/second/volt. Related Topics 10.3 The Ideal Linear-Phase Low-Pass Filter ? 25.3 Application-Specific Integrated Circuits ? 73.2 Noise References AFDPLUS Reference Manual, Boulder, Colo.: RLM Research, 1991 (software used to generate the graphs in this section). R. G. Best, Phase-Locked Loops—Theory, Design & Applications, New York: McGraw-Hill, 1984. A. Blanchard, Phase-Locked Loops, Application to Coherent Receiver Design, New York: Wiley Interscience, 1976. ? 2000 by CRC Press LLC W. F. Egan, Frequency Synthesis by Phase Lock, New York: Wiley Interscience, 1981. F. M. Gardner, Phaselock Techniques, New York: Wiley, 1979. J. Gorski-Popiel, Frequency Synthesis; Techniques & Applications, Piscataway, N.J.: IEEE Press, 1975. W.C. Lindsey and M.K. Simon, Phase-Locked Loops & Their Applications, Piscataway, N.J.: IEEE Press, 1978. V. Manassewtsch, Frequency Synthesizers: Theory and Design, New York: Wiley Interscience, 1980. U. L. Rhode, Digital PLL Frequency Synthesizers Theory and Design, Englewood Cliffs, N.J.: Prentice-Hall, 1983. Further Information Recommended periodicals that cover the subject of PLLs include IEEE Transactions on Communications, IEEE Transactions on Circuits and Systems, and IEEE Transactions on Signal Processing. Occasionally articles dealing with PLLs may also be found in EDN, Electronic Design, RF Design, and Microwaves and RF Magazine. A four- part PLL tutorial article titled PLL Primer, by Andrzej B. Przedpelski, appeared in RF Design Magazine in the March/April 1983, May/June 1983, July/August 1983, and November 1987 issues. Another good source of general PLL design information can be obtained from application notes available from various PLL component manufacturers. Phase-Locked Loop Design Fundamentals, by Garth Nash, is available from Motorola, Inc. as AN-535 and gives an excellent step-by-step synthesizer design procedure. ? 2000 by CRC Press LLC