ASICs...THE COURSE (1 WEEK)
1
PROGRAMMABLE
ASIC I/O CELLS
6.1 DC Output
Key concepts:
Input/output cell (I/O cell) ? I/O requirements ? DC output ? AC output ? DC input ? AC input ?
Clock input ? Power input
A robot arm example
To design a system work from the outputs
back to the inputs
(a) Three small DC motors drive the arm
(b) Switches control each motor
A circuit to drive a small electric
motor (0.5A) using ASIC I/O buffers
Work from the outputs to the inputs
The 470? resistors drop up to 5V
if an output buffer current
approaches 10mA, reducing the
drive to the output transistors
open–closeup–down
left–right(a) (b)
motor+
direction control
motor +directioncontrol
all R=470 ? 5VI/O buffer
IOmax =10mA (continuous)ASIC
6
2 SECTION 6 PROGRAMMABLE ASIC I/O CELLS ASICS... THE COURSE
CMOS output buffer characteristics
(a) A CMOS complementary output buffer
(b) Transistor M2 (M1 off) sinks (to GND) a current IOL through a pull-up resistor, R1
(c) Transistor M1 (M2 off) sources (from VDD) a current –IOH (IOH is negative) through a
pull-down resistor, R2
(d) Output characteristics:
? Data books specify characteristics at two points, A (VOHmin, IOHmax) and B (VOLmax,
IOLmax)
Example (Xilinx XC5200):
VOLmax=0.4V, low-level output voltage at IOLmax=8.0mA
VOHmin=4.0V, high-level output voltage at IOHmax=–8.0mA
? Output current, IO, is positive if it flows into the output
? Input current, if there is any, is positive if it flows into the input
? Output buffer can force the output pad to 0.4V or lower and sink no more than 8mA
? When the output is 4V, the buffer can source 8mA
? Specifying only VOLmax=0.4V and VOHmin=4.0V for a technology is strictly incorrect
? We do not know the value of IOLpeak or IOHpeak (typical values are 50–200mA)
'1'
M1'0'
IOH
M2
IOL VOHI/Opad
M1
M2 VO
IO
VO
IO
VDD0VOLmax VOHmin
R1
R2(a) (b) (c) (d)
IOLpeak–IOHpeak
IOL –IOH
A B
VDDVDDVDD
VOLIN tryingto be '0' tryingto be '1'off
off 8mA(negative)
ASICs... THE COURSE 6.2 AC Output 3
6.1.1 Totem-Pole Output
6.1.2 Clamp Diodes
6.2 AC Output
Keywords: totem-pole output buffer ? similar to TTL totem-pole output ? two n-channel
transistors in a stack ? reduced output voltage swing
Output buffer characteristics
(a) A CMOS totem-pole output stage (both M1 and M2 are n-channel transistors)
(b) Totem-pole output characteristics (notice the reduced signal swing)
(c) Clamp diodes, D1 and D2, in an output buffer (totem-pole or complementary) prevent
the I/O pad from voltage excursions greater than VDD and less than VSS
(d) The clamp diodes conduct as the output voltage exceeds the supply voltage bounds
Keywords: bus transceivers ? bus transaction (a sequence of signals on a bus) ? floating a bus
? bus keeper ? trip points ? three-stated (high-impedance or hi-Z) ? time to float ? disable time,
time to begin hi-Z, or time to turn off ? slew ? sustained three-state (s/t/s) ? turnaround cycle
I/OpadVDDM1
M2 IOL–IOH V
O
IOIOL
–IOH VO
IO
VDD
VDDM1
M2 IO +VO
D1
D2 VDD +0.5V–0.5VVDD –V tn
(a) (b) (c) (d)
IO +VO
4 SECTION 6 PROGRAMMABLE ASIC I/O CELLS ASICS... THE COURSE
Three-state bus timing
The on-chip delays, t2OE and t3OE,
for the logic that generates signals
CHIP2.E1 and CHIP3.E1 are
derived from the timing models
(The minimum values for each chip
would be the clock-to-Q delay times)
BUSA.B1
CHIP2.OE(ACT2/3)
CHIP3.OE(XC3000)
'1' hi-Z '0'
tfloat tslewtactive
VOHmin
VOLmax
CLK
hi-Z to '0'
tsparet2OE t3OE
VILmax(Xilinx)
50%
50%
50%
ASICs... THE COURSE 6.2 AC Output 5
6.2.1 Supply Bounce
Supply bounce
A substantial current IOL may flow in the resistance, RS, and inductance, LS, that are be-
tween the on-chip GND net and the off-chip, external ground connection
(a) As the pull-down device, M1, switches, it causes the GND net (value VSS) to bounce
(b) The supply bounce is dependent on the output slew rate
(c) Ground bounce can cause other output buffers to generate a logic glitch
(d) Bounce can also cause errors on other inputs
Keywords: simultaneously-switching outputs (SSOs) ? quiet I/O ? slew-rate control ? I/O
management ? packaging ? PCB layout ? ground planes ? inductance
'0' to '1' M1
RL
(a)
VDD
GND
OUT1 VOLmax
t
t
M2
M3
VDD
TTL '1'
M4
M5
VDD
'1' OUT2O2I1IN1 1.4V
2.5V
t1.4V
3.0V
1.4V
0V
VSS1.4 V
false '1'
false '0'
VOHmin
VOLmax
0V
VOLP
(b)
(c)
(d)
RSLSM1 switchingcauses groundbounce IOL
IOL
t
Vo1 Vo2 Vo2
Vo1
Vi1
Vi1
6 SECTION 6 PROGRAMMABLE ASIC I/O CELLS ASICS... THE COURSE
6.2.2 Transmission Lines
6.3 DC Input
Transmission lines
(a) A printed-circuit board (PCB) trace is a transmission (TX) line (Z0 = 50?–100?)
(b) A driver launches an incident wave, which is reflected at the end of the line
(c) A connection starts to look like a TX line when the rise time is about 2 × line delay (2tf)
R0
Z0 tfTX line
00
1ns per 15cm +R0
Z0
2tf tf
5V 0
5V 5V
Vint
t t
Cin
Z0 VOLmax
t
2.5VVOHmin
(c)
2tf
(b)(a)
DR RX Vin
Vin V1 V2 V2 V1
V2V1
V1
ASICs... THE COURSE 6.3 DC Input 7
Transmission line termination
(a) Open-circuit or capacitive termination
(b) Parallel resistive termination
(c) Thévenin termination
(d) Series termination at the source
(e) Parallel termination using a voltage bias
(f) Parallel termination with a series capacitor
A switch input
(a) A pushbutton switch
connected to an input buffer
with a pull-up resistor
(b) As the switch bounces
several pulses may be
generated
We might have to debounce
this signal using an SR flip-flop
or small state machine
VDD
TX line CinV1
(a)
Z0
R0
(b)
R2
(c)
R1
≈ 100 ?≈100 ? ≈ 100 ?≈ 100?
(d)
≈100?R1 R0
(e)
≈ 100?
+ VB R0
(f)
≈ 100 ?
C1≈ 50 ? ≈ 100 ? ≈ 100 ?≈ 100pF
≈ 100 ?
≈ 300 ?Z0
Z0 Z0
V2 Z0
Z0
(a)
I2I/OpadI1
VDD 5–50k ?
≈10pF t
5V
0V
Vi1
(b)
Switch closes,bounces, andcloses again.
t1
t2 t3
t4
t5
RPU
Cin 1.4Vinputbuffer Vi 2
Vi1 Vi2
8 SECTION 6 PROGRAMMABLE ASIC I/O CELLS ASICS... THE COURSE
DC input
(a) A Schmitt-trigger inverter ? lower switching threshold ? upper switching threshold ?
difference between thresholds is the hysteresis
(b) A noisy input signal
(c) Output from an inverter with no hysteresis
(d) Hysteresis helps prevent glitches
(e) A typical FPGA input buffer with a hysteresis of 200mV and a threshold of 1.4V
t2V
2.5 V
glitch
(b)
(c)
(d)0V
Vout
2.5V
Vin
5.0V
0V 5V
Vin Vout 3V5V
0VVout
Vout(a) (e)
OUT
0V2.5V
5.0V
0V 5V
I/O pad IN
1.4V
≈ 200mVhysteresis
t
t
(no hysteresis)
Vin
Vout Vin
Vin
Vout
ASICs... THE COURSE 6.3 DC Input 9
6.3.1 Noise Margins
Noise margins
(a) Transfer characteristics of a CMOS inverter with the lowest switching threshold
(b) The highest switching threshold
(c) A graphical representation of CMOS logic thresholds
(d) Logic thresholds at the inputs and outputs of a logic gate or an ASIC
(e) The switching thresholds viewed as a plug and socket
(f) CMOS plugs fit CMOS sockets and the clearances are the noise margins
0V
V2
V1
5V
5V
slope=–1
VILmax =1V 0V
V2
V1
5V
5VVIHmin= 3.5V
V1 V2
socket
VOLmaxVOHmin
VIHmin
VILmax bad
VDD
VSS
Vout ishere forlogic '1'
Vout ishere forlogic '0'
Vin is herefor logic '1'
Vin is herefor logic '0'
VNMH =1V
VNML=0.5V
noise
CMOS CMOS
plug
CMOS CMOS
CMOS 4.5V
0.5V1.0V3.5V CMOS
Vin
(a) (c)(b)
(d) (f)(e)
5.0V
0.0V
Voutinputbuffer/inverter outputbuffer
logicinputs outputs
slope=–1
10 SECTION 6 PROGRAMMABLE ASIC I/O CELLS ASICS... THE COURSE
TTL and CMOS logic thresholds
(a) TTL logic thresholds
(b) Typical CMOS logic thresholds
(c) A TTL plug will not fit in a CMOS socket
(d) Raising VOHmin solves the problem
CMOSTTL(a) (c)
CMOSTTLTTL
0.8V2.0V 2.7V0.4VTTL 0.0V
5.0V TTL/CMOS
0.8V2.0V 3.86V0.4VTTL/CMOS0.0V
5.0V
(d)
CMOS 4.5V
0.5V1.0V3.5V CMOS
(b)
5.0V
0.0V
ASICs... THE COURSE 6.3 DC Input 11
6.3.2 Mixed-Voltage Systems
FPGA logic thresholds
I/O options Input levels Output levels (high current) Output levels (low current)
XC3000 TTL 2.0 0.8 3.86 –4.0 0.40 4.0
CMOS 3.85 0.9 3.86 –4.0 0.40 4.0
XC3000L 2.0 0.8 2.40 –4.0 0.40 4.0 2.80 –0.1 0.2 0.1
XC4000 2.0 0.8 2.40 –4.0 0.40 12.0
XC4000H TTL TTL 2.0 0.8 2.40 –4.0 0.50 24.0
CMOS CMOS 3.85 0.9 4.00 –1.0 0.50 24.0
XC8100 TTL R 2.0 0.8 3.86 –4.0 0.50 24.0
CMOS C 3.85 0.9 3.86 –4.0 0.40 4.0
ACT 2/3 2.0 0.8 2.4 –8.0 0.50 12.0 3.84 –4.0 0.33 6.0
FLEX10k 3V/5V 2.0 0.8 2.4 –4.0 0.45 12.0
Mixed-voltage systems
(a) TTL levels
(b) Low-voltage CMOS
levels ? JEDEC 8 ?
3.3±0.3V
(c) Mixed-voltage ASIC ?
5V-tolerant I/O ? VDDint
and VDDI/O
(d) A problem when con-
necting two chips with
different supply
voltages—caused by the
input clamp diodes
0.8V2.0V
(a)
TTL
0.8V2.0V 2.7V0.4VTTL 0.0V
5.0V CMOS3V 2.4V
CMOS3V(b)
3.3V0.4V
0.0V
VDDIO VDDINT
core I/O(c)
3.0VM1
M2 Rin
D1
D2
M3
M4OUT1 IN2
D3
D4
'0' I2
VDD1 VDD 2CHIP1powersCHIP2
CHIP1 CHIP2
+5.5V +
(d) ≈ 1k?
12 SECTION 6 PROGRAMMABLE ASIC I/O CELLS ASICS... THE COURSE
6.4 AC Input
6.4.1 Metastability
Keywords and concepts: input bus ? sampled data ? clock frequency of 100kHz ? FPGA ? sys-
tem clock ? 10MHz ? Data should be at the flip-flop input at least the flip-flop setup time before
the clock edge. Unfortunately there is no way to guarantee this; the data clock and the system
clock are completely independent
Metastability
(a) Data coming from one clocked
system is an asynchronous input
to another
(b) A flip-flop (or latch, a sampler)
has a very narrow decision window
bounded by the setup and hold
times to resolve the input
If the data input changes inside the
decision window (a setup or hold-
time violation) the output may be
metastable—neither '1' or '0'—an
upset
(a)
tr
D1CLKQ1
setup and hold window(limits of decision window)
Q2
metastable outputD2
decisionwindow
tpd tsu2
(b)
D1 Q1
CLK
Q2CLI/Opad
tr tpd tsu2tsu 1
D2
CLK2
asynchronousinput
fclkfdata
50%
ASICs... THE COURSE 6.4 AC Input 13
The mean time between upsets (MTBU) or MTBF is
where fclock is the clock frequency and fdata is the data frequency
A synchronizer is built from two flip-flops in cascade, and greatly reduces the effective val-
ues of τc and T0 over a single flip-flop. The penalty is an extra clock cycle of latency.
Metastability parameters for FPGA flip-flops (not guaranteed by the vendors)
FPGA T0/s τc/s
Actel ACT 1 1.0E–09 2.17E–10
Xilinx XC3020-70 1.5E–10 2.71E–10
QuickLogic QL12x16-0 2.94E–11 2.91E–10
QuickLogic QL12x16-1 8.38E–11 2.09E–10
QuickLogic QL12x16-2 1.23E–10 1.85E–10
Altera MAX 7000 2.98E–17 2.00E–10
Altera FLEX 8000 1.01E–13 7.89E–11
1 exp tr/τc
MTBU = –––––––––––––– = ––––––––––––––
pfclockfdata fclock fdata
14 SECTION 6 PROGRAMMABLE ASIC I/O CELLS ASICS... THE COURSE
Mean time between failure (MTBF) as a function of resolution time
The data is from FPGA vendors’ data books for a single flip-flop with clock frequency of
10MHz and a data input frequency of 1MHz
1012
2 3 4 5
QuickLogic pASIC 1-0QuickLogic pASIC 1-1
QuickLogic pASIC 1-2Actel ACT 1
Xilinx XC3020–70
resolutiontime, tr /ns
MTBF/s
fclock =10MHzfdata =1MHz
108
104
(3 years)
100
ASICs... THE COURSE 6.5 Clock Input 15
6.5 Clock Input
Clock input
(a) Timing model (Xilinx XC4005-6)
(b) A simplified view of clock distribution ? clock skew ? clock latency
(c) Timing diagram
(Xilinx eliminates the variable internal delay tPG, by specifying a pin-to-pin setup time,
tPSUFmin=2ns)
(a)
clock-buffer cell
(c)
skew
CLKi
CLKn
(b)
CLK
tskewtPG
tPSUF
? = variable routing delay
pin-to-pinsetup time
latency
tskew
tPGmax =8ns
I/Opad
CL
Dn tPICK = 7ns tPSUFmin =2ns
CLK
Di QitPICK =7ns
CLKi?
Dn QntPICK =7ns
CLKn?
I/Opad
I/Ocell I/Ocell
tPG
tPSUF
50%tPG
CLKn
CLKit
skew
CLK
I/O cell
CLB
clockspine
16 SECTION 6 PROGRAMMABLE ASIC I/O CELLS ASICS... THE COURSE
6.5.1 Registered Input
Programmable input delay
(a) Pin-to-pin timing model (XC4005-6) with pin-to-pin timing parameters
(b) Timing diagrams with and without programmable delay
Notice tPSUFmin = 2 ns ≠ tPICK – tPGmax = –1 ns
Registered output
(a) Timing model with
values for an XC4005-6
programmed with the
fast slew-rate option
(b) Timing diagram
(b)(a)
D1D Q1
CLK
tPHF=5.5ns (tCKI =0ns)pin-to-pinhold time
CLK1TD1
pin-to-pinsetup timetPSUF
=2nswithoutdelaywith
delay tPSU=21ns tPH=0ns
CLKCLK1
D1D=D1(withoutdelay) tCKI (zero)tPG
D1(with delay) tPHF
tPSUF
tPH (zero)tPSU
internal hold time
tPG (variable)T = programmable delay
I/Opad
(b)(a)
Q1
CLKtPG (variable)
tOKPOF=7.5ns
CLK1D1
CLKCLK1
Q1 tPG
tICKOF tOKPOF
tICKOF =15.5ns
clockbuffer I/O pad
IOB
ASICs... THE COURSE 6.6 Power Input 17
6.6 Power Input
6.6.1 Power Dissipation
6.6.2 Power-On Reset
Thermal characteristics of ASIC packages
Package Pin count Max. power P
max/W
θJA /°CW–1
(still air)
θJA /°CW–1
(still air)
CPGA 84 33 32–38
CQFP 84 40
CQFP 172 25
VQFP 80 68
Key concepts: Power-on reset sequence ? Xilinx FPGAs configure all flip-flops (in either the
CLBs or IOBs) as either SET or RESET ? after chip programming is complete, the global
SET/RESET signal forces all flip-flops on the chip to a known state ? this may determine the ini-
tial state of a state machine, for example
18 SECTION 6 PROGRAMMABLE ASIC I/O CELLS ASICS... THE COURSE
6.7 Xilinx I/O Block
The Xilinx XC4000 family IOB (input/output block). (Source: Xilinx.)
Q
I/Opad
slewrate passivepull-down
D
QD
delay
outputbuffer
inputbuffer
flip-flop orlatch input clock
outputclock
I1
I2
OE
OUT
passivepull-upM M M
MMM
M
M
M M
OK
IKM
three-state
T
flip-flop orlatch
R1
M1
M2 R2
OB
IB
FFO
FFI
IO
TS D1
D2
VDD
R3
= programmable MUX= SRAM cellM
≈100 kohm
≈100 ohm
≈100 kohm
M
ASICs... THE COURSE 6.7 Xilinx I/O Block 19
The Xilinx LCA (Logic Cell Array) timing model (XC5210-6). (Source: Xilinx.)
O1
O2
I3
clock tooutput combinationallogic setup
IOB2 clock to output
output
IOB3
IOB4
clock tooutput
CLB3CLB2CLB1
tCKO tILO tICK tOPtCKO
tOKPO
Q
CLK3
D
QCLK4 D
DQ
tDICKsetup
I/Opad
0.8ns 5.6ns 2.3ns 5.8ns 4.6ns (fast)9.5ns (slow)
10.1ns (fast)14.9ns (slow)
CL? ? ??
?
?
IKinternalclockI2 global clockbuffer
5.8ns
input (fast), tPIDF =5.7ns
tBUFG, global buffer delay=9.4 ns
? = variable routing delay
? ?
?
CLK
I1
tPIDinput (slow)
11.4ns IOB1
CLK2
tPSUpin-to-pinsetup
8.5 ns CL
CL = combinational logic
20 SECTION 6 PROGRAMMABLE ASIC I/O CELLS ASICS... THE COURSE
6.7.1 Boundary Scan
6.8 Other I/O Cells
Key concepts: IEEE boundary-scan standard 1149.1 ? Many FPGAs contain a standard
boundary-scan test logic structure with a four-pin interface ? in-system programming (ISP)
A simplified block diagram of the Altera
I/O Control Block (IOC) used in the
MAX 5000 and MAX 7000 series
The I/O pin feedback allows the I/O
pad to be isolated from the macrocell
It is thus possible to use a LAB without
using up an I/O pad (as you often
have to do using a PLD such as a
22V10)
The PIA is the chipwide interconnect
A simplified block diagram of the Altera
I/O Element (IOE), used in the FLEX
8000 and 10k series
The MAX 9000 IOC (I/O Cell) is similar
The FastTrack Interconnect bus is the
chipwide interconnect
The Peripheral Control Bus (PCB) is
used for control signals common to
each IOE
I/Opadoutput enable
fast input to macrocell (7000E only)
Logic Array Block(LAB)
I/O ControlBlock (IOC)ProgrammableInterconnect Array (PIA)
6–12 IOCsper LAB
I/O pinfeedback
FastTrack Interconnect
output enable
3-statebuffer
I/OpadD Q
CLK
CLRN
M
EN
data in
slew-ratecontrol
PeripheralControl Bus (PCB)
B1 IOFF1
= programmable MUX= programmable memory
ASICs... THE COURSE 6.9 Summary 21
6.9 Summary
Key concepts:
Outputs can typically source or sink 5–10mA continuously into a DC load
Outputs can typically source or sink 50–200mA transiently into an AC load
Input buffers can be CMOS (threshold at 0.5VDD) or TTL (1.4V)
Input buffers normally have a small hysteresis (100–200mV)
CMOS inputs must never be left floating
Clamp diodes to GND and VDD are present on every pin
Inputs and outputs can be registered or direct
I/O registers can be in the I/O cell or in the core
Metastability is a problem when working with asynchronous inputs
22 SECTION 6 PROGRAMMABLE ASIC I/O CELLS ASICS... THE COURSE
