ASICs...THE COURSE (1 WEEK)
1
PROGRAMMABLE
ASIC DESIGN
SOFTWARE
8.1 Design Systems
Key concepts: There are five components of a programmable ASIC or FPGA :
(1) the programming technology
(2) the basic logic cell
(3) the I/O cell
(4) the interconnect
(5) the design software that allows you to program the ASIC
The design software is much more closely tied to the FPGA architecture than is the case for
other types of ASICs
Keywords: design kits ? original equipment manufacturer (OEM) ? generic cell library ? hard-
ware description languages (HDLs) ? ABEL (pronounced “able”) ? CUPL (“cupple”) ? PALASM
(“pal-azzam”) ? VHDL ? Verilog ? logic simulator ? back-annotation ? postlayout timing
information ? postlayout netlist (also called a back-annotated netlist) ? postlayout timing simu-
lation ? timing-analysis ? timing constraint ? timing violation ? forward-annotation
8
2 SECTION 8 PROGRAMMABLE ASIC DESIGN SOFTWARE ASICS... THE COURSE
8.1.1 Xilinx
The Xilinx FPGA design flow
(The program names and file names change with the newer Xilinx Alliance and Foundation
tools, but the information flow is identical.)
.LCAnetlist
xmake partition logicinto CLBs
.BITfile
makebits createprogrammingfile
.XNFnetlist
ppr/apr place androuteback-annotated
netlist with delays
netlist withoutdelays.XNFnetlist
prelayoutsimulation design entrystart
...toxnf
postlayoutsimulation
1ns
netlistwith unitdelays
Xilinxsoftware
S01
m2_1 Xilinx celllibrary
to FPGA or PROM
10011000...
1.12 ns
14 2 3
9
5 6 7 8
ASICs... THE COURSE 8.1 Design Systems 3
8.1.2 Actel
File types used by Actel design software (an example—these change often)
ADL Main design netlist
IPF Partial or complete pin assignment for the design
CRT Net criticality
VALIDATED Audit information
COB List of macros removed from design
VLD Information, warning, and error messages
PIN Complete pin assignment for the design
DFR Information about routability and I/O assignment quality
LOC Placement of non-I/O macros, pin swapping, and freeway assignment
PLI Feedback from placement step
SEG Assignment of horizontal routing segments
STF Back-annotation timing
RTI Feedback from routing step
FUS Fuse coordinates (column-track, row-track)
DEL Delays for input pins, nets, and I/O modules
AVI Fuse programming times and currents for last chip programmed
4 SECTION 8 PROGRAMMABLE ASIC DESIGN SOFTWARE ASICS... THE COURSE
FPGA state-machine language (an example of “third-party” tools)
LOG/iC state-machine language PALASM version
*IDENTIFICATION
sequence detector
LOG/iC code
*X-NAMES
X; !input
*Y-NAMES
D; !output, D = 1 when three 1's
appear on X
*FLOW-TABLE
;State, X input, Y output, next
state
S1, X1, Y0, F2;
S1, X0, Y0, F1;
S2, X1, Y0, F3;
S2, X0, Y0, F1;
S3, X1, Y0, F4;
S3, X0, Y0, F1;
S4, X1, Y1, F4;
S4, X0, Y0, F1;
*STATE-ASSIGNMENT
BINARY;
*RUN-CONTROL
PROGFORMAT = P-EQUATIONS;
*END
TITLE sequence detector
CHIP MEALY USER
CLK Z QQ2 QQ1 X
EQUATIONS
Z = X * QQ2 * QQ1
QQ2 := X * QQ1 + X * QQ2
QQ1 := X * QQ2 + X * /QQ1
ASICs... THE COURSE 8.2 Logic Synthesis 5
8.1.3 Altera
8.2 Logic Synthesis
It is easier to write A = B + C than to draw an FPGA schematic for a 32-bit adder at the gate
level
Altera uses a self-contained design system, MAX+plus (as well as an interface to EDIF for
third-party schematic entry or logic synthesis).
? The interconnect scheme in Altera complex PLDs is nearly deterministic, simplifying the
physical-design software as well as eliminating the need for back-annotation and a postlayout
simulation.
? As Altera FPGAs become larger and more complex, some cases require signals to make
more than one pass through the routing structures or travel large distances across the Altera
FastTrack interconnect. It is possible to tell if this will be the case only by trying to place and
route an Altera device.
Key concepts, facts, and terms: logic synthesis ? logic minimization ? mapping ? fine-grain
architecture ? coarse-grain architecture ? vendor independence ? Synplicity ? Synopsys FPGA
Express ? FPGA Compiler ? Design Compiler ? Exemplar ? X-BLOX ? LPM ? IP cores
6 SECTION 8 PROGRAMMABLE ASIC DESIGN SOFTWARE ASICS... THE COURSE
8.2.1 FPGA Synthesis
The VHDL code for a sequence detector
entity detector is port (X, CLK: in BIT; Z : out BIT); end;
architecture behave of detector is
type states is (S1, S2, S3, S4);
signal current, next: states;
begin
combinational: process begin
case current is
when S1 =>
if X = '1' then Z <= '0'; next <= S3; else Z <= '0'; next <=
S1; end if;
when S2 =>
if X = '1' then Z <= '0'; next <= S2; else Z <= '0'; next <=
S1; end if;
when S3 =>
if X = '1' then Z <= '0'; next <= S2; else Z <= '0'; next <=
S1; end if;
when S4 =>
if X = '1' then Z <= '1'; next <= S4; else Z <= '0'; next <=
S1; end if
end case;
end process
sequential: process begin
wait until CLK'event and CLK = '1'; current <= next ;
end process;
end behave;
A Synopsys script
/design checking/
search_path = .
/use the TI cell libraries/
link_library = tpc10.db
target_library = tpc10.db
symbol_library = tpc10.sdb
read -f vhdl detector.vhd
current_design = detector
write -n -f db -hierarchy -0
detector.db
check_design > detector.rpt
report_design > detector.rpt
/optimize for area/
max_area 0.0
compile
write -h -f db -o detector_opt.db
report -area -cell -timing >
detector.rpt
free -all
/write EDIF netlist/
write -h -f edif -0
exit
ASICs... THE COURSE 8.3 The Halfgate ASIC 7
8.3 The Halfgate ASIC
8 SECTION 8 PROGRAMMABLE ASIC DESIGN SOFTWARE ASICS... THE COURSE
8.3.1 Xilinx
Design flow for the Xilinx implementation of the halfgate ASIC
Script (using Compass tools as an example) Design flow
# halfgate.xilinx.inp
shell setdef
path working xc4000d xblox cmosch000x
quit
asic
open [v]halfgate
synthesize
save [nls]halfgate_p
quit
fpga
set tag xc4000
set opt area
optimize [nls]halfgate_p
quit
qtv
open [nls]halfgate_p
trace critical
print trace [txt]halfgate_p
quit
shell vuterm
exec xnfmerge -p 4003PC84 halfgate_p >
/dev/null
exec xnfprep halfgate_p > /dev/null
exec ppr halfgate_p > /dev/null
exec makebits -w halfgate_p > /dev/null
exec lca2xnf -g -v halfgate_p
halfgate_b > /dev/null
quit
manager notice
utility netlist
open [xnf]halfgate_b
save [nls]halfgate_b
save [edf]halfgate_b
quit
qtv
open [nls]halfgate_b
trace critical
print trace [txt]halfgate_b
quit
3
4
5
1
2
XSYM2 XSYM1myInput myOutput
_IN_myInput OBUFIBUF 2.8ns 11.6ns
1nsmyInput myOutput
_IN_myInput_IBUF myOutput_OBUFmyInput myOutput
_IN_myInput OBUFIBUF
myInput myOutput
myOutput = ~myInput
4
3
2
1
5
ASICs... THE COURSE 8.3 The Halfgate ASIC 9
The Xilinx files for the halfgate ASIC
Verilog file (halfgate.v)
Preroute XNF file (halfgate_p.xnf)
module halfgate(myInput, myOutput); input myInput; output
myOutput; wire myOutput;
assign myOutput = ~myInput;
endmodule
LCANET, 5
USER, FPGA-Optimizer, 4.1,
Date:960710 , Option: Area
PROG, FPGA-Optimizer, 4.1,
"Lib=4000"
PART, 4010PG191
PWR, 0, GND
PWR, 1, VCC
SYM,_IN_myInput_IBUF,IBUF,LIB
VER=2.0.0
PIN, I, I, myInput,
PIN, O, O, _IN_myInput,
END
EXT, myInput, I,
SYM,
myOutput_obuf,OBUF,LIBVER=
2.0.0,
PIN, I, I, _IN_myInput,,
INV
PIN, O, O, myOutput,
END
EXT, myOutput, O,
EOF
10 SECTION 8 PROGRAMMABLE ASIC DESIGN SOFTWARE ASICS... THE COURSE
LCA file (halfgate_p.lca)
Postroute XNF file (halfgate_b.xnf)
;: halfgate_p.lca (4003PC84-
4), makebits 5.2.0, Tue Jul 16
20:09:43 1996
Version 2
Design 4003PC84 4 0
Speed -4
Addnet PAD_myInput PAD61.I2
PAD1.O
Netdelay PAD_myInput PAD1.O
3.1
Program PAD_myInput {65G521}
{65G287} {65G50} {63G50}
{52G50} {45G50}
NProgram PAD_myInput
col.B.long.3:PAD1.O
col.B.long.3:row.G.local.1
col.B.long.3:row.M.local.5-s
MB.
40.1.14 MB.40.1.35
row.M.local.5:PAD61.I2
Editblk PAD61
Base IO
Config INFF: I1: I2:I O:
OUT: PAD: TRI:
Endblk
Editblk PAD1
Base IO
Config INFF: I1: I2: O:
OUT:O:NOT PAD: TRI:
Endblk
Nameblk PAD61 myInput
Nameblk PAD1 myOutput
Intnet myOutput PAD
myOutput
Intnet myInput PAD myInput
System FGG 0 VERS 2 !
System FGG 1 GD0 0 !
LCANET, 4
PROG, LCA2XNF, 5.2.0, "COMMAND
= -g -v halfgate_p halfgate_b
TIME = Tue Jul 16 21:53:31
1996"
PART, 4003PC84-4
SYM, XSYM1, OBUF, SLOW
PIN, O, O, myOutput, 3.0
PIN, I, I, _IN_myInput,
8.6, INV
END
SYM, XSYM2, IBUF
PIN, O, O, _IN_myInput,
2.8
PIN, I, I, myInput
END
EXT, myOutput, O, 10
EXT, myInput, I, 29
EOF
ASICs... THE COURSE 8.3 The Halfgate ASIC 11
8.3.2 Actel
The Actel files for the halfgate ASIC
ADL file STF file
; HEADER
; FILEID ADL ./halfgate_io.adl
85e8053b
; CHECKSUM 85e8053b
; PROGRAM certify
; VERSION 23/1
; ALSMAJORREV 2
; ALSMINORREV 3
; ALSPATCHREV .1
; NODEID 72705192
; VAR FAMILY 1400
; ENDHEADER
DEF halfgate_io; myInput,
myOutput.
USE ADLIB:INBUF; INBUF_2.
USE ADLIB:OUTBUF; OUTBUF_3.
USE ADLIB:INV; u2.
NET DEF_NET_8; u2:A, INBUF_2:Y.
NET DEF_NET_9; myInput,
INBUF_2:PAD.
NET DEF_NET_11; OUTBUF_3:D, u2:Y.
NET DEF_NET_12; myOutput,
OUTBUF_3:PAD.
END.
; HEADER
; FILEID STF ./halfgate_io.stf
c96ef4d8
... lines omitted ... (126 lines
total)
DEF halfgate_io.
USE ; INBUF_2/U0;
TPADH:'11:26:37',
TPADL:'13:30:41',
TPADE:'12:29:41',
TPADD:'20:48:70',
TYH:'8:20:27',
TYL:'12:28:39'.
PIN u2:A;
RDEL:'13:31:42',
FDEL:'11:26:37'.
USE ; OUTBUF_3/U0;
TPADH:'11:26:37',
TPADL:'13:30:41',
TPADE:'12:29:41',
TPADD:'20:48:70',
TYH:'8:20:27',
TYL:'12:28:39'.
PIN OUTBUF_3/U0:D;
RDEL:'14:32:45',
FDEL:'11:26:37'.
END.
12 SECTION 8 PROGRAMMABLE ASIC DESIGN SOFTWARE ASICS... THE COURSE
8.3.3 Altera
EDIF netlist in Altera format for the halfgate ASIC
(edif halfgate_p
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap
(keywordLevel 0))
(status
(written
(timeStamp 1996 7
10 23 55 8)
(program "COMPASS
Design Automation --
EDIF Interface"
(version "v9r1.2
last updated 26-Mar-
96"))
(author
"mikes")))
(library flex8kd
(edifLevel 0)
(technology
(numberDefinition
)
(simulationInfo
(logicValue H)
(logicValue
L)))
(cell not
(cellType
GENERIC)
(view
COMPASS_mde_view
(viewType
NETLIST)
(interface
(port IN
(direction
INPUT))
(port OUT
(direction
OUTPUT))
(designator
"@@Label")))))
(library working
(edifLevel 0)
(technology
(numberDefinition
)
(simulationInfo
(logicValue H)
(logicValue
L)))
(cell halfgate_p
(cellType
GENERIC)
(view
COMPASS_nls_view
(viewType
NETLIST)
(interface
(port myInput
(direction
INPUT))
(port myOutput
(direction
OUTPUT))
(designator
"@@Label"))
(contents
(instance B1_i1
(viewRef
COMPASS_mde_view
(cellRef not
(libraryRef
flex8kd))))
(net myInput
(joined
(portRef
myInput)
(portRef IN
(instanceRef
B1_i1))))
(net myOutput
(joined
(portRef
myOutput)
(portRef OUT
(instanceRef
B1_i1))))
(net VDD
(joined )
(property
global
(string
"vcc")))
(net VSS
(joined )
(property
global
(string
"gnd")))))))
(design halfgate_p
(cellRef halfgate_p
(libraryRef
working))))
ASICs... THE COURSE 8.3 The Halfgate ASIC 13
The structural postlayout files generated by the Altera MAX+plus software:
// halfgate_p (EPM7032LC44) MAX+plus II Version 5.1 RC6 10/03/94
// Wed Jul 17 04:07:10 1996
`timescale 100 ps / 100 ps
module TRI_halfgate_p( IN, OE, OUT ); input IN; input OE; output OUT;
bufif1 ( OUT, IN, OE );
specify
specparam TTRI = 40; specparam TTXZ = 60; specparam TTZX = 60;
(IN => OUT) = (TTRI,TTRI);
(OE => OUT) = (0,0, TTXZ, TTZX, TTXZ, TTZX);
endspecify
endmodule
module halfgate_p (myInput, myOutput);
input myInput; output myOutput; supply0 gnd; supply1 vcc;
wire B1_i1, myInput, myOutput, N_8, N_10, N_11, N_12, N_14;
TRI_halfgate_p tri_2 ( .OUT(myOutput), .IN(N_8), .OE(vcc) );
TRANSPORT transport_3 ( N_8, N_8_A );
defparam transport_3.DELAY = 10;
and delay_3 ( N_8_A, B1_i1 );
Report for the halfgate ASIC fitted to an Altera MAX 7000 complex PLD
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
43 - - INPUT 0 0 0 0 0 0 1 myInput
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
41 17 B OUTPUT t 0 0 0 1 0 0 0 myOutput
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
+- LC17 myOutput
|
LC | | A B | Name
Pin
43 -> * | - * | myInput
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
14 SECTION 8 PROGRAMMABLE ASIC DESIGN SOFTWARE ASICS... THE COURSE
xor xor2_4 ( B1_i1, N_10, N_14 );
or or1_5 ( N_10, N_11 );
TRANSPORT transport_6 ( N_11, N_11_A );
defparam transport_6.DELAY = 60;
and and1_6 ( N_11_A, N_12 );
TRANSPORT transport_7 ( N_12, N_12_A );
defparam transport_7.DELAY = 40;
not not_7 ( N_12_A, myInput );
TRANSPORT transport_8 ( N_14, N_14_A );
defparam transport_8.DELAY = 60;
and and1_8 ( N_14_A, gnd );
endmodule
// MAX+plus II Version 5.1 RC6 10/03/94 Wed Jul 17 04:07:10 1996
`timescale 100 ps / 100 ps
module TRANSPORT( OUT, IN ); input IN; output OUT; reg OUTR;
wire OUT = OUTR; parameter DELAY = 0;
`ifdef ZeroDelaySim
always @IN OUTR <= IN;
`else
always @IN OUTR <= #DELAY IN;
`endif
`ifdef Silos
initial #0 OUTR = IN;
`endif
endmodule
ASICs... THE COURSE 8.3 The Halfgate ASIC 15
The VHDL version of the postlayout Altera MAX 7000 schematic for the halfgate ASIC
macrocell
n_delay_3 n_8
B1_i1
n_10
n_14 n_xor_4
n_or_5n_11n_and_6
'1'
n_12
n_and_8gnd
n_12
LAB B Logic Cell 17
ProgrammableInterconnect Array (PIA)
Pin41I/O pad
OE output enable
I/O ControlBlock (IOC)
Pin43I/O pad
n_tri_halfgate_pvcc
n_not_7
myOutput
myInput
I/O ControlBlock (IOC)
unused
16 SECTION 8 PROGRAMMABLE ASIC DESIGN SOFTWARE ASICS... THE COURSE
8.3.4 Comparison
8.4 Summary
? Xilinx XC4000, a nondeterministic coarse-grained FPGA
? Actel ACT 3, a nondeterministic fine-grained FPGA
? Altera MAX 7000, a deterministic complex PLD
The differences:
1. The Xilinx LCA architecture does not permit an accurate timing analysis until after place and
route. This is because of the coarse-grained nondeterministic architecture.
2. The Actel ACT architecture is nondeterministic, but the fine-grained structure allows fairly
accurate preroute timing prediction.
3. The Altera MAX CPLD requires logic to be fitted to the product steering and programmable
array logic. The Altera MAX 7000 has an almost deterministic architecture, which allows accu-
rate preroute timing.
Key concepts:
? FPGA design flow: design entry, simulation, physical design, and programming
? Schematic entry, hardware design languages, logic synthesis
? PALASM as a common low-level hardware description
? EDIF, Verilog, and VHDL as vendor-independent netlist standards
