Dec,10,2003
6.12J / 3.155J Microelectronic processing
Patterning materials at the nanoscale
Outline
1,Introduction - How small would you like to go?… can you go?
2,Optical and other lithography
3,Subtractive and additive patterning
4,More exotic patterning methods:
Interference,
(Imprint,)
Block copolymers
Self assembly
(Building on last year’s notes of Caroline Ross)
Dec,10,2003
6.12J / 3.155J Microelectronic processing
How small would you like to go? …and can you go?
with semiconductors?…with lithography?
Semiconductor scaling drivers:
w Speed of light in global interconnects,v μ c/√k
w Increased information density
w Increased logic speed
w Economies of scale
Semiconductor scaling challenges:
w diffusion length control,statistics,especially for channel
w Thermal management,V
2
/R
Power density,Pentium,Pentium III,,Pentium III,Nuclear Reactor
w Dielectric breakdown field,V/d
w Interconnect cross-talk,delay,C?,t = L/C
w Information stability,k
B
T < CV
2
w Screening lengths (range of band bending,depletion regions)
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Four problems as size shrinks:
1,Drain,source
doping concentration
limited by thermodynamics
2,Physical tunneling
through gate oxide (I
off
< I
on
)
3,Statistical fluctuations
of doping,N
d
≈ 50/(10 nm)
3
4,Economic cost of Fab
How small can MOSFETs go?
Dec,10,2003
6.12J / 3.155J Microelectronic processing
International Technology Roadmap
for Semiconductors; 2002
N
d
≈ 50 in 10x10x10 nm
3
Dec,10,2003
6.12J / 3.155J Microelectronic processing
How small can you go
with semiconductors?…with lithography?
Lithography limitations:
w Fresnel and Fraunhoffer limitations
w Other light sources or particles?
w When the optical resolution exceeds physical resolution
w e-beam,secondary generation blurs lines
w Particle damage
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Fresnel (near field diffraction),l < g < W
2
/ l
Minimum resolved feature = (lg)
1/2
Can Lithography get you there?
Proximity lithography
For g = 20 microns,l = 436 nm => 3 microns
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Dec,10,2003
6.12J / 3.155J Microelectronic processing
Fraunhoffer (far field diffraction):
Minimum resolved feature = lf/d (no limit on lens diameter,d)
Can Projection lithography get you there?
For f ≈ d,l = 436 nm => 0.4 microns
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Dec,10,2003
6.12J / 3.155J Microelectronic processing
l =
hc
E
l =
h
mv
=
1.23
E(eV )
(?)
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Semiconductor scaling challenges:
w diffusion length control,statistics,especially for channel
w Thermal management,V
2
/R
Power den.,Pentium,Pentium III,,Pentium III,Nuclear Reactor
w Dielectric breakdown field,V/d
w Interconnect cross-talk,delay,C?,t = L/C
w Information stability,k
B
T > CV
2
w Screening lengths
(range of band bending,depletion regions)
Recall semiconductor physical limits
Electron
concentration
If not semiconductors,then what other information technologies? …
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Size limitations on other information technologies
Schematic of longitudinal
recording medium
Magnetic disk
storage media
Each bit (currently about 0.5 x 0.08 x 0.03 μm - ≈ 10 Gb/in
2
)
Consists of 1000 grains; noise μ N
-1/2
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Dec,10,2003
6.12J / 3.155J Microelectronic processing
Ideal medium,single bit = 1 single-domain particle
Patterned
storage media
100 nm
‘1’ ‘0’ ‘1’
Each bit (occupying about 100 x 100 nm,≈ 100 Gb/in
2
)
consists of 1000 grains; media noise largely eliminated
200 nm
Each pillar is
single-domain,
can be
magnetized
‘up’ or ‘down’
Dec,10,2003
6.12J / 3.155J Microelectronic processing
How small must particle be to be in single-domain state?
Exchange length,l,over which the magnetization is approximately parallel
l = (A/M
s
2
)
1/2
(20 nm for Ni)
A = exchange constant (~10
-6
erg/cm); M
s
= saturation magnetization
Single domain
nm scale
d < l
Non-uniform
d > l
Domain wall width,d ≈ p(A/K
u
)
1/2
,
K
u
= anisotropy.
Multi-domain
micron scale
d >> l,d
V
particle
￡
25k
B
T
K
u
SD particles
thermally decouple,
Superparamagnetism
(Semiconductor memory problem,CV
2
< k
B
T )
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Spin-based devices
Metal length scales shorter
e
-
e
-
e
-
Mobile carrier
Scatters
from ion
r < r < rSpin-dependent
resistivity
x
M (x)
Spin memory
is lost over x,t
e
-
M (x)
x
e
-
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Unlike semiconductor devices,
performance of
spin-based devices
improves as thickness decreases
because screening lengths
and spin diffusion lengths in metals << than in semiconductors.
Spintronics = spin (magnetism)-based electronic devices
Separator Device
non-mag metal => low-impedance
spin valve or spin switch
insulator => high-impedance
spin-tunnel junction
(Messervey and Tedrow,Phys,Rpts,238,174 (‘96);
Moodera et al,Phys,Rev,Lett,80,2941 (‘98))
The smaller the better
x
M (x)
Spin memory
is lost over x,t
e
-
Dec,10,2003
6.12J / 3.155J Microelectronic processing
So it is worth exploring the limits of
Nano-lithography,
nano-patterning,
self-assembly
not just for semiconductor devices
but for magnetics as well…
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Subtractive and additive patterning
Whichever lithography method is used,
structures are created by subtractive or additive patterning.
(c) remove magnetic material (d) remove template
substrate
(a) deposit magnetic material (b) define template on top
template
magnetic material
Subtractive patterning requires removal (etching) of the magnetic material.
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Additive patterning
(does not require etching of the magnetic material)
(a) deposit template (b) deposit magnetic (c) remove template (“lift-off”)
material on top of template
substrate
magnetic material
template
(b) electroplate to fill template (c) remove template
OR
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Pros and Cons of these two basic methods
Additive patterning is easier because it does not require etching of the magnetic
film,It is better for making tall structures.
However it is limited to film deposition methods that do not give good step
coverage over the mask:
Evaporation,produces tapered
structures due to shadowing
evaporative deposition
electrodeposition
sputtering (low-pressure,<0.1 mTorr)
Evaporation and electrodeposition limit choice of materials
Au
Electroplating,requires
conductive substrate
Dec,10,2003
6.12J / 3.155J Microelectronic processing
200 nm
Examples of Additive patterning
C,A,Ross,M.I.T.
100 nm
Evaporated pyramids…in template after liftoff
Electrodeposited Ni pillars
200 nm
Each pillar is
single-domain,
can be
magnetized
‘up’ or ‘down’
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Additive patterns with Electron-beam lithography
An electron beam ‘writes’ (exposes) resist,typically PMMA,This is
done in a dedicated e-beam writer,A scanning electron microscope
can be modified to perform this function.
Resolution depends on the beam diameter and production of
secondary electrons.
Since this is a serial writing process,it can be slow,The writing
speed depends on the beam current and resist sensitivity (which
govern the data rate) and the pixel size (resolution).
e.g,to write 1 cm
2
of 10 nm pixels,at 1000 A/cm
2
,100 electrons per pixel,if all
pixels are addressed:
converted SEM,100 kHz,takes > 1 month
commercial writer,100 MHz,takes 1 hr
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Co rings,
12 nm thick
Diameter:
150 nm – 1 mm
Ring width:
30 nm-200 nm
200 nm
200 nm
500 nm
200 nm
200 nm
200 nm
Electron-beam lithography
C,A,Ross
200 nm
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Examples of,lift-off” processing
Liftoff does not work for sputtering unless the
pressure is very low,because of step coverage.
Ion-beam sputtering @ 0.1 mTorr
Magnetron sputtering @ 3 mTorr
500 nm
500 nm
F.J,Casta?o
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Another additive patterning,Shadow-masking
For relatively coarse patterning,a mask can be placed in the deposition system
so that material selectively deposits on certain parts of the substrate,or smaller
Patterns of ~100 mm can be made.
collimated
source (e.g.
evaporation
cell)
shadow mask
structure
substrate
A relatively simple process,but the mask becomes coated and must be cleaned or replaced.
Structure with <100 nm wide features made
by an e-beam patterned shadow mask,Park
et al,J Appl Phys 81,4717,null(1997)
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6.12J / 3.155J Microelectronic processing
Triple-angle evaporation through shadow mask
(Lu,Moodera,Wang,and O’H,NIRT)
Top resist layer
a) First
evaporation,
b) Oxidation
Substrate
0°
c) Second
evaporation
+20°
First tunnel
junction
d) Third
evaporation
Second tunnel
junction
-20°
Large undercut is needed
in shadow mask
for evaporation of tunnel junctions
Suspended
resist
bridge
Island
Lead
Lead
Top view - island region
Resist Undercut Substrate
582 n m
60 n m
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Measurement of spin tunneling demands
junction resistance of 26 - 500 kW
Fe Al Fe
200 nm
Al
2
O
3
barrier
Fe Metal Fe
M
1
M
2
Double junction device
Enhanced magnetoresistance due to
co-tunneling in double-junction device
Junction area ≈ 80 ￥ 80 nm
(Junction resistance depends on oxide thickness and area)
Double junction device
(Lu,Moodera,Wang,and O’H,NIRT)
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Subtractive patterning (etch away)
…allows more flexibility in the types of films that are patterned.
Requires an etch step and most magnetic materials are notoriously hard to etch.
Chemical (wet) etching in acids,not suitable for very small structures
Reactive ion etching,most magnetic materials are resistant to removal
Ion milling (sputter etching),physical removal of material
using energetic ions,requiring a hard mask,This can cause damage to the edges of
the structures,Subtractive patterning works best for thinner films.
mask,e.g,W
Magnetic film
substrate
Ar+
disordered
region
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Examples of Subtractive patterning
Sputtered films etched into different shapes
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Dec,10,2003
6.12J / 3.155J Microelectronic processing
Making periodic nanoscale patterns
Resist layer (usually polymeric) is spin-coated on substrate,then baked.
Resist is sensitive to radiation,e.g,light,x-rays or electrons
Pattern is exposed in the resist layer using photons,electrons,etc.
Resist is developed to selectively remove the parts that have been exposed
(positive resist) or unexposed (negative resist),then baked.
exposure
positive resist
negative resist
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Some complications:
Reflective substrates can lead to poorly defined resist edges
after development,One solution is to incorporate an
antireflective coating which absorbs light between the
substrate and the resist.
Adhesion of resists is often poor,so the surface is often treated
with an adhesion promoter such as hexamethyldisilazane
(HMDS).
Multilevel resists (2 separate layers,with the top layer slightly
less sensitive) can be used to get a good undercut profile that
is advantageous for lift-off processing.
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Interference lithography
Interference lithography,Optical standing wave exposes a grating pattern into
resist layer,Can superpose gratings or fringe patterns.
Periods of l/2 are possible.
An antireflective layer is typically needed.
Types of patterns formed are strictly periodic,dots,pillars,or lines.
Mirror
Substrate
Laser
beam,
wave-
length l
Angle q
Dec,10,2003
6.12J / 3.155J Microelectronic processing
100 nm
200 nm
1000nm
PSV-elements
word lines
sense lines
500nm
300nm
word lines
sense lines
Examples of structures made by
Interference lithography (C.A,Ross)
ARC-insulator
PSV/W -wires
Dec,10,2003
6.12J / 3.155J Microelectronic processing
X-ray Lithography
Resembles contact printing optical lithography,but wavelength ≈ 0.4 nm to 4.5 nm
is used to reduce diffraction effects and scattering.
A membrane mask is made (typically using e-beam lithography).
The x-ray source can be an electron impact source (rotating anode) or a high-
brightness synchrotron.
Resists are similar to e-beam lithography.
100 nm wide line made by XRL
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Dec,10,2003
6.12J / 3.155J Microelectronic processing
Imprint Lithography
A hard ‘stamp’,(silica,SiN,or Si) is pressed into a resist layer,transferring
pattern pattern resist.
Or flexible stamp made of PMDS is used to transfer material onto a substrate,
similar to an ink stamp.
The stamp is made by another form of lithography.
pressure
stamp
resist
substrate
25 nm wide bars
made by imprint
lithography,Wu
et al,JVSTB 16
3825,null(1998)
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6.12J / 3.155J Microelectronic processing
Focussed Ion Beam (FIB) Patterning
Beams of energetic particles such as Ga+ can be used to pattern substrates directly
by milling away material,Like e-beam writing,this is a slow process.
There are other probe-based,direct-writing methods,
e.g,CVD-writing using a scanning probe microscope.
150 nm wide Fe pillars made
using CVD,Wirth et al,Phys
Rev B 57 R14028,null(1998)
250 nm islands defined in a film by a
FIB,Lohau et al,Appl Phys Lett 78
990,null(2001)
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Dec,10,2003
6.12J / 3.155J Microelectronic processing
Novel patterning processes for nanoscale devices
Perhaps less obvious:
Self assembly (“Bottom up”)
Block copolymers?
Wet chemical processes?
Carbon nono-tubes,rings?
Other organics
75% of NIRTs
Dec,10,2003
6.12J / 3.155J Microelectronic processing
29~50nm18~35nm
PFS spheres,
resistant to O
2
plasma
PS matrix:
removed by O
2
plasma
Block copolymer lithography
Block copolymers,two immiscible blocks,A and B.
Volume fraction of each component determines a range
of morphologies obtained on annealing;
periodicities of a few nm and higher.
These self-assembling systems are promising
nanolithography templates.
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6.12J / 3.155J Microelectronic processing
Self assembly,Block co-polymers
Gleiter,2000
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6.12J / 3.155J Microelectronic processing
Magnetic particles can be attached to end of nano-tube
Tunneling device?
SET
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Dec,10,2003
6.12J / 3.155J Microelectronic processing
“Bottom up”,Patterning Carbon Nanotubes,Rings
Francesco Stellacci (M.I.T.) with M,Prato,Trieste,Italy
Magnetic Nanotubes
Diamagnetic rings
Paramagnetic rings
NS
Fluid level
Glass cuvette
100 nm
Rings show ballistic conductivity
(spin coherence?)
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Biologically benign,but diamagnetic?
Francesco Stellacci
Hydrophobic/hydrophilic
p-bonded rings
self-assemble on gold
SH COOH
SH
MPA
C8
Courtesy of Francesco Stellacci
Dec,10,2003
6.12J / 3.155J Microelectronic processing
National Facilities
For researchers (industrial and academic) without access to lithography facilities,
the National Nano Users Network provides access to facilities at four sites in the
US,Cornell,Howard,Stanford,Penn State and UCSB.
www.nnun.org
“National Nanofabrication Users Network (NNUN) provides users with access
to some of the most sophisticated nanofabrication technologies in the world with
facilities open to all users from academia,government,and industry,The
combined staffs of the NNUN have extensive experience in all phases of
nanofabrication and its use in fields ranging from nanophysics to biology to
electronics,We have experts in micromechanics and biology to assist users in
translating their ideas into experimental reality,With the assistance of the
NNUN,users can often fabricate advanced nanostructures within weeks of initial
contact.” (NNUN website)
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Summary
Simplest patterning uses shadow-masking directly in a deposition system,
relatively large-scale structures.
Simplest processing using a resist layer is contact-printing,
requires a resist spinner,hotplates,developer,a bright lamp,and mask.
Projection optical lithography => smaller structures (~500 nm);
requires more complex equipment.
Most common method for sub-micron structures of arbitrary shape
is e-beam lithography,requires SEM or a dedicated e-beam writer.
NNUN has facilities available to the public,A wide variety of other specialized
lithography methods have been developed,each of which has its own advantages
and disadvantages,The nature of resist limits resist-based lithography to ~5 nm edge
roughness.
For features with dimensions of a few nm,other processes such as chemically-
synthesized nanoparticle formation may be appropriate.
Dec,10,2003
6.12J / 3.155J Microelectronic processing
References
S.A,Campbell,The science and engineering of microelectronic fabrication,
Oxford (1996)
J.D,Plummer,M.D,Deal and P.B,Griffin,Silicon VLSI Technology:
Fundamentals,Practice and Modeling,Prentice Hall,(2000)
S.K,Ghandhi,VLSI Fabrication principles,Wiley (1994)
S.M,Sze,VLSI Technology,McGraw-Hill (1988)
H.I,Smith,Submicron and nanometer-structures technology,Nanostructures
Press,Sudbury MA (1994)
C.A,Ross,“Patterned media”,Ann,Rev,Materials Research 31 203 (2001)
6.12J / 3.155J Microelectronic processing
Patterning materials at the nanoscale
Outline
1,Introduction - How small would you like to go?… can you go?
2,Optical and other lithography
3,Subtractive and additive patterning
4,More exotic patterning methods:
Interference,
(Imprint,)
Block copolymers
Self assembly
(Building on last year’s notes of Caroline Ross)
Dec,10,2003
6.12J / 3.155J Microelectronic processing
How small would you like to go? …and can you go?
with semiconductors?…with lithography?
Semiconductor scaling drivers:
w Speed of light in global interconnects,v μ c/√k
w Increased information density
w Increased logic speed
w Economies of scale
Semiconductor scaling challenges:
w diffusion length control,statistics,especially for channel
w Thermal management,V
2
/R
Power density,Pentium,Pentium III,,Pentium III,Nuclear Reactor
w Dielectric breakdown field,V/d
w Interconnect cross-talk,delay,C?,t = L/C
w Information stability,k
B
T < CV
2
w Screening lengths (range of band bending,depletion regions)
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Four problems as size shrinks:
1,Drain,source
doping concentration
limited by thermodynamics
2,Physical tunneling
through gate oxide (I
off
< I
on
)
3,Statistical fluctuations
of doping,N
d
≈ 50/(10 nm)
3
4,Economic cost of Fab
How small can MOSFETs go?
Dec,10,2003
6.12J / 3.155J Microelectronic processing
International Technology Roadmap
for Semiconductors; 2002
N
d
≈ 50 in 10x10x10 nm
3
Dec,10,2003
6.12J / 3.155J Microelectronic processing
How small can you go
with semiconductors?…with lithography?
Lithography limitations:
w Fresnel and Fraunhoffer limitations
w Other light sources or particles?
w When the optical resolution exceeds physical resolution
w e-beam,secondary generation blurs lines
w Particle damage
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Fresnel (near field diffraction),l < g < W
2
/ l
Minimum resolved feature = (lg)
1/2
Can Lithography get you there?
Proximity lithography
For g = 20 microns,l = 436 nm => 3 microns
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Dec,10,2003
6.12J / 3.155J Microelectronic processing
Fraunhoffer (far field diffraction):
Minimum resolved feature = lf/d (no limit on lens diameter,d)
Can Projection lithography get you there?
For f ≈ d,l = 436 nm => 0.4 microns
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6.12J / 3.155J Microelectronic processing
l =
hc
E
l =
h
mv
=
1.23
E(eV )
(?)
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Semiconductor scaling challenges:
w diffusion length control,statistics,especially for channel
w Thermal management,V
2
/R
Power den.,Pentium,Pentium III,,Pentium III,Nuclear Reactor
w Dielectric breakdown field,V/d
w Interconnect cross-talk,delay,C?,t = L/C
w Information stability,k
B
T > CV
2
w Screening lengths
(range of band bending,depletion regions)
Recall semiconductor physical limits
Electron
concentration
If not semiconductors,then what other information technologies? …
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Size limitations on other information technologies
Schematic of longitudinal
recording medium
Magnetic disk
storage media
Each bit (currently about 0.5 x 0.08 x 0.03 μm - ≈ 10 Gb/in
2
)
Consists of 1000 grains; noise μ N
-1/2
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Dec,10,2003
6.12J / 3.155J Microelectronic processing
Ideal medium,single bit = 1 single-domain particle
Patterned
storage media
100 nm
‘1’ ‘0’ ‘1’
Each bit (occupying about 100 x 100 nm,≈ 100 Gb/in
2
)
consists of 1000 grains; media noise largely eliminated
200 nm
Each pillar is
single-domain,
can be
magnetized
‘up’ or ‘down’
Dec,10,2003
6.12J / 3.155J Microelectronic processing
How small must particle be to be in single-domain state?
Exchange length,l,over which the magnetization is approximately parallel
l = (A/M
s
2
)
1/2
(20 nm for Ni)
A = exchange constant (~10
-6
erg/cm); M
s
= saturation magnetization
Single domain
nm scale
d < l
Non-uniform
d > l
Domain wall width,d ≈ p(A/K
u
)
1/2
,
K
u
= anisotropy.
Multi-domain
micron scale
d >> l,d
V
particle
￡
25k
B
T
K
u
SD particles
thermally decouple,
Superparamagnetism
(Semiconductor memory problem,CV
2
< k
B
T )
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Spin-based devices
Metal length scales shorter
e
-
e
-
e
-
Mobile carrier
Scatters
from ion
r < r < rSpin-dependent
resistivity
x
M (x)
Spin memory
is lost over x,t
e
-
M (x)
x
e
-
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Unlike semiconductor devices,
performance of
spin-based devices
improves as thickness decreases
because screening lengths
and spin diffusion lengths in metals << than in semiconductors.
Spintronics = spin (magnetism)-based electronic devices
Separator Device
non-mag metal => low-impedance
spin valve or spin switch
insulator => high-impedance
spin-tunnel junction
(Messervey and Tedrow,Phys,Rpts,238,174 (‘96);
Moodera et al,Phys,Rev,Lett,80,2941 (‘98))
The smaller the better
x
M (x)
Spin memory
is lost over x,t
e
-
Dec,10,2003
6.12J / 3.155J Microelectronic processing
So it is worth exploring the limits of
Nano-lithography,
nano-patterning,
self-assembly
not just for semiconductor devices
but for magnetics as well…
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Subtractive and additive patterning
Whichever lithography method is used,
structures are created by subtractive or additive patterning.
(c) remove magnetic material (d) remove template
substrate
(a) deposit magnetic material (b) define template on top
template
magnetic material
Subtractive patterning requires removal (etching) of the magnetic material.
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Additive patterning
(does not require etching of the magnetic material)
(a) deposit template (b) deposit magnetic (c) remove template (“lift-off”)
material on top of template
substrate
magnetic material
template
(b) electroplate to fill template (c) remove template
OR
Dec,10,2003
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Pros and Cons of these two basic methods
Additive patterning is easier because it does not require etching of the magnetic
film,It is better for making tall structures.
However it is limited to film deposition methods that do not give good step
coverage over the mask:
Evaporation,produces tapered
structures due to shadowing
evaporative deposition
electrodeposition
sputtering (low-pressure,<0.1 mTorr)
Evaporation and electrodeposition limit choice of materials
Au
Electroplating,requires
conductive substrate
Dec,10,2003
6.12J / 3.155J Microelectronic processing
200 nm
Examples of Additive patterning
C,A,Ross,M.I.T.
100 nm
Evaporated pyramids…in template after liftoff
Electrodeposited Ni pillars
200 nm
Each pillar is
single-domain,
can be
magnetized
‘up’ or ‘down’
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Additive patterns with Electron-beam lithography
An electron beam ‘writes’ (exposes) resist,typically PMMA,This is
done in a dedicated e-beam writer,A scanning electron microscope
can be modified to perform this function.
Resolution depends on the beam diameter and production of
secondary electrons.
Since this is a serial writing process,it can be slow,The writing
speed depends on the beam current and resist sensitivity (which
govern the data rate) and the pixel size (resolution).
e.g,to write 1 cm
2
of 10 nm pixels,at 1000 A/cm
2
,100 electrons per pixel,if all
pixels are addressed:
converted SEM,100 kHz,takes > 1 month
commercial writer,100 MHz,takes 1 hr
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Co rings,
12 nm thick
Diameter:
150 nm – 1 mm
Ring width:
30 nm-200 nm
200 nm
200 nm
500 nm
200 nm
200 nm
200 nm
Electron-beam lithography
C,A,Ross
200 nm
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Examples of,lift-off” processing
Liftoff does not work for sputtering unless the
pressure is very low,because of step coverage.
Ion-beam sputtering @ 0.1 mTorr
Magnetron sputtering @ 3 mTorr
500 nm
500 nm
F.J,Casta?o
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Another additive patterning,Shadow-masking
For relatively coarse patterning,a mask can be placed in the deposition system
so that material selectively deposits on certain parts of the substrate,or smaller
Patterns of ~100 mm can be made.
collimated
source (e.g.
evaporation
cell)
shadow mask
structure
substrate
A relatively simple process,but the mask becomes coated and must be cleaned or replaced.
Structure with <100 nm wide features made
by an e-beam patterned shadow mask,Park
et al,J Appl Phys 81,4717,null(1997)
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6.12J / 3.155J Microelectronic processing
Triple-angle evaporation through shadow mask
(Lu,Moodera,Wang,and O’H,NIRT)
Top resist layer
a) First
evaporation,
b) Oxidation
Substrate
0°
c) Second
evaporation
+20°
First tunnel
junction
d) Third
evaporation
Second tunnel
junction
-20°
Large undercut is needed
in shadow mask
for evaporation of tunnel junctions
Suspended
resist
bridge
Island
Lead
Lead
Top view - island region
Resist Undercut Substrate
582 n m
60 n m
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Measurement of spin tunneling demands
junction resistance of 26 - 500 kW
Fe Al Fe
200 nm
Al
2
O
3
barrier
Fe Metal Fe
M
1
M
2
Double junction device
Enhanced magnetoresistance due to
co-tunneling in double-junction device
Junction area ≈ 80 ￥ 80 nm
(Junction resistance depends on oxide thickness and area)
Double junction device
(Lu,Moodera,Wang,and O’H,NIRT)
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Subtractive patterning (etch away)
…allows more flexibility in the types of films that are patterned.
Requires an etch step and most magnetic materials are notoriously hard to etch.
Chemical (wet) etching in acids,not suitable for very small structures
Reactive ion etching,most magnetic materials are resistant to removal
Ion milling (sputter etching),physical removal of material
using energetic ions,requiring a hard mask,This can cause damage to the edges of
the structures,Subtractive patterning works best for thinner films.
mask,e.g,W
Magnetic film
substrate
Ar+
disordered
region
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Examples of Subtractive patterning
Sputtered films etched into different shapes
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6.12J / 3.155J Microelectronic processing
Making periodic nanoscale patterns
Resist layer (usually polymeric) is spin-coated on substrate,then baked.
Resist is sensitive to radiation,e.g,light,x-rays or electrons
Pattern is exposed in the resist layer using photons,electrons,etc.
Resist is developed to selectively remove the parts that have been exposed
(positive resist) or unexposed (negative resist),then baked.
exposure
positive resist
negative resist
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Some complications:
Reflective substrates can lead to poorly defined resist edges
after development,One solution is to incorporate an
antireflective coating which absorbs light between the
substrate and the resist.
Adhesion of resists is often poor,so the surface is often treated
with an adhesion promoter such as hexamethyldisilazane
(HMDS).
Multilevel resists (2 separate layers,with the top layer slightly
less sensitive) can be used to get a good undercut profile that
is advantageous for lift-off processing.
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Interference lithography
Interference lithography,Optical standing wave exposes a grating pattern into
resist layer,Can superpose gratings or fringe patterns.
Periods of l/2 are possible.
An antireflective layer is typically needed.
Types of patterns formed are strictly periodic,dots,pillars,or lines.
Mirror
Substrate
Laser
beam,
wave-
length l
Angle q
Dec,10,2003
6.12J / 3.155J Microelectronic processing
100 nm
200 nm
1000nm
PSV-elements
word lines
sense lines
500nm
300nm
word lines
sense lines
Examples of structures made by
Interference lithography (C.A,Ross)
ARC-insulator
PSV/W -wires
Dec,10,2003
6.12J / 3.155J Microelectronic processing
X-ray Lithography
Resembles contact printing optical lithography,but wavelength ≈ 0.4 nm to 4.5 nm
is used to reduce diffraction effects and scattering.
A membrane mask is made (typically using e-beam lithography).
The x-ray source can be an electron impact source (rotating anode) or a high-
brightness synchrotron.
Resists are similar to e-beam lithography.
100 nm wide line made by XRL
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6.12J / 3.155J Microelectronic processing
Imprint Lithography
A hard ‘stamp’,(silica,SiN,or Si) is pressed into a resist layer,transferring
pattern pattern resist.
Or flexible stamp made of PMDS is used to transfer material onto a substrate,
similar to an ink stamp.
The stamp is made by another form of lithography.
pressure
stamp
resist
substrate
25 nm wide bars
made by imprint
lithography,Wu
et al,JVSTB 16
3825,null(1998)
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Focussed Ion Beam (FIB) Patterning
Beams of energetic particles such as Ga+ can be used to pattern substrates directly
by milling away material,Like e-beam writing,this is a slow process.
There are other probe-based,direct-writing methods,
e.g,CVD-writing using a scanning probe microscope.
150 nm wide Fe pillars made
using CVD,Wirth et al,Phys
Rev B 57 R14028,null(1998)
250 nm islands defined in a film by a
FIB,Lohau et al,Appl Phys Lett 78
990,null(2001)
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6.12J / 3.155J Microelectronic processing
Novel patterning processes for nanoscale devices
Perhaps less obvious:
Self assembly (“Bottom up”)
Block copolymers?
Wet chemical processes?
Carbon nono-tubes,rings?
Other organics
75% of NIRTs
Dec,10,2003
6.12J / 3.155J Microelectronic processing
29~50nm18~35nm
PFS spheres,
resistant to O
2
plasma
PS matrix:
removed by O
2
plasma
Block copolymer lithography
Block copolymers,two immiscible blocks,A and B.
Volume fraction of each component determines a range
of morphologies obtained on annealing;
periodicities of a few nm and higher.
These self-assembling systems are promising
nanolithography templates.
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Self assembly,Block co-polymers
Gleiter,2000
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Magnetic particles can be attached to end of nano-tube
Tunneling device?
SET
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“Bottom up”,Patterning Carbon Nanotubes,Rings
Francesco Stellacci (M.I.T.) with M,Prato,Trieste,Italy
Magnetic Nanotubes
Diamagnetic rings
Paramagnetic rings
NS
Fluid level
Glass cuvette
100 nm
Rings show ballistic conductivity
(spin coherence?)
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Biologically benign,but diamagnetic?
Francesco Stellacci
Hydrophobic/hydrophilic
p-bonded rings
self-assemble on gold
SH COOH
SH
MPA
C8
Courtesy of Francesco Stellacci
Dec,10,2003
6.12J / 3.155J Microelectronic processing
National Facilities
For researchers (industrial and academic) without access to lithography facilities,
the National Nano Users Network provides access to facilities at four sites in the
US,Cornell,Howard,Stanford,Penn State and UCSB.
www.nnun.org
“National Nanofabrication Users Network (NNUN) provides users with access
to some of the most sophisticated nanofabrication technologies in the world with
facilities open to all users from academia,government,and industry,The
combined staffs of the NNUN have extensive experience in all phases of
nanofabrication and its use in fields ranging from nanophysics to biology to
electronics,We have experts in micromechanics and biology to assist users in
translating their ideas into experimental reality,With the assistance of the
NNUN,users can often fabricate advanced nanostructures within weeks of initial
contact.” (NNUN website)
Dec,10,2003
6.12J / 3.155J Microelectronic processing
Summary
Simplest patterning uses shadow-masking directly in a deposition system,
relatively large-scale structures.
Simplest processing using a resist layer is contact-printing,
requires a resist spinner,hotplates,developer,a bright lamp,and mask.
Projection optical lithography => smaller structures (~500 nm);
requires more complex equipment.
Most common method for sub-micron structures of arbitrary shape
is e-beam lithography,requires SEM or a dedicated e-beam writer.
NNUN has facilities available to the public,A wide variety of other specialized
lithography methods have been developed,each of which has its own advantages
and disadvantages,The nature of resist limits resist-based lithography to ~5 nm edge
roughness.
For features with dimensions of a few nm,other processes such as chemically-
synthesized nanoparticle formation may be appropriate.
Dec,10,2003
6.12J / 3.155J Microelectronic processing
References
S.A,Campbell,The science and engineering of microelectronic fabrication,
Oxford (1996)
J.D,Plummer,M.D,Deal and P.B,Griffin,Silicon VLSI Technology:
Fundamentals,Practice and Modeling,Prentice Hall,(2000)
S.K,Ghandhi,VLSI Fabrication principles,Wiley (1994)
S.M,Sze,VLSI Technology,McGraw-Hill (1988)
H.I,Smith,Submicron and nanometer-structures technology,Nanostructures
Press,Sudbury MA (1994)
C.A,Ross,“Patterned media”,Ann,Rev,Materials Research 31 203 (2001)
