3.155J/6.152J Lecture 2:
IC Lab Overview
Prof,Martin A,Schmidt
Massachusetts Institute of Technology
9/8/2003
Outline
The MOSFET Structure
Semiconductor Doping
The MOSFET as a Switch
A MOSFET Process
The MOS Capacitor Process
Recommended reading
Plummer,Chapter 1
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 2
MOSFET
G
Source Drain
Oxide
Gate
Bulk
S
D
D
G
S
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 3
N-Channel MOSFET
+V
G
n-type n-type
Oxide
Gate
p-type
+V
D
0 V
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 4
A Word About Doping…,
Silicon has four valence electrons
It covalently bonds with 4 adjacent atoms in the crystal lattice
Si
Si
Si
Si Si Si Si
Si Si Si Si
Si Si Si Si
SiSiSiSi
SiSiSiSi
SiSiSiSi
SiSiSiSi Si Si Si SiSi
SiSiSiSi Si Si Si SiSi
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 5
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 6
Intrinsic Semiconductor
Si
Si
Si
Si Si Si Si
Si Si Si Si
Si Si Si Si
SiSiSiSi
SiSiSiSi
SiSiSiSi
SiSiSiSi Si Si Si SiSi
SiSiSiSi Si Si Si SiSi
Increasing Temperature Causes Creation of Free Carriers
10
10
cm
-3
free carriers at 23C (out of 2x10
23
cm
-3
)
Intrinsic Conductivity
N-type Doping
Phosphorus has 5 valence electrons
‘Donates’ one conduction electron – n-type
Our substrate has 10
15
cm
-3
phosphorus (1 in 10
8
)
Si
Si Si Si Si
Si Si Si Si
SiSiSiSi
SiSiSiSi
SiSiSiSi Si Si Si SiSi
SiSiSiSi Si Si Si SiSi
P
Si Si Si Si SiSiSiSiSi
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 7
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 8
P-type Doping
B
Si
Si Si Si Si
Si Si Si Si
Si Si Si Si
SiSiSiSi
SiSiSiSi
SiSiSiSi
SiSiSiSi Si Si Si SiSi
SiSiSiSi Si Si Si SiSi
Si
Boron has 3 valence electrons
‘Accepts’ one electron from lattice
Creates a ‘hole’ – p-type
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 9
Counter Doping
Si
Si Si Si Si
Si Si Si Si
Si Si Si Si
SiSiSiSi
SiSiSiSi
SiSiSiSi
SiSiSiSi Si Si Si SiSi
SiSiSiSi Si Si Si SiSi
P
B
The addition of one more B than P causes the
doping type to change from n-type to p-type
Counter Doping Process
n-type (10
15
cm
-3
)
Concentration10
15
n-type (10
15
cm
-3
)
p-type (>10
15
cm
-3
)
Implant Boron
and Anneal
Depth
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 10
P/N Junction
+ - ++ - + - +
+ - + - + --
+ - + - + - +
+ - + - + --
+ - + - + - +
+ - + - + --
+ - + - + - +
- + - + - +
- + - + - + -
+ - + - + - +
- + - + - + -
+ - + - + - +
- + - + - + -
+ - + - + - +
n-type
p-type
Depletion Region
-
-
-
-
-
+
+
+
+
+
p-type n-type
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 11
P/N Junction - Diode
I
-
-
-
-
-
+
+
+
+
+
p-type n-type
I
V
+ V
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 12
----------------
N-Channel MOSFET Operation
0 V
+V
G
n-type n-type
Oxide
p-type
+V
D
0 V
+++++++++++++++++
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 13
MOSFET as a Switch
0 V
n-type n-type
Oxide
Gate
p-type
+V
D
0 V
n-type n-type
Oxide
Gate
p-type
+V
D
0 V
+V
G
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 14
Starting Material
Single crystal silicon
Mask Set
Contains x,y info
(Top View)
Process Sequence
Contains z info
(Cross Section)
Microfabricated Devices
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 15
Sample Mask Set
Four Levels (Masks)
Mask Definition
1 Active Area
2 Polysilicon
3 Contact Cuts
4 Aluminum
Transistor
Diffusion Polysilicon Metal
(MOSFET)
Resistor Resistor Resistor
Fall 2003 – M.A,Schmidt
(Diode)
3.155J/6.152J – Lecture 2 – Slide 16
-------
Our Process
Poly Gate pMOS
p-channel
Metal-Oxide-Semiconductor (MOSFET)
polysilicon
n-silicon
p p
+++++++
Source
DrainGate
Polycrystaline Silicon
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 17
Starting Material
6” (150mm) Diameter Silicon Wafer
30 +/- 1 mil thick (~750 μm)
n-type (doped with Phosphorus)
1.5?-cm resistivity (10
15
cm
-3
Phos)
<100> crystal orientation
Minor Flat
<100>
Major Flat
<110>
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 18
FET Process Steps
1,Characterize the wafer (resistivity,orientation,and type)
2,Grow 5000A ‘Field Oxide’ for device isolation
Typically at 800-1100C for 1 hour in O
2
or steam
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 19
Process Steps
3,Pattern Active Area (Mask #1)
Mask
Coat with
photoresist
Expose
Develop
Etch
*
Strip resist
*
Wet etch
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 20
Process Steps
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 21
Process Steps
4,Grow 500A Gate Oxide
5,Deposit 5000A Polysilicon by LPCVD (low pressure
chemical vapor deposition)
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 22
M.A,Schmidt 3 152J – Lecture 2 – SFall 2003 –,155J/6,lide 23
Process Steps
6,Pattern Polysilicon (Mask #2)
Process Steps
7,Etch Gate Oxide
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 24
Process Steps
8,Ion Implantation of Boron
B
+
B
+
B
+
B
+
B
+
B
+
B
+
B
+
B
+
B
+
B
+
B
+
B
+
B
+
B
+
9,Drive-In (950C in O
2
)
Note self alignment
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 25
Process Steps
10,Strip Backside
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 26
Process Steps
11,Pattern Contact Cuts (Mask #3)
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 27
Process Steps
12,Evaporate Aluminum
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 28
M.A,Schmidt 3 152J – Lecture 2 – SFall 2003 –,155J/6,lide 29
Process Steps
13,Pattern Aluminum (Mask #4)
Process Steps
2
:H
2
)
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 30
14,Sinter (400C – N
Process Results
The Four Mask Process Yields
Resistors
Metal
Polysilicon
Diffusion
Capacitors
Metal-Silicon
Metal-Polysilicon
Polysilicon-Silicon
Gate Oxide
Field Oxide
Diode
MOSFET
Bipolar Junction Transistor (low quality)
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 31
Our Labs
Lab Session 1
1.1 Lab Safety and Cleanroom Orientation
1.2 RCA (ICL RCA)
1.3 Gate Oxidation
Thermco Atmospheric Furnace (5D-FieldOx)
Dry Oxidation,1000°C 60 minutes
1.4 Doped Polysilicon Deposition
Thermco LPCVD (6A-Poly)
Lab Session 2
2.1 Measure oxide thickness (UV1280)
2.2 HMDS,Photoresist Application,Postbake (SSI coater track)
2.3 Dry etch backside polysilicon (LAM490B)
2.4 Etch backside oxide in BOE until de-wet (OxEtch-BOE)
2.5 Strip frontisde resist with Matrix System One Stripper (Asher)
Lab Session 3
3.1 HMDS,Photoresist Application,Pre-bake (SSI coater track)
3.2 Exposure,Development,and Inspection (I-Stepper)
3.3 Dry-etch polysilicon (LAM490B)
3.4 Strip photoresist with Matrix System One Stripper (Asher)
3.5 Visual Inspection,
3.6 HF dip for 30 s (ICL Pre-Metal)
3.7 Device characterization,MOS Capacitor
Determine oxide capacitance,
Determine bulk dopant concentration,
Determine fixed interface charge,
3.8 Sheet resistance measurement,Van der Pauw structure
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 32
Lab Session 1
1.1 Lab Safety and Cleanroom Orientation
1.2 RCA (ICL RCA)
1.3 Gate Oxidation
Thermco Atmospheric Furnace (5D-FieldOx)
Dry Oxidation,1000°C 60 minutes
1.4 Doped Polysilicon Deposition
Thermco LPCVD (6A-Poly)
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 33
Lab Session 2
2.1 Measure oxide thickness (UV1280)
2.2 HMDS,Photoresist Application,Postbake
(SSI coater track)
2.3 Dry etch backside polysilicon (LAM490B)
2.4 Etch backside oxide in BOE until de-wet
(OxEtch-BOE)
2.5 Strip frontisde resist with Matrix System
One Stripper (Asher)
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 34
Lab Session 3
3.1 HMDS,Photoresist Application,Pre-bake
(SSI coater track)
3.2 Exposure,Development,and Inspection
(I-Stepper)
3.3 Dry-etch polysilicon (LAM490B)
3.4 Strip photoresist with Matrix System One
Stripper (Asher)
3.5 Visual Inspection
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 35
Lab Session 3 (con’t.)
3.6 HF dip for 30 s (ICL Pre-Metal)
3.7 Device characterization,MOS Capacitor
Determine oxide capacitance,
Determine bulk dopant concentration,
Determine fixed interface charge,
3.8 Sheet resistance measurement,Van der
Pauw structure
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 36
IC Lab Overview
Prof,Martin A,Schmidt
Massachusetts Institute of Technology
9/8/2003
Outline
The MOSFET Structure
Semiconductor Doping
The MOSFET as a Switch
A MOSFET Process
The MOS Capacitor Process
Recommended reading
Plummer,Chapter 1
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 2
MOSFET
G
Source Drain
Oxide
Gate
Bulk
S
D
D
G
S
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 3
N-Channel MOSFET
+V
G
n-type n-type
Oxide
Gate
p-type
+V
D
0 V
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 4
A Word About Doping…,
Silicon has four valence electrons
It covalently bonds with 4 adjacent atoms in the crystal lattice
Si
Si
Si
Si Si Si Si
Si Si Si Si
Si Si Si Si
SiSiSiSi
SiSiSiSi
SiSiSiSi
SiSiSiSi Si Si Si SiSi
SiSiSiSi Si Si Si SiSi
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 5
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 6
Intrinsic Semiconductor
Si
Si
Si
Si Si Si Si
Si Si Si Si
Si Si Si Si
SiSiSiSi
SiSiSiSi
SiSiSiSi
SiSiSiSi Si Si Si SiSi
SiSiSiSi Si Si Si SiSi
Increasing Temperature Causes Creation of Free Carriers
10
10
cm
-3
free carriers at 23C (out of 2x10
23
cm
-3
)
Intrinsic Conductivity
N-type Doping
Phosphorus has 5 valence electrons
‘Donates’ one conduction electron – n-type
Our substrate has 10
15
cm
-3
phosphorus (1 in 10
8
)
Si
Si Si Si Si
Si Si Si Si
SiSiSiSi
SiSiSiSi
SiSiSiSi Si Si Si SiSi
SiSiSiSi Si Si Si SiSi
P
Si Si Si Si SiSiSiSiSi
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 7
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 8
P-type Doping
B
Si
Si Si Si Si
Si Si Si Si
Si Si Si Si
SiSiSiSi
SiSiSiSi
SiSiSiSi
SiSiSiSi Si Si Si SiSi
SiSiSiSi Si Si Si SiSi
Si
Boron has 3 valence electrons
‘Accepts’ one electron from lattice
Creates a ‘hole’ – p-type
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 9
Counter Doping
Si
Si Si Si Si
Si Si Si Si
Si Si Si Si
SiSiSiSi
SiSiSiSi
SiSiSiSi
SiSiSiSi Si Si Si SiSi
SiSiSiSi Si Si Si SiSi
P
B
The addition of one more B than P causes the
doping type to change from n-type to p-type
Counter Doping Process
n-type (10
15
cm
-3
)
Concentration10
15
n-type (10
15
cm
-3
)
p-type (>10
15
cm
-3
)
Implant Boron
and Anneal
Depth
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 10
P/N Junction
+ - ++ - + - +
+ - + - + --
+ - + - + - +
+ - + - + --
+ - + - + - +
+ - + - + --
+ - + - + - +
- + - + - +
- + - + - + -
+ - + - + - +
- + - + - + -
+ - + - + - +
- + - + - + -
+ - + - + - +
n-type
p-type
Depletion Region
-
-
-
-
-
+
+
+
+
+
p-type n-type
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 11
P/N Junction - Diode
I
-
-
-
-
-
+
+
+
+
+
p-type n-type
I
V
+ V
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 12
----------------
N-Channel MOSFET Operation
0 V
+V
G
n-type n-type
Oxide
p-type
+V
D
0 V
+++++++++++++++++
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 13
MOSFET as a Switch
0 V
n-type n-type
Oxide
Gate
p-type
+V
D
0 V
n-type n-type
Oxide
Gate
p-type
+V
D
0 V
+V
G
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 14
Starting Material
Single crystal silicon
Mask Set
Contains x,y info
(Top View)
Process Sequence
Contains z info
(Cross Section)
Microfabricated Devices
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 15
Sample Mask Set
Four Levels (Masks)
Mask Definition
1 Active Area
2 Polysilicon
3 Contact Cuts
4 Aluminum
Transistor
Diffusion Polysilicon Metal
(MOSFET)
Resistor Resistor Resistor
Fall 2003 – M.A,Schmidt
(Diode)
3.155J/6.152J – Lecture 2 – Slide 16
-------
Our Process
Poly Gate pMOS
p-channel
Metal-Oxide-Semiconductor (MOSFET)
polysilicon
n-silicon
p p
+++++++
Source
DrainGate
Polycrystaline Silicon
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 17
Starting Material
6” (150mm) Diameter Silicon Wafer
30 +/- 1 mil thick (~750 μm)
n-type (doped with Phosphorus)
1.5?-cm resistivity (10
15
cm
-3
Phos)
<100> crystal orientation
Minor Flat
<100>
Major Flat
<110>
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 18
FET Process Steps
1,Characterize the wafer (resistivity,orientation,and type)
2,Grow 5000A ‘Field Oxide’ for device isolation
Typically at 800-1100C for 1 hour in O
2
or steam
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 19
Process Steps
3,Pattern Active Area (Mask #1)
Mask
Coat with
photoresist
Expose
Develop
Etch
*
Strip resist
*
Wet etch
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 20
Process Steps
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 21
Process Steps
4,Grow 500A Gate Oxide
5,Deposit 5000A Polysilicon by LPCVD (low pressure
chemical vapor deposition)
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 22
M.A,Schmidt 3 152J – Lecture 2 – SFall 2003 –,155J/6,lide 23
Process Steps
6,Pattern Polysilicon (Mask #2)
Process Steps
7,Etch Gate Oxide
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 24
Process Steps
8,Ion Implantation of Boron
B
+
B
+
B
+
B
+
B
+
B
+
B
+
B
+
B
+
B
+
B
+
B
+
B
+
B
+
B
+
9,Drive-In (950C in O
2
)
Note self alignment
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 25
Process Steps
10,Strip Backside
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 26
Process Steps
11,Pattern Contact Cuts (Mask #3)
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 27
Process Steps
12,Evaporate Aluminum
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 28
M.A,Schmidt 3 152J – Lecture 2 – SFall 2003 –,155J/6,lide 29
Process Steps
13,Pattern Aluminum (Mask #4)
Process Steps
2
:H
2
)
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 30
14,Sinter (400C – N
Process Results
The Four Mask Process Yields
Resistors
Metal
Polysilicon
Diffusion
Capacitors
Metal-Silicon
Metal-Polysilicon
Polysilicon-Silicon
Gate Oxide
Field Oxide
Diode
MOSFET
Bipolar Junction Transistor (low quality)
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 31
Our Labs
Lab Session 1
1.1 Lab Safety and Cleanroom Orientation
1.2 RCA (ICL RCA)
1.3 Gate Oxidation
Thermco Atmospheric Furnace (5D-FieldOx)
Dry Oxidation,1000°C 60 minutes
1.4 Doped Polysilicon Deposition
Thermco LPCVD (6A-Poly)
Lab Session 2
2.1 Measure oxide thickness (UV1280)
2.2 HMDS,Photoresist Application,Postbake (SSI coater track)
2.3 Dry etch backside polysilicon (LAM490B)
2.4 Etch backside oxide in BOE until de-wet (OxEtch-BOE)
2.5 Strip frontisde resist with Matrix System One Stripper (Asher)
Lab Session 3
3.1 HMDS,Photoresist Application,Pre-bake (SSI coater track)
3.2 Exposure,Development,and Inspection (I-Stepper)
3.3 Dry-etch polysilicon (LAM490B)
3.4 Strip photoresist with Matrix System One Stripper (Asher)
3.5 Visual Inspection,
3.6 HF dip for 30 s (ICL Pre-Metal)
3.7 Device characterization,MOS Capacitor
Determine oxide capacitance,
Determine bulk dopant concentration,
Determine fixed interface charge,
3.8 Sheet resistance measurement,Van der Pauw structure
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 32
Lab Session 1
1.1 Lab Safety and Cleanroom Orientation
1.2 RCA (ICL RCA)
1.3 Gate Oxidation
Thermco Atmospheric Furnace (5D-FieldOx)
Dry Oxidation,1000°C 60 minutes
1.4 Doped Polysilicon Deposition
Thermco LPCVD (6A-Poly)
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 33
Lab Session 2
2.1 Measure oxide thickness (UV1280)
2.2 HMDS,Photoresist Application,Postbake
(SSI coater track)
2.3 Dry etch backside polysilicon (LAM490B)
2.4 Etch backside oxide in BOE until de-wet
(OxEtch-BOE)
2.5 Strip frontisde resist with Matrix System
One Stripper (Asher)
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 34
Lab Session 3
3.1 HMDS,Photoresist Application,Pre-bake
(SSI coater track)
3.2 Exposure,Development,and Inspection
(I-Stepper)
3.3 Dry-etch polysilicon (LAM490B)
3.4 Strip photoresist with Matrix System One
Stripper (Asher)
3.5 Visual Inspection
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 35
Lab Session 3 (con’t.)
3.6 HF dip for 30 s (ICL Pre-Metal)
3.7 Device characterization,MOS Capacitor
Determine oxide capacitance,
Determine bulk dopant concentration,
Determine fixed interface charge,
3.8 Sheet resistance measurement,Van der
Pauw structure
Fall 2003 – M.A,Schmidt 3.155J/6.152J – Lecture 2 – Slide 36
