METALLIZATION,INTERCONNECTS
Read,Plummer Chapter 11; Campbell Chapter 15
Why do we need metallization? - To connect devices electrically
Local interconnects:
gate contacts,doped polySi,silicides
Inter-level
to each other and to the outside world; power and data,
plugs,vias,e.g,W
Packaging
Longer range interconnects,
Cu or Al (several mm per chip)
Materials choices for interconnects,more complex multilayer interconnects.
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Generic metallization layout
gate contact (local interconnect)
Plug,via
metal lines
(global
interconnects)
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1
Requirements for metallization,
1,Low electrical resistivity
2,Electrical contact with device (Ohmic or Schottky)
3,Step coverage
4,Patterning methods (can it be etched?)
5,Thermal and mechanical stability
6,Reliability in service,e.g,electro-migration,Next week
(beside metallization,
inter-metal dielectrics are equally important …)
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ox ≈F
min
ox
e
0
r
Hx
ox s
ˉ
WL
F
min
ˉ
k 4
ox
t
L
a10
-17
10
-8
t
L
= RCa1.8ke
0
rL
2
+
á?H,L
s
,x
ox
t
L
a 3.6k
á?
t
gate
a10
-11
min
=0.25 microns
WSi
2
W
Al
Cu
for F
Poly Si
Local interconnects LF
min
sec
Delay Global interconnects LA few mm t
L
a10
-9
sec
time
(sec)
Inductive effects 2 -3 orders smaller; t
ind
=(LC)
10
-12
1 10 100
Chip area (mm
2
)
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Crudely,t = 1 cm/c = 10
-8
sec
but if e > e
0
,t = 1 cm (eμ) > 10
-8
sec
Compared to gate times of order 10
-11
sec
L WL
R =r C =k
ox
e
0
WH x
ox
Fringe field factor
ê
11
HL
+k
ox
e
0
L
1,Resistivity,why low? C
I
C
s
R
L
H
WL
s
s
2
ê
L
2
3
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1,Resistivity
Which material
is better for local
and which for
global
interconnects?
use for GaAs
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2,Ohmic and Schottky junctions
Even after selecting conductor material,
no guarantee it will make good electrical contact to Si,GaAs,etc.
Nature of contact depends on charge transfer at metal/semiconductor interface;
charging => band bending & bending depends on
work functions,f
m
,f
s
and electron affinity,c.
E
f
Energy
Metal
n-type semiconductor
Vacuum
f
m
f
s
c
E
f
E
c
E
v
Background for Schottky barriers
When a p-n junction is formed..,
Mobile e’s
p
Mobile
holes
Immobile e’s
n
Immobile
holes
e
-
E
F
E
F
E
F
E
Excess e’s h’s
(ddepletion region)
=> E field that
halts flow of e’s
..,there is a net flow of carriers
across interface…
until energy difference is neutralized and
Fermi energies come to a common value,
What happens at semiconductor/metal interface…
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f
s
f
m
Schottky barriers
When a metal -n-type semiconductor junction is formed with >,.,
Vacuum
Vacuum
Mobile e’s
Immobile
holes
e
-
..,there is a net flow of carriers
across interface…
f
m
f
s
n
E
F
E
F E
F
Mobile e’s
n
f
m
E
Heavily
doped
E
F
Lightly
doped
until energy difference is neutralized and
Fermi energies come to a common value,
w depletion region (length governed by screening length)
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4
Ideal Schottky junction,>
There is a barrier
n-type semiconductor,f
B
M o b i l e e’s
n
f
m
E
preventing electrons from going
from metal to
E
F E
F
-type semiconductorf n,
s
There is an internal field keeping
carriers away from junction,
This junction behaves like a diode,
Vacuum
If < there is no barrier for n-type
semiconductor (Ohmic),
ln I
f
m
V
f
B
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f
s
f
m
5
Metallic electrons can only go over barrier
by thermionic emission,
tunnel or
or can tunnel through
thermioic
if it is narrow (highly doped),
If f > f => Schottky contact with n-type semiconductor
ms
Ohmic with p-type
If f < f => Schottky contact with p-type semiconductor
ms
Ohmic with n-type
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The metal work function
should determine contact type,
but in practice,
surface contamination and traps
pin Fermi level
and usually have Schottky barrier
when f
B
= 0.5 - 0.8 eV,
To obtain Ohmic contact,
make barrier very narrow
very heavy doping
(n
+
or p
+
~ 10
20
cm
-3
)
adjacent to the metal,
Al is a p dopant,
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6
3,Step coverage,and 4,Patterning
Step coverage is controlled by the deposition method;
Patterning method is controlled by the chemistry of the material,
Dep,method Etch method
Al-Si-Cu Sputter RIE in CCl
4
or wet etch*
in acetic/nitric acid
W CVD etch or CMP
poly-Si CVD Nitric acid
Cu P late,sputter Damascene,CMP
*undesirable for very small features
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Cu by damascene process
Cu problem,difficult to etch; also it reacts with Si,
degrades the operation of the transistors,
Solution:
Damascene process for deposition,does not require etching,Make
trenches,deposit plating base,then fill with electrodeposition and
polish surface,The vias can be made simultaneously in a dual-
damascene process,Al can also be deposited by a damascene
process (sputter and reflow to fill trenches),
polish
Cu
dielectric
barrier
use diffusion barriers to prevent diffusion,e.g.TiN (made by CVD),
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7
5,Stability,thermal and mechanical
Thermal stability,
At elevated temperatures,metals can react with Si or SiO
2
to produce unwanted phases,e.g,silicides,eutectics or intermetallics,
This limits the maximum processing temperature
(T typically quite low compared to temperatures needed for oxidation,dopant
diffusion,hence the metal is done last),
Max,temperatures,
Al on Si <450?C
W on Si <600?C
Effects can be predicted from the phase diagrams,
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8
Al-Si has a eutectic at 577?
C,1.59%Si,
During processing,
Si can diffuse into the Al,
The Al under compression,
which can destroy any
junction underneath,
Al
Si
forms spikes into the Si
Al on Si @ T > 450?C
Solution,add ~1%Si to metal;
use barrier layers eg,PtSi,TiSi
2
,TiW,TiN
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Gate contacts
Al cannot withstand the temperatures needed for MOSFET
fabrication,Instead,gate contacts are made of,
Silicides
Many possibilities WSi
2
,TaSi
2
,MoSi
2
,TiSi
22
Several complex crystal structures may be possible in each system,
19
Polysilicon,doped heavily,…or,.,
,For lower resistivity than polySi,Make by sputtering,
CVD,or by depositing metal on Si then reacting,
Silicide over poly-Si (“polycide”) on the gate takes advantage of the
reliable Si/oxide interface but with lower resistance
Silicides can be made on gate,source and drain by self-aligned process
(“salicide”),the silicide forms only at the places where the metal contacts the
silicon,then the unreacted metal is removed,
,CoSi
All have different microstructures,thermal stabilities and reactivities,
Mechanical stability
As wafer is thermally cycled during processing & packaging,
mechanical stresses can build up due to thermal mismatch,
Deposited films,oxides etc,also grow with internal stress,These
stresses can cause delamination and void or hillock formation,
10
Thermal management in packaging,
Old IBM multi-chip module
More than 30 layers
of ceramic,green sheet”
Fired
Containing x,y lines and vias
and 100 chips mounted with solder balls
x
y
vias
Power,
signals
in and out
How pick ceramic,conductors to co-fire
without warp (thermal expansion),
Optimal dielectric constant for speed,
no electrical breaks,robust…
And hermetically sealed
with helium and heat sinks
contacting each chip
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12
Void can form if line is in tension,
Dielectric
Metal line
Substrate
Interface can delaminate
In compression,metal can be
extruded as ‘hillocks’ through
cracks in the overcoat,
Solutions:
control thermal cycling during processing,
or choose materials with compatible thermal expansion
control film stress (by deposition method)
use adhesion layer,eg that reacts with silica to form an oxide,
making a chemical bond to the substrate,
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6,Reliability
There are several failure mechanisms that can occur during the
lifetime of the device,as well as during fabrication,We will
look at reliability in more detail next lecture,
For metallization,the key problems are,
Electromigration (material transport along the metal line due to
a high current density) - reduce this by adding 0.5%Cu to Al
Stress-induced voiding or hillock formation
Corrosion (of Al,AlSiCu,or Cu to form oxides)
Interdiffusion of the metal,which can degrade the transistors (a
problem with Cu) - reduce with diffusion barriers
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What is the best metal,taking all these factors into account?
For Si,
Al-Si-Cu lines (low resistivity) with multilayers of Ti/TiN to reduce
diffusion and electromigration - now replaced by fully-encapsulated
Cu
W vias (not needed in Cu metallization,where we make vias by
dual-damascene process)
Poly-Si gate contacts (avoids spiking,adequate conductivity) or
Silicide/metal gate contacts (e.g,PtSi,TiSi
2
made by reacting metal
with silicon),
For GaAs,
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AuGeNi alloys on n-GaAs,AuZn alloys on p-GaAs,
26
13
1mm
oxide
VLSI Technology,Multilayer Al metal plus W plugs,
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15
1mm
glass
Al
spin-on
glass
W
VLSI Technology,Multilayer Al metal plus W plugs,
Note use of chemical-mechanical polishing to planarize surface,
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Background for Schottky barriers
E
Mobile holes
Immobile holes
Mobile e’s
E
Low
mass
electrons
P
Immobile e’s E
FN
E
Ftype
type
High
mass
holes
Semiconductors have two distinct types of carriers (e’s and h’s)
characterized by
w different mobilities,concentrations,conductivities
w different Fermi energies for N and P
w carriers scattered into dopant sites become trapped
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17