电子工程师手册（英文版五）：ch085

Serra, M., Dervisoglu, B.I. “Testing” The Electrical Engineering Handbook Ed. Richard C. Dorf Boca Raton: CRC Press LLC, 2000 85 Testing 85.1Digital IC Testing Taxonomy of Testing?Fault Models?Test Pattern Generation? Output Response Analysis 85.2Design for Test The Testability Problem?Design for Testability?Future for Design for Test 85.1 Digital IC Testing Micaela Serra In this section we give an overview of digital testing techniques with appropriate reference to material containing all details of the methodology and algorithms. First, we present a general introduction of terminology and a taxonomy of testing methods. Next, we present a definition of fault models, and finally we discuss the main approaches for test pattern generation and data compaction, respectively. Taxonomy of Testing The evaluation of the reliability and quality of a digital IC is commonly called testing, yet it comprises distinct phases that are mostly kept separate both in the research community and in industrial practice. 1. Verification is the initial phase in which the first prototype chips are “tested” to ensure that they match their functional specification, that is, to verify the correctness of the design. Verification checks that all design rules are adhered to, from layout to electrical parameters; more generally, this type of functional testing checks that the circuit: (a) implements what it is supposed to do and (b) does not do what it is not supposed to do. Both conditions are necessary. This type of evaluation is done at the design stage and uses a variety of techniques, including logic verification with the use of hardware description languages, full functional simulation, and generation of functional test vectors. We do not discuss verification techniques here. 2. Testing correctly refers to the phase when one must ensure that only defect-free production chips are packaged and shipped and detect faults arising from manufacturing and/or wear-out. Testing methods must (a) be fast enough to be applied to large amounts of chips during production, (b) take into consideration whether the industry concerned has access to large expensive external tester machines, and (c) consider whether the implementation of built-in self-test (BIST) proves to be advantageous. In BIST, the circuit is designed to include its own self-testing extra circuitry and thus can signal directly, during testing, its possible failure status. Of course, this involves a certain amount of overhead in area, and trade-offs must be considered. The development of appropriate testing algorithms and their tool support can require a large amount of engineering effort, but one must note that it may need to be done only once per design. The speed of application of the algorithm (applied to many copies of the chips) can be of more importance. Micaela Serra University of Victoria Bulent I. Dervisoglu Hewlett-Packard Company ? 2000 by CRC Press LLC 3. Parametric testing is done to ensure that components meet design specification for delays, voltages, power, etc. Lately much attention has been given to I DDq testing, a parametric technique for CMOS testing. I DDq testing monitors the current I DD that a circuit draws when it is in a quiescent state. It is used to detect faults such as bridging faults, transistor stuck-open faults, or gate oxide leaks, which increase the normally low I DD [Jacomino et al., 1989]. The density of circuitry continues to increase, while the number of I/O pins remains small. This causes a serious escalation of complexity, and testing is becoming one of the major costs to industry (estimated up to 30%). ICs should be tested before and after packaging, after mounting on a board, and periodically during operation. Different methods may be necessary for each case. Thus by testing we imply the means by which some qualities or attributes are determined to be fault-free or faulty. The main purpose of testing is the detection of malfunctions (Go/NoGo test), and only subsequently one may be interested in the actual location of the malfunction; this is called fault diagnosis or fault location. Most testing techniques are designed to be applied to combinational circuits only. While this may appear a strong restriction, in practice it is a realistic assumption based on the idea of designing a sequential circuit by partitioning the memory elements from the control functionality such that the circuit can be reconfigured as combinational at testing time. This general approach is one of the methods in design for testability (DFT) (see Section 85.2). DFT encompasses any design strategy aimed at enhancing the testability of a circuit. In particular, scan design is the best-known implementation for separating the latches from the combinational gates such that some of the latches can also be reconfigured and used as either tester units or as input generator units (essential for built-in testing). Figure 85.1(a) shows the general division for algorithms in testing. Test pattern generation implies a fair amount of work in generating an appropriate subset of all input combinations, such that a desired percentage of faults is activated and observed at the outputs. Output response analysis encompasses methods which capture only the output stream, with appropriate transformations, with the assumption that the circuit is stimulated by either an exhaustive or a random set of input combinations. Both methodologies are introduced below. Moreover a further division can be seen between on-line and off-line methods [see Fig. 85.1(b)]. In the former, each output word from the circuit is tested during normal operation. In the latter, the circuit must suspend normal operation and enter a “test mode,” at which time the appropriate method of testing is applied. While off-line testing can be executed either through external testing (a tester machine external to the circuitry) or through the use of BIST, on-line testing (also called concurrent checking) usually implies that the circuit contains some coding scheme which has been previously embedded in the design of the circuitry. If many defects are present during the manufacturing process, the manufacturing yield is lowered, and testing becomes of paramount importance. Some estimation can be given about the relationship between manufac- turing yield, effectiveness of testing and defect level remaining after test [Williams, 1986]. Let Y denote the yield, where Y is some value between 1 (100% defect-free production) and 0 (all circuits faulty after testing). FIGURE 85.1 Taxonomy of testing methods. (a) Test pattern generation; (b) on-line and off-line methods. ? 2000 by CRC Press LLC Let FC be the fault coverage, calculated as the percentage of detected faults over the total number of detectable modeled faults (see below for fault models). The value of FC ranges from 1 (all possible faults detected) to 0 (no testing done). We are interested in the final defect level (DL), after test, defined as the probability of shipping a defective product. It has been shown that tests with high fault coverage (for certain fault models, see below) also have high defect coverage. The empirical equation is DL = (1 – Y 1-FC ) 100% Plotting this equation gives interesting and practical results. Table 85.1 shows only a few examples of some practical values of Y and FC. The main conclusion to be drawn is that a very high fault coverage must be achieved to obtain any acceptable defect level value, and manufacturing yield must be continually improved to maintain reli- ability of shipped products. Fault Models At the defect level, an enormous number of different failures could be present, and it is totally infeasible to analyze them as such. Thus failures are grouped together with regards to their logical fault effect on the functionality of the circuit, and this leads to the construction of logical fault models as the basis for testing algorithms [Abramovici et al., 1992]. More precisely, a fault denotes the physical failure mechanism, the fault effect denotes the logical effect of a fault on a signal-carrying net, and an error is defined as the condition (or state) of a system containing a fault (deviation from correct state). Faults can be further divided into classes, as shown in Fig. 85.2. Here we discuss only permanent faults, that is, faults in existence long enough to be observed at test time, as opposed to temporary faults (transient or intermittent), which appear and disappear in short intervals of time, or delay faults, which affect the operating speed of the circuit. Moreover we do not discuss sequential faults, which cause a combinational circuit to behave like a sequential one, as they are mainly restricted to certain technologies (e.g., CMOS). The most commonly used fault model is that of a stuck-at fault, which is modeled by having a line segment stuck at logic 0 or 1 (stuck-at 1 or stuck-at 0). One may consider single or multiple stuck-at faults and Fig. 85.3 shows an example for a simple circuit. The fault-free function is shown as F, while the faulty functions, under FIGURE 85.2 Fault characteristics. FIGURE 85.3 Single stuck-at fault example. TABLE 85.1 Examples of Defect Levels YFCDL 0.15 0.90 0.18 0.25 0.00 0.75 0.25 0.90 0.15 ? 2000 by CRC Press LLC the occurrence of the single stuck-at faults of either line 1 stuck-at 0 (1/0) or of line 2 stuck-at 1 (2/1), are shown as F*. Bridging faults occur when two or more lines are shorted together. There are two main problems in the analysis of bridging faults: (1) the theoretical number of possible such faults is extremely high and (2) the operational effect is of a wired logic AND or OR, depending on technology, and it can even have different effects in complex CMOS gates. CMOS stuck-open faults have been examined recently, as they cannot be modeled from the more classical fault models and are restricted to the CMOS technology. They occur when the path through one of the p-channel or one of the n-channel transistors becomes an open circuit. The main difficulty in detecting this type of fault is that it changes the combinational behavior of a cell into a sequential one. Thus the logical effect is to retain, on a given line, the previous value, introducing a memory state. To detect such a fault, one must apply two stimuli: the first to set a line at a certain value and the second to try and change that value. This, of course, increases the complexity of fault detection. Test Pattern Generation Test pattern generation is the process of generating a (minimal) set of input patterns to stimulate the inputs of a circuit such that detectable faults can be exercised (if present) [Abramovici et al., 1992]. The process can be divided in two distinct phases: (1) derivation of a test and (2) application of a test. For (1), one must first select appropriate models for the circuit (gate or transistor level) and for faults; one must construct the test such that the output signal from a faulty circuit is different from that of a good circuit. This can be computa- tionally very expensive, but one must remember that the process is done only once at the end of the design stage. The generation of a test set can be obtained either by manual methods, by algorithmic methods (with or without heuristics), or by pseudo-random methods. On the other hand, for (2), a test is subsequently applied many times to each IC and thus must be efficient both in space (storage requirements for the patterns) and in time. Often such a set is not minimal, as near minimality may be sufficient. The main considerations in evaluating a test set are the time to construct a minimal test set; the size of the test pattern generator, i.e., the software or hardware module used to stimulate the circuit under test; the size of the test set itself; the time to load the test patterns; and the equipment required (if external) or the BIST overhead. Most algorithmic test pattern generators are based on the concept of sensitized paths. Given a line in a circuit, one wants to find a sensitized path to take a possible error all the way to an observable output. For example, to sensitize a path that goes through one input of an AND gate, one must set all other inputs of the gate to logic 1 to permit the sensitized signal to carry through. Figure 85.4 summarizes the underlying principles of trying to construct a test set. Each column shows the expected output for each input combination of a NAND gate. Columns 3 to 8 show the output under the presence of a stuck-at fault as per label. The output bits that permit detection of the corresponding fault are shown in a square, and thus at the bottom the minimal test set is listed, comprising the minimal number of distinct patterns necessary to detect all single stuck-at faults. FIGURE 85.4 Test set example. ? 2000 by CRC Press LLC The best-known algorithms are the D-algorithm (precursor to all), PODEM, and FAN [Abramovici, 1992]. Three steps can be identified in most automatic test pattern generation (ATPG) programs: (1) listing the signals on the inputs of a gate controlling the line on which a fault should be detected, (2) determining the primary input conditions necessary to obtain these signals (back propagation) and sensitizing the path to the primary outputs such that the signals and fault can be observed, and (3) repeating this procedure until all detectable faults in a given fault set have been covered. PODEM and FAN introduce powerful heuristics to speed the three steps by aiding in the sequential selection of faults to be examined and by cutting the amount of back and forward propagation necessary. Notwithstanding heuristics, algorithmic test pattern generation is very computationally expensive and can encounter numerous difficulties, especially in certain types of networks. Newer alternatives are based on pseudo- random pattern generation [Bardell et al., 1987] and fault simulation. In this strategy, a large set of patterns is generated pseudo-randomly with the aid of an inexpensive (hardware or software) generator. Typical choices for these are linear feedback shift registers and linear cellular automata registers (see below). The pseudo-random set is used to stimulate a circuit, and, using a fault simulator, one can evaluate the number of faults that are covered by this set. An algorithmic test pattern generator is then applied to find coverage for the remaining faults (hopefully, a small number), and the pseudo-random set is thus augmented. The disadvantages are that the resulting set is very large and fault simulation is also computationally expensive. However, this method presents an alternative for circuits where the application of deterministic algorithms for all faults is infeasible. Output Response Analysis Especially when designing a circuit including some BIST, one must decide how to check the correctness of the circuit’s responses [Bardell et al., 1987]. It is infeasible to store on-chip all expected responses, and thus a common solution is to reduce the circuit responses to relatively short sequences: this process is called data compaction and the short, compacted resulting sequence is called a signature. The normal configuration for data compaction testing is shown in Fig. 85.5. The n-input circuit is stimulated by an input pattern generator (pseudo-random or exhaustive if n < 20); the resulting output vector(s), of length up to 22, is compacted to a very short signature of length k << 22 (usually k is around 16 to 32 bits). The signature is then compared to a known good value. The main advantages of this method are that (1) the testing can be done at circuit speed, (2) there is no need to generate test patterns, and (3) the testing circuitry involves a very small area, especially if the circuit has been designed using scan techniques (see Section 85.2). The issues revolve around designing very efficient input generators and compactors. The main disadvantage of this method is the possibility of aliasing. When the short signature is formed, a loss of information occurs, and it can be the case that a faulty circuit produces the same signature of a fault- free circuit, thus remaining undetected. The design method for data compaction aims at minimizing the probability of aliasing. Using the compactors explained below, the probability of aliasing has been theoretically proven to be 2 –k , where k is the length of the compactor (and thus the length of the signature). It is important to note that (1) the result is asymptotically independent of the size and complexity of the circuit under test; (2) for k = 16, the probability of aliasing is only about 10 –6 and thus quite acceptable; and (3) the empirical results show that in practice this method is even more effective. Most of all, this is the chosen methodology when BIST is required for its effectiveness, speed, and small area overhead. A secondary issue in data compaction is in the determination of the expected “good” signature. The best way is to use fault-free simulation for both the circuit and the compactor, and then the appropriate comparator can be built as part of the testing circuitry [Bardell et al., 1987; Abramovici, 1992]. FIGURE 85.5 Data compaction testing. ? 2000 by CRC Press LLC The most important issue is in the choice of a compactor. Although no “perfect” compactor can be found, several have been shown to be very effective. Several compaction techniques have been researched: counting techniques, as in one’s count, syndrome testing, transition count, and Walsh spectra coefficients; and signature analysis techniques based on linear feedback shift registers (LFSRs) or linear cellular automata registers (LCARs). Only these latter ones are discussed here. LFSRs and LCARs are also the preferred implementation for the input pattern generators. LFSRs as Pseudo-Random Pattern Generators An autonomous LFSR is a clocked synchronous shift register augmented with appropriate feedback taps and receiving no external input [Bardell et al., 1987; Abramovici, 1992]. It is an example of a general linear finite state machine, where the memory cells are simple D flip-flops and the next state operations are implemented by EXOR gates only. Figure 85.6 shows an example of an autonomous LFSR of length k = 3. An LFSR of length k can be described by a polynomial with binary coefficients of degree k, where the nonzero coefficients of the polynomial denote the positions of the respective feedback taps. In Fig. 85.6, the high-order coefficient for x 3 is 1, and thus there is a feedback tap from the rightmost cell s 2 ; the coefficient for x 2 is 0, and thus no feedback tap exists after cell s 1 ; however, taps are present from cell s 0 and to the leftmost stage since x and x 0 have nonzero coefficients. Since this is an autonomous LFSR, there is no external input to the leftmost cell. The state of the LFSR is denoted by the binary state of its cells. In Fig. 85.6, the next state of each cell is determined by the implementation given by its polynomial and can be summarized as follows: s 0 + = s 2 , s 1 + = s 0 % s 2 , s 2 + = s 1 , where the s i + denotes the next state of cell s i at each clock cycle. If the LFSR is initialized in a nonzero state, it cycles through a sequence of states and eventually comes back to the initial state, following the functionality of the next-state rules implemented by its polynomial description. An LFSR that goes through all possible 2 k - 1 nonzero states is said to be described by a primitive polynomial (see theory of Galois fields for the definition of primitive), and such polynomials can be found from tables [Bardell et al., 1987]. By connecting the output of each cell to an input of a circuit under test, the LFSR implements an ideal input generator, as it is inexpensive in its implementation and it provides the stimuli in pseudo-random order for either exhaustive or pseudo-exhaustive testing. LFSRs as Signature Analyzer If the leftmost cell of an LFSR is connected to an external input, as shown in Fig. 85.7, the LFSR can be used as a compactor [Bardell et al., 1987; Abramovici, 1992]. In general, the underlying operation of the LFSR is to compute polynomial division over a finite field, and the theoretical analysis of the effectiveness of signature analysis is based on this functionality. The polynomial describing the LFSR implementation is seen to be the divisor polynomial. The binary input stream can be seen to represent the coefficients (high order first) of a dividend polynomial. For example, if the input stream is 1001011 (bits are input left to right in time), the dividend polynomial is x 6 + x 3 + x + 1. After seven clock cycles for all the input bits to have entered the LFSR, the binary output stream exiting from the right denotes the quotient polynomial, while the last state of the cells in the LFSR denotes the remainder polynomial. In the process of computing a signature for testing the circuit, the input stream to the LFSR used as a compactor is the output stream from the circuit under test. At the end of the testing cycles, only the last state of the LFSR is examined and considered to be the compacted signature of the circuit. In most real cases, circuits have many outputs, and the LFSR is converted into a multiple-input shift register (MISR). A MISR is constructed by adding EXOR gates to the input of some or all the flip-flop cells; the outputs of the circuit are then fed through these gates into the compactor. The probability of aliasing for a MISR is the same as that of an LFSR; FIGURE 85.6Autonomous LFSR. ? 2000 by CRC Press LLC however, some errors are missed due to cancellation. This is the case when an error in one output at time t is canceled by the EXOR operation with the error in another output at time t + 1. Given an equally likely probability of errors occurring, the probability of error cancellation has been shown to be 2 1–m–N , where m is the number of outputs compacted and N is the length of the output streams. Given that the normal length of signatures used varies between k = 16 and k = 32, the probability of aliasing is minimal and considered acceptable in practice. In MISR, the length of the compactor also depends on the number of outputs tested. If the number of outputs is greater than the length of the MISR, algorithms or heuristics exist for combining outputs with EXOR trees before feeding them to the compactor. If the number of outputs is much smaller, various choices can be evaluated. The amount of aliasing that actually occurs in a particular circuit can be computed by full fault simulation, that is, by injecting each possible fault into a simulated circuit and computing the resulting signature. Changes in aliasing can be achieved by changing the polynomial used to define the compactor. It has been shown that primitive polynomials, essential for the generation of exhaustive input generators (see above), also possess better aliasing characteristics. Data Compaction with Linear Cellular Automata Registers LCARs are one-dimensional arrays composed of two types of cells: rule 150 and rule 90 cells [Cattell et al., 1996]. Each cell is composed of a flip-flop that saves the current state of the cell and an EXOR gate used to compute the next state of the cell. A rule 150 cell computes its next state as the EXOR of its present state and of the states of its two (left and right) neighbors. A rule 90 cell computes its next state as the EXOR of the states of its two neighbors only. As can be seen in Fig. 85.8, all connections in an LCAR are near-neighbor connections, thus saving routing area and delays (common for long LFSRs). Up to two inputs can be trivially connected to an LCAR, or it can be easily converted to accept multiple inputs fed through the cell rules. There are some advantages of using LCARs instead of LFSRs: first, the localization of all connections, and second, and most importantly, it has been shown that LCARs are much “better” pseudo-random pattern generators when used in autonomous mode, as they do not show the corre- lation of bits due to the shifting of the LFSRs. Finally, the better pattern distribution provided by LCARs as input stimuli has been shown to provide better detection for delay faults and open faults, normally very difficult to test. As for LFSRs, LCARs are fully described by a characteristic polynomial, and through it any linear finite state machine can be built either as an LFSR or as an LCAR. It is, however, more difficult, given a polynomial, to derive the corresponding LCAR, and tables are now used. The main disadvantage of LCARs is in the area overhead incurred by the extra EXOR gates necessary for the implementation of the cell rules. This is offset by their better performance. The corresponding multiple-output compactor is called a MICA. Summary Accessibility to internal dense circuitry is becoming a greater problem, and thus it is essential that a designer consider how the IC will be tested and incorporate structures in the design. Formal DFT techniques are FIGURE 85.7LFSR for signature analysis. FIGURE 85.8LCAR for signature analysis. ? 2000 by CRC Press LLC concerned with providing access points for testing (see controllability and observability in Section 85.2). As test pattern generation becomes even more prohibitive, probabilistic solutions based on compaction and using fault simulation are more widespread, especially if they are supported by DFT techniques and they can avoid the major expense of dedicated external testers. However, any technique chosen must be incorporated within the framework of a powerful CAD system providing semiautomatic analysis and feedback, such that the rule of ten can be kept under control: if one does not find a failure at a particular stage, then detection at the next stage will cost 10 times as much! Defining Terms Aliasing: Whenever the faulty output produces the same signature as a fault-free output. Built-in self-test (BIST): The inclusion of on-chip circuitry to provide testing. Fault coverage: The fraction of possible failures that the test technique can detect. Fault simulation: An empirical method used to determine how faults affect the operation of the circuit and also how much testing is required to obtain the desired fault coverage. I DD q testing: A parametric technique to monitor the current I DD that a circuit draws when it is in a quiescent state. It is used to detect faults which increase the normally low I DD . LFSR: A shift register formed by D flip-flops and EXOR gates, chained together, with a synchronous clock, used either as input pattern generator or as signature analyzer. MISR: Multiple-input LFSR. Off-line testing: Testing process carried out while the tested circuit is not in use. On-line testing: Concurrent testing to detect errors while circuit is in operation. Pseudo-random pattern generator: Generates a binary sequence of patterns where the bits appear to be random in the local sense (1 and 0 are equally likely), but they are repeatable (hence only pseudo-random). Random testing: The process of testing using a set of pseudo-randomly generated patterns. Sequential fault: A fault that causes a combinational circuit to behave like a sequential one. Signature analysis: A test where the responses of a device over time are compacted into a characteristic value called a signature, which is then compared to a known good one. Stuck-at fault: A fault model represented by a signal stuck at a fixed logic value (0 or 1). Test pattern (test vector): Input vector such that the faulty output is different from the fault-free output (the fault is stimulated and detected). Related Topic 23.2 Testing References M. Abramovici, M.A. Breuer and A.D. Friedman, Digital Systems Testing and Testable Design, Rockville, Md.: IEEE Press, 1992. P.H. Bardell, W.H. McAnney, and J. Savir, Built-In Test for VLSI: Pseudorandom Techniques, New York: John Wiley and Sons, 1987. K. Cattell and J.C. Muzio, “Synthesis of one-dimensional linear hybrid cellular automata,” IEEE Trans. Computer Aided Design, vol. 15, no. 3, pp. 325–335, 1996. N.H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley, 1993. T.W. Williams (Ed.), VLSI Testing, Amsterdam: North-Holland, 1986. Further Information The author would like to recommend reading the book by Abramovici et al. [1992] that, at the present time, gives the most comprehensive view of testing methods and design for testability. More information on deter- ministic pattern generation can also be found in Fault Tolerant Computing, edited by D.K. Pradhan, and for ? 2000 by CRC Press LLC newer approaches of random testing the book by Bardell et al. contains basic information. The latest state-of- the-art research is to be found mainly in proceedings of the IEEE International Test Conference. 85.2 Design for Test Bulent I. Dervisoglu Testing of electronic circuits, which has long been pursued as an activity that follows the design and manufacture of (at least) the prototype product, has currently become a topic of up-front investigation and commitment. Today, it is not uncommon to list the design for testability (DFT) features of a product among the so-called functional requirements in the definition of a new product to be developed. Just how such a major transfor- mation has occurred can be understood by examining the testability problems faced by manufacturing orga- nizations and considering their impact on time to market (TTM). The Testability Problem The primary objective of testing digital circuits at chip, board, or system level is to detect the presence of hardware failures induced by faults in the manufacturing processes or by operating stress or wearout mecha- nisms. Furthermore, during manufacturing, a secondary but equally important objective is to accurately determine which component or physical element (e.g., connecting wire) is faulty so that quick diagnosis/repair of the product becomes possible. These objectives are necessary due to imperfections in the manufacturing processes used in building digital electronic components/systems. All digital circuits must undergo appropriate level testing to avoid shipping faulty components/systems to the customer. Analog circuits may have minimum and maximum allowable input signal values (e.g., input voltage) as well as infinitely many values in between these that the component has to be able to respond to. Testing of analog circuits is often achieved by checking the circuit response at the specified upper and lower bounds as well as observing/quantifying the change of the output response with varying input signal values. On the other hand, the behavior of a digital system is characterized by discrete (as opposed to continuous) responses to discrete operating state/input signal permu- tations such that testing of digital circuits may be achieved by checking their behavior under every operating mode and input signal permutation. In principle this approach is valid. However, in practice, most digital circuits are too complex to be tested using such a brute force technique. Instead, test methods have been developed to test digital circuits using only a fraction of all possible test conditions without sacrificing test coverage. Here, test coverage is used to refer to the ratio of faults that can be detected to all faults which are taken into consideration, expressed as a percentage. At the present time the most popular fault model is the so- called stuck-at fault model that refers to individual nets being considered to be fault-free (i.e., good network) or considered to be permanently stuck at either one of the logic 1 or logic 0 values. For example, if the device under test (DUT) contains several components (or building blocks), where the sum of all input and output terminals (nodes) of the components is k, there are said to be 2k possible stuck-at faults, corresponding to each of the circuit nodes being permanently stuck at one of the two possible logic states. In general, a larger number of possible stuck-at faults leads to increased difficulty of testing the digital circuit. For the purpose of test pattern (i.e., input stimulus) generation it is often assumed that the circuit under test (CUT) is either fault-free or it contains only one node which is permanently stuck at a particular logic state. Thus, the most widely used fault model is the so-called single stuck-at fault model. Using this model each fault is tested by applying a specific test pattern that, in a good circuit, drives the particular node to the logic state which has the opposite value from the state of the fault assumed to be present in the faulty circuit. For example, to test if node v is stuck at logic state x (denoted by v/x or v-x), a test pattern must be used that would cause node v to be driven to the opposite of logic state x if the circuit is not faulty. Thus, the test pattern attempts to show that node v is not stuck at x by driving the node to a value other than x, which for a two-valued digital circuit must be the opposite of x (denoted by ~x). This leads to the requirement that to detect any stuck-at fault v/x, it is necessary to be able to control the logic value at node v so that it can be set to ~v. If the signal value at node v can be observed directly by connecting it to a test equipment, the particular fault v/x can be detected readily. However, in most cases, node v may be an internal node, which is inaccessible for direct ? 2000 by CRC Press LLC observation from outside the component package. In that case, it is necessary to create a condition where the value of the signal on an externally observable node, say node t, will be different for each of the two possible values that node v can take on, that is, node t shall be driven to logic state y or ~y depending upon whether node v is at logic state x or ~x, respectively. Note that x and y may represent the same or different logic states. The external pins of a component are the only means of applying the stimuli and observing the behavior of that component. During testing, a test pattern is used as the stimulus to detect the presence of a particular fault by causing at least one output pin of the component to take on a different value depending upon whether the targeted fault is present or not. Thus, a test pattern is used for controlling the circuit’s nodes so that the presence of a fault on a circuit node can be observed on at least one of the circuit’s external pins. Solving the dual problems of controllability and observability is the primary objective of all test methods. The logic-to-pin ratio of a digital circuit is a relative measure of the ratio of possible faults in the circuit to the number of signal pins (i.e., not including the constant power/ground pins) of that component. A large-value logic-to-pin ratio implies that logic states of a large number of circuit nodes must be controlled using a small number of external pins. As a result, conflicting requirements for controllability and observability become harder to satisfy, and the circuit is considered to be more difficult to test. Consider Fig. 85.9, which depicts a single (hypothetical) integrated circuit (IC) component and shows its internal circuitry which uses four NAND gates. The nodes of the circuit are numbered 1 through 12 and the external pins of the component are labeled A, B, and C. To detect if node 7 is stuck at logic 0 (i.e., 7/0), a test pattern must be found that sets node 7 (and hence, node 5) to the logic 1 state. This can be achieved by setting either or both of the external pins A and B to the logic 0 state. Furthermore, to observe (or deduce) the value of node 7 at the only externally visible circuit pin, C, it is necessary to create a condition where the logic state of node 12 becomes dependent on the value of node 7. The only path from node 7 to node 12 passes through node 10, and since node 10 is the output of a NAND gate the second input to that gate (i.e., node 6) must be set to the logic 1 state by setting input pin A to the logic 1 state. Therefore, the only possible test pattern for 7/0 is A = 1 and B = 0. At this point, we must still continue the analysis to see if indeed node 12 will reflect the value of node 7. With input terminals A and B set to logic 1 and logic 0, respectively, node 9 will be set to logic 0, which causes node 11 to become logic 1. With these settings, the value at node 12 will be determined by the value at node 10 and the test pattern is valid. Table 85.2 shows the values of all circuit nodes when this test pattern is applied to the circuit of Fig. 85.9. It should be evident from the simple example of a combinational circuit described above that test pattern generation for digital circuits can be very difficult and involved. The problem becomes much more complex when dealing with sequential circuits, where the internal state variables (i.e., bistable memory storage elements such as latches and flip-flops) must be treated as pseudo-inputs and pseudo-outputs that must be controlled and observed using the external pins of the component. In this case test patterns become test sequences that must be applied in precise order, and outputs must be observed only at prescribed times. Thus, the testing of sequential FIGURE 85.9Example logic circuit with internal node 7 stuck at 0 (7/0). TABLE 85.2 Test Pattern for Node 7/0 for the Circuit in Fig. 85.9 AB123456789101 12 C 101010111100111 good circuit 101010110 101 1 00 with fault 7/0 ? 2000 by CRC Press LLC circuits is much harder to achieve compared to the testing of combinational circuits. Computer programs, called automatic test pattern generation (ATPG) programs, have been developed for generating test patterns for combinational or sequential circuits. By far, the generation of test patterns for combinational circuits is better understood and automated than doing the same for sequential circuits. Before discussing the various techniques that may be used to improve testability of digital circuits, it is necessary to mention the related problem of determining test effectiveness. A typical digital system contains a very large number of possible stuck-at faults. This and the logical complexity of the circuits make it unacceptable to “guess” how effective the test patterns (or the diagnostic program) will be in detecting all possible faults. This problem is often approached in a formal manner by using a class of test tool called a fault simulator program. A fault simulator uses the given set of test patterns to simulate the given circuit first when there are no faults assumed present (i.e., good circuit simulation). Next, the circuit is simulated with the same set of test patterns, but this time the effects of each possible stuck-at fault are considered one at a time. For a given test pattern, and given stuck-at-type fault, if the output of the good circuit simulation differs from the output obtained during fault simulation, then the given fault will be detected by the given test pattern. This way, it is possible to determine the percentage of all possible stuck-at faults that may be present in a digital circuit which will be covered by the given set of test patterns. Most ATPG programs operate by picking a possible fault from among the possible faults, generating a specific test pattern that covers it, simulating the logic circuit with the newly generated test pattern to determine which other faults are incidentally covered by the same pattern, and continuing the process until all faults have been considered. Of the two related processes of test pattern generation and fault simulation, the latter is by far the more time-consuming one. A different approach is taken in some testability analysis tools whereby rather than determining which faults are covered by a given test pattern, the analysis program assigns a numeric value to indicate the degree of difficulty of controlling and observing the digital circuit’s nodes. This analysis, which can be done much more quickly compared to performing fault simulation, should be done prior to attempting to generate the test patterns for a circuit so that time will not be spent unnecessarily on digital circuits which are likely to present difficulties for the ATPG/fault-simulation process to deal with. Design for Testability Low-cost/high-volume manufacturing requires that product testability be considered up front since a product which is inherently hard to test will cost both time and money to achieve a desired level of quality. There are many steps that can be taken to improve the testability of digital circuits and systems. The following subsections describe some of the techniques that can be used. Ad-Hoc Techniques [Abramovici et al., 1990; Bardell et al., 1978] Circuit/System Reset Requirements. A simple and straightforward mechanism for resetting a digital circuit to a known state is an essential requirement for testability. It should be noted that the requirement is not only for having the reset function provided but further that it should be simple to execute. For example, applying a defined sequence of external signals to a circuit which must be synchronized with a free-running clock signal would not be considered a simple reset mechanism. Instead, keeping an external signal at some logic value for a minimum duration is a much more desirable approach. It is very desirable that the reset function be asynchronous (i.e., not require system clock pulses to execute) since during power-up a circuit may need to be reset even before free-running clock pulses can be started. Clock Control Requirements. Another very important requirement for implementing DFT is the ability to control the clocking of the internal logic of the digital circuit. If the external clock signal is gated with some other signals such that it is necessary to determine how to set these other signals to their required values to allow the externally applied clock pulse to reach the internal flip-flop clock terminals, then the ATPG program has another level of constraints to resolve in generating the test patterns. Furthermore, some of these additional requirements may pose difficulties in satisfying them during component and/or system testing. Most ATPG programs assume that once the test pattern has been applied to the pins of the component, the system’s response to that pattern can be captured by applying an external clock pulse which enables the internal flip-flops to ? 2000 by CRC Press LLC respond to the test pattern. Thus, the ATPG programs assume that the internal flip-flop clock inputs are controlled directly from an external pin of the component. This very desirable characteristic is often expressed by stating that externally applied clock pulses are not allowed to be gated by other signals before these reach the clock terminals of the internal flip-flops. A side benefit of this design rule is that it prevents glitches (i.e., undesirable pulses) which might be generated at the flip-flop clock terminals due to changing the other inputs to the clock gating circuit while the clock pulse is present. Managing “Unused“ Inputs of Components.When designing digital systems from existing components there may be inputs of those components that, for the current implementation, are not needed. For example, if a two-input AND gate is needed to implement a logic circuit on a printed circuit board, it may be possible to use one of the unused three-input AND gate elements from an IC package already present on that board. In this case, the unused third input of that AND gate must be connected to the logic 1 level in order that a three- input AND function may be implemented using the other two inputs to that gate. Thus, the unused input to the AND gate may be connected directly to the V cc (i.e, power supply) signal. Similarly, if a flip-flop contains unused preset or clear terminals, these may be tied off to their respective deasserted states. In many cases printed circuit boards are tested using an in-circuit tester which uses a bed-of-nails test fixture to make physical contact with selected nets on the board so that their values can be observed or controlled by the tester. For the in- circuit tester to control the value of a net it has to backdrive the output of the component which normally drives that net. Since IC components have limited output drive capabilities, the in-circuit tester can overcome the electrical drive from that component and can force that net to a value opposite the value which the driving IC is trying to achieve. By keeping such backdriving conditions to last only a very short period, damage to the opposing IC component is prevented. However, if the net is driven not by an IC but directly from the V cc or ground (Gnd) signals, then the in-circuit tester may not be able to overcome their drive. Furthermore, back- driving the V cc or Gnd levels would prevent the other IC components from being able to perform their normal functions. Instead, if the logic signals to such unused terminals are applied using pull-up or pull-down resistors when connecting these to the V cc or Gnd levels, respectively, these signals may be controlled by the in-circuit tester. For example, this way it becomes possible to set/reset a flip-flop value by using the normally “unused” preset/clear terminal of that flip-flop. Note that if the flip-flop contains both a preset and a clear input which are unused, these must be pulled up (or pulled down) through separate resistors so that each can be controlled by the in-circuit tester independent of the other. This is illustrated in Fig. 85.10. Synchronous versus Asynchronous Design Style.More than any other issue, discussions concerning synchro- nous versus asynchronous design style create the most disagreements concerning design for testability. Many logic designers who are experienced in using SSI and MSI IC chips have adapted a design style where synchronous (e.g., clocked) and asynchronous (e.g., self-timed) designs are freely mixed together. Using clocked flip-flops FIGURE 85.10Using pull-up resistor to tie off unused preset/clear inputs of flip-flops. ? 2000 by CRC Press LLC with asynchronous preset/clear inputs is a typical example of this design style. Similarly, building latches out of, say, cross-coupled NAND gates and using these as state variables in implementing finite-state machines used to be a very common technique. However, concerns about system initialization and pattern generation have made this style undesirable for implementing DFT. Indeed, most of the so-called structured design styles described below make it a requirement that all internal storage elements be constructed from clocked flip-flops, and feedback loops in combinational circuits are broken with the insertion of such flip-flops, along the feedback paths. Asynchronous circuits suffer from combinational circuit hazards that are glitches created as a result of delay differences along circuit paths. Some hazards may be prevented by constraining the manner (i.e., sequence) in which circuit inputs are allowed to be changed. Whereas such constraints may be met during regular system operation, often test pattern generation algorithms cannot take such constraints into account. Therefore, asynchronous logic may create severe problems during testing. Avoiding Redundant Logic.Technically speaking, redundancy is the only reason why a given stuck-at fault might not be detectable by any test. For example, if an INVERTER function is implemented by tying both inputs of a two-input NAND gate together, then a stuck-at 1 fault on either one of the inputs becomes undetectable since the output signal can still be determined correctly by the remaining nonfaulty input signal. This creates two problems. First, conventional ATPG programs might spend a lot of time trying to generate a test pattern for such a fault before they declare the fault untestable. Second, the presence of an undetectable fault can cause a detectable fault to become undetectable (it may also cause an undetectable fault to become detectable). For example, consider a parity checking circuit in which an existing stuck-at fault may cause the wrong parity to be generated, and the existence of a second fault may correct the parity and hence hide both failures. The remedy for these situations is to try to avoid redundancy in the first place, and when this is not possible provide additional circuit modes where the redundant circuits might be isolated. Alternately (or in addition) it may be useful to provide additional test points, as described below. Providing Test Points.A test point is an input or output signal to control or observe intermediate signals in a logic circuit. For example, if triple redundancy has been used to implement a fault-tolerant circuit, additional output signals might be provided so that signal values from the identical functional units become individually observable, improving the testability of the overall circuit. Similarly, control signals might be provided so that, during testing, outputs from some functional units may be forced into certain states which allow easier observation of the outputs from other circuits. Recommended sites for inserting test points include redundant nets, nets with large fan-outs, preset and clear inputs of flip-flops, nets that carry system clock signals, (at least some of the) inputs to logic circuit gates with large number of inputs (i.e., large fan-in), data and/or address lines of bus lines, as well as intermediate points in cascaded circuits (such as long ripple counters, shift registers). Logic Partitioning. Traditionally logic partitioning has been used as a strategy when the circuit is too large/complex for the test generation tools to handle. Thus, its objective is to reduce the number of circuit nodes that must be considered jointly in order to generate test patterns. The partitioning process identifies the logic cones, which are sections of logic receiving inputs from multiple input sources and generating a single output. Thus, a digital circuit would be broken into as many individual logic cones as there are individually observable output signals. Obviously, the logic cones may (and often do) overlap with each other since they share common input signals or intermediate signals generated from inside one partition and used in another partition. This is illustrated in Fig. 85.11(a), where two overlapping cones of logic are shown. Here, logic cones O 1 and O 2 contain primary inputs I 1 , I 2 , I 3 , I 4 and I 3 , I 4 , I 5 , I 6 , respectively. When either partition is dependent on more inputs than what the ATPG tools or the tester can accommodate, it is possible to insert an additional gate, controlled by a tester input in order to test each partition independently of the other. This is illustrated in Fig. 85.11(b), where an additional input pin I t has been added such that with I t set to logic 0 by the tester, it is possible to test either partition without requiring to control shared inputs I 3 or I 4 . Logic partitioning has become more important as a result of increased use of pseudo-exhaustive testing (to be described later). Testing Embedded Memory Blocks.A major testability problem arises when a regular-structure memory block such as random-access memory (RAM) or read-only memory (ROM) is embedded into a logic circuit. This creates three problems: ? 2000 by CRC Press LLC 1.Testing logic that is downstream from the RAM block (i.e., output of RAM block drives the downstream logic) is difficult since this requires setting the test pattern at the RAM outputs. This problem is usually solved by providing a bypass mode where data inputs to the RAM (or ROM) block are channeled directly to the RAM (or ROM) outputs without (or in addition to) being stored inside the RAM block. This way the RAM data outputs can be controlled by controlling the data inputs as desired. 2.Testing logic that is upstream from the RAM block (i.e., outputs from logic circuit are captured by the RAM block) is difficult since the observation point is the RAM block. That is, it is necessary to access the RAM block in order to observe the test results. This problem might be solved by improving the observability of the RAM inputs and/or making the RAM outputs more easily observable as well as providing the bypass capability. This way, inputs to the RAM might be bypassed directly to the RAM outputs where they may be observed. This may require adding an observe-only register to capture the RAM outputs. 3.Testing of the RAM block itself is difficult since controlling its inputs and observing its outputs require manipulating the upstream and downstream logic circuit blocks, which may be difficult to achieve. Solution to this problem involves providing adequate control of the RAM block inputs (data, address, and read/write control) as well as providing observability of the RAM outputs. In effect, the embedded RAM block can be made testable as if it was a stand-alone block where established memory test algorithms can be applied [Breuer and Friedman, 1976]. Figure 85.12 illustrates how to improve testability of an embedded RAM structure. Structured Techniques An alternate approach to improving the testability of digital circuits is to carry out the circuit design by following certain rules that, by construction, assure high testability of the resulting circuits. Since the main problem in achieving testability of a digital circuit is achieving adequate controllability/observability of its internal nodes, structured DFT approaches [Bardell and McAnney, 1978] follow strict design rules that are aimed at achieving this goal. Furthermore, most structured DFT approaches require/recommend additional design rules aimed at preventing incorrect circuit operation as a result of signal races and hazards. FIGURE 85.11(a) Logic partitioning with overlapping logic cones. (b) Adding an additional test point to reduce depen- dence on primary inputs. ? 2000 by CRC Press LLC Level-Sensitive Scan Design (LSSD).Level-sensitive scan design [Eichelberger and Williams, 1978] imposes strict rules on clock signal usage and allows implementing sequential behavior to be implemented only using the shift-register latch (SRL). In the first place, by not allowing any feedback involving combinational circuit elements alone, the LSSD approach prevents timing failures that might be present in purely asynchronous designs. Furthermore, rigid clocking rules are stated in order to prevent SRL data inputs from changing while the clock pulse(s) is (are) transitioning. Hence, the digital circuit is separated into two sections: (1) a robust (i.e., level-sensitive) multi-input/multi-output combinational circuit and (2) a set of SRL elements with which sequential behavior is implemented. In addition to their normal system interconnections each SRL is also connected to its two neighboring SRLs to form a shift-register structure. The serial shift input and shift output signals are labeled scan-in and scan-out, respectively, and treated as primary input/output terminals. Figure 85.13 FIGURE 85.12Providing testability in a design containing an embedded memory block. FIGURE 85.13(a) LSSD circuit model. (b) SRL block diagram. (c) SRL logic diagram. ? 2000 by CRC Press LLC shows an LSSD circuit model and the general form of an SRL. The significance of the shift-register (often referred to as the scan-register) structure is that, during testing, it allows each SRL’s value to be individually controllable and observable by shifting (i.e., scanning) a serial vector into/out of the scan register. Hence, the SRLs can be treated as pseudo-input/output terminals, and the testing of the digital circuit is reduced to that of a combinational circuit only. Figure 85.13(a) shows an LSSD circuit model, and the general form of an SRL is given in Fig. 85.13(b). A possible gate-level circuit implementation of an SRL is shown in Fig. 85.13(c). Among the most important LSSD design rules are the following: 1.All internal storage is implemented using SRLs. Each SRL operates such that the L1 latch accepts one or the other of the system data-in or the scan-in data values depending upon whether the system clk or the scan-in clk clock pulse is applied, respectively. The L2 latch accepts the L1 latch value when the scan- out clk clock pulse is applied. The L1 and L2 latches are stable (i.e., cannot change) when the clocks are off. 2.The SRL clocks system clk, scan-in clk, and scan-out clk must be controlled from primary circuit terminals and must be operated in nonoverlapping fashion. This eliminates dependency on minimum circuit delay and assures hazard-free (i.e, level-sensitive) operation. 3.System data-out from SRL 1 may feed the system data-in terminal of SRL 2 only if the system clk which feeds SRL 1 does not overlap with the system clk which feeds SRL 2 . This rule prevents the data input to a latch from changing while its clock signal is transitioning. 4.All SRLs are interconnected into one or multiple shift registers by connecting the scan-out terminal from one SRL to the scan-in terminal of the next one in series. If multiple shift registers are implemented, each must be capable of being shifted simultaneously with the others and must have its own scan-in and scan-out primary terminals. Scan Path.The scan-path [Funatsu et al., 1975] approach can be seen as a generalization of the LSSD approach since it follows the same principles but uses standard D-type flip-flops as the storage elements instead of the SRLs. The scannable flip-flops can be implemented using dual-ported latches (similar to the L1 latch in the SRL) or using a multiplexor to select between the scan-in and system data-in signals to feed the D input of a standard D-type flip-flop, as shown in Fig. 85.14. Scan/Set Logic.Scan/set [Stewart, 1977] is another form of implementing scan technology whereby the sequential circuit structure is separated from its accompanying scan/set register. This is illustrated in Fig. 85.15. A variation on this scheme is the so-called shadow-register concept that has been implemented in some off- the-shelf IC components [AMDI, 1987]. Random-Access Scan.Random-access scan [Ando, 1980] uses a technique akin to addressing locations in a memory (e.g., RAM) block in order to make the states of all storage elements controllable and observable from primary input/output terminals. Using this approach, each storage element is made individually addressable (i.e., accessible) so that in order to control and/or observe the value of an individual storage element it is not necessary to shift in/shift out all other storage elements as well. Figure 85.16(a) shows the general model of a digital circuit employing the random-access scan approach. A possible gate-level circuit implementation of an addressable latch is given in Fig. 85.16(b). FIGURE 85.14Model of a digital circuit with scan path. ? 2000 by CRC Press LLC Using this approach, each storage element in the circuit is given a unique x/y address and the decoded address signals are connected to the x/y address inputs of the latches. As seen in the circuit of Fig. 85.16(b), each latch can then be individually written into using the scan-in terminal or its output can be observed using the scan- out terminal, provided that the pair of x/y address lines connected to the current latch are both asserted (i.e., FIGURE 85.15 Generic scan/set circuit design. FIGURE 85.16 (a) General model for digital circuit implementing random-access scan. (b) Logic diagram for addressable latch. ? 2000 by CRC Press LLC set to logic 1). Furthermore, whereas it is also necessary to apply the scan-in clk in order to write into the latch, no clock is necessary to observe the latch output. This is a convenient feature that allows the latch values to be selectively observable even while the regular system operations are being executed. The scan-out values from the individual latches are combined together into a single AND gate and brought out to a primary output terminal of the circuit. This arrangement works since for any given address only one of the addressable latches will be selected and the scan-out from all other latches will be forced to the logic 1 state. On the other hand, a disadvantage of this approach is that before addressing each latch its proper address must first be applied to the circuit. Boundary Scan.Unlike the other scan-based techniques described above, boundary scan [IEEE, 1990] is intended primarily for testing the board-level interconnections among the IC components on a printed circuit board (PCB). In effect, boundary scan is a special form of scan path that is implemented around every I/O pin of an IC component in order to provide controllability and observability of the I/O pin values during testing. Test control signals provided by an on-chip controller are used to disable the boundary-scan cells during regular system operation so that signal values can flow in/out of the IC component without interference from the test circuits. During testing, output pin values can be controlled using values preloaded into the boundary-scan register. Similarly, signal values received on the input pins can be captured into the boundary-scan register and subsequently shifted out to be observed on an external tester. Boundary scan has become an important tool in achieving design for testability following the adoption of the IEEE 1149.1 Test Access Port and Boundary-Scan Architecture in 1990. The IEEE 1149.1 Standard defines a mandatory four-pin (plus an optional fifth pin) test access port (TAP) for providing the interface between the IC component and a digital tester. TAP signals comprise test data input (TDI), test data output (TDO), test clock (TCK), and test mode select (TMS) plus an optional asynchronous tap reset (TRST*) signal. The overall IEEE 1149.1 test architecture (see Fig. 85.17) includes: ?The TAP ?The TAP controller ?The instruction register (IR) ?A group of mandatory and optional test data registers (TDRs) The TAP controller is characterized by a 16-state finite-state machine (FSM) whose behavior is defined by the IEEE 1149.1 Standard. State transitions of the TAP FSM are controlled by the TMS input line and the dedicated test clock, TCK. Figure 85.18 shows the state-transition diagram for the TAP FSM. FIGURE 85.17Architecture of IEEE 1149.1 boundary-scan standard. ? 2000 by CRC Press LLC A most important test data register defined by the IEEE 1149.1 Standard is the boundary-scan register that has individual cells associated with each I/O pin of the IC component. Mandatory and permissible features of the boundary-scan register cells are defined by the standard. In addition, a special single-bit register called the BYPASS register has been provided to furnish a more efficient way to shift data through IC components when multiple ICs are chained together by connecting the TDO output from one component to the TDI input of another. Another mandatory feature of the IEEE 1149.1 Standard is the instruction register and an associated list of mandatory/permissible instructions that govern the behavior of the IC component during testing. The three mandatory instructions are called SAMPLE/PRELOAD, BYPASS, and EXTEST. SAMPLE allows taking a snap- shot of the normal operation of the IC, whereas PRELOAD is used for shifting the captured values out while new values are loaded into the boundary-scan register. BYPASS allows shortening the (electrical) distance between the TDI and TDO pins by providing a single-bit register as a shortcut during scan operations involving multiple IC components that are connected in series. EXTEST is the “workhorse” instruction that allows driving the signal values on the component’s output pads from the boundary register while capturing the input values into their respective cells in the boundary register. This is followed by shifting the captured values out (using the TDO output) while simultaneously shifting in the new driving values (using the TDI input). An alternative to using boundary scan is to use a “traditional” in-circuit tester that uses a special “bed-of- nails” fixture. In this approach [Parker, 1987], every net on a PCB would be probed using a tester pin which comes in physical contact with that net such that the current signal value of the net can be observed by the tester. The tester can also be used to control the signal values of the individual nets by injecting appropriate currents through the tester pins. However, since each net is already connected to an output pin of a component on the PCB, this approach amounts to backdriving the output drivers of IC components and therefore poses a potential risk of damage to the IC components. This approach is becoming more difficult and/or costly to implement as the number of nets goes up and IC pin spacing is reduced. Furthermore, due to fixturing difficulties, double-sided PCBs cannot be tested in this manner. The IEEE 1149.1 boundary-scan standard [IEEE, 1990] helps solve these problems by providing convenient direct access to the I/O pins of an IC component without requiring the traditional bed-of-nails fixture. The “CrossCheck” Technique. The CrossCheck approach [Gheewala, 1989] uses cells with built-in test points to observe critical signal values. The test points are connected to an underlining grid structure using very small FETs called cross-point switches. An on-chip test control circuit generates the necessary signals to address the individual probe lines and capture the results in a multi-input signature register (MISR). Test patterns can be FIGURE 85.18 State-transition diagram for the TAP FSM. ? 2000 by CRC Press LLC generated externally or by using an on-chip pattern generator, and the final test signature (i.e., contents of MISR) can be accessed using dedicated test pins, such as by providing an IEEE 1149.1 TAP (see previous subsection). Figure 85.19 shows how the CrossCheck technique is implemented on an ASIC. CrossCheck methodology provides a high degree of observability of the ASIC. Since it is not possible to provide observability of all signals of a design, careful analysis must be performed to determine the most effective points for inserting the cross-point switches. Similarly, the size of the grid structure for the probe lines might be chosen to be design-dependent. However, in many instances it may be better to implement the probe lines as part of the IC master slice in order to reduce the amount of customization to a minimum. The benefit offered by the CrossCheck technique is due to the potential for the reduced number of test patterns necessary to test an ASIC. This is due to the fact that as observability of internal nodes is increased it becomes easier to generate efficient test patterns which can detect many faults simultaneously. Furthermore, increased observability of internal nodes also improves diagnosability and may help determine the root cause of a failure sooner. On the negative side, the CrossCheck technique does not help improve controllability of internal nodes as achieved using scan-path techniques. Also, a primary disadvantage of the CrossCheck meth- odology is area penalty due to routing channels that must be set aside for the grid structure. Furthermore, added capacitance of the cross-point switches may affect performance, especially in high-speed applications. In addition, since the technique offers very good observability but no controllability of the internal nodes, it lacks the advantage offered by scan-based approaches for system debug and internal path-delay testing [Der- visoglu and Stong, 1991]. However, recent advances have been made that improve the controllability of internal nodes using the CrossCheck technique in gate-array ICs. FIGURE 85.19(a) Cross-point switch implementation. (b) Overview of the CrossCheck technique. ? 2000 by CRC Press LLC Built-in Self-Test (BIST) Techniques.The term built-in self-test (or BIST) is a generic name given to any test technique in which an external test resource (e.g., component tester) is not needed to apply test patterns and check a circuit’s response to those patterns. This implies that the test patterns must be preloaded into the target device or be generated by the target device itself, in real time. For example, dedicating a section of an IC component for implementing a ROM-based sequencer to apply prestored patterns to test another section of that IC would be classified as a BIST technique. It is often more cost effective to generate the test patterns in real time (i.e., during testing), but in general it is not possible to develop real-time test pattern generation techniques that generate arbitrarily selected test patterns without additionally generating unnecessary ones. Note that whereas storing the test patterns in a ROM might be acceptable in some cases, the size of ROM necessary to store the test patterns prevents this technique being used for implementing BIST in large/complex digital circuits. One approach to test vector generation is to ignore the specifics of the target circuit and enumerate all possible permutations of inputs. Thus, using exhaustive testing, an n-input combinational logic cone would be tested by checking its response to all 2**n permutations of input values. In this case, a binary counter can be used as the test pattern generator (TPG). Other, more efficient counter forms (such as a maximal-length linear feedback shift register, LFSR) may also be used as the TPG. An LFSR is a special kind of circular-shift register where the serial data input is determined by an EXCLUSIVE-OR function of some of the bit positions. Bit positions which are included in the feedback EXCLUSIVE-OR function are referred to as the tap positions. For any given degree (i.e., number of bits) n of LFSR there is at least one set of tap positions that result in the LFSR going through all nonzero n-bit permutations when it is started in any nonzero state. An LFSR that can go through all 2**n states is called a maximal-length LFSR. Figure 85.20 shows a 3-bit maximal-length LFSR and the state sequence that it produces. Exhaustive testing guarantees that all detectable faults which do not transform a combinational circuit into a sequential circuit will be detected. Depending upon the clock frequency, this approach becomes impractical to apply when the number of input variables goes up (usually above 22) [McCluskey, 1984]. In cases where the number of test patterns necessary to achieve exhaustive testing is too large to be applicable, a related technique, called pseudo-random testing, may be used. Pseudo-random testing achieves many of the benefits of exhaustive testing but requires much fewer test patterns. This is achieved by generating the test patterns in random fashion from among the 2**n possible patterns. However, the random generation of test patterns is done using a deterministic algorithm that produces test patterns in repeatable sequence. Before pseudo-random testing is chosen, it is necessary to examine the pseudo-random test resistance of the circuit. For example, if 500,000 pseudo-random test patterns are applied to a 20-input AND gate, there is only a 0.00004% probability that an essential test pattern (which sets all 20 inputs to logic 1) will be included among them. Yet another related technique is to use pseudo-exhaustive testing that aims at breaking a circuit into separate partitions and testing each partition exhaustively [Barzilai et al., 1985; Dervisoglu, 1985; Bardell and McAnney, 1984]. Pseudo-exhaustive testing uses the same techniques used in exhaustive testing for testing the individual partitions without generating test patterns that cover the entire circuit. Mathematical considerations for pseudo- random/pseudo-exhaustive testing are too complex to describe here. The following example is presented for illustration purposes only. Figure 85.21 depicts the combinational portion of a digital circuit consisting of a number of overlapping logic cones that each produce a single output signal. All inputs are assumed to be FIGURE 85.20Three-bit maximal-length LFSR. ? 2000 by CRC Press LLC connected to scannable flip-flops (i.e., pseudo-inputs) or to primary input pins of the component such that all inputs are 100% controllable either by controlling the values in the flip-flops or the primary input pins. All flip-flops are assumed to be scannable and are arranged into a single scan path such that the logic cones have n or fewer inputs all of which lie within k consecutive bits along the scan path. Outputs from the individual logic cones connect (not shown here) to the inputs of flip-flops and/or primary output pins. Thus, all logic cone outputs are also 100% observable. Now, assume that the serial output from the LFSR shown in Fig. 85.20 is connected as the “scan-in” input to the scan-path register shown in Fig. 85.21. In this case any consecutive 3-bit partition of the scan-path register will go through the same state sequence as the LFSR itself, delayed from it by the number of flip-flops between that partition and the output bit of the LFSR. For example, the third logic cone that has inputs from flip-flops 4, 5, and 6 will see all input permutations except the all-zeros case which can be applied separately as a special case. On the other hand, the first logic cone, with inputs from flip- flops 1, 2, and 4, will not receive all possible nonzero permutations of three input variables. This is because the first logic cone receives its three inputs from three nonconsecutive positions of the scan-path register. In this case only input permutations that have even parity across positions 1, 2, and 4 will be received by the first logic cone. Furthermore, the fourth logic cone that also receives inputs from three nonconsecutive bit positions which are 4 bits apart will receive all 3-bit nonzero input permutations. Analysis of which set of input permutations may be generated across nonconsecutive n bits of a scan-path register which receives the outputs from an mth degree (m 3 n) LFSR is based on linear dependence and is outside the scope of this section. However, the problem may also be approached statistically by choosing the degree of the LFSR to be higher than n but smaller than k which is the largest span of inputs to any logic cone. For example, in Fig. 85.21 the degree of the LFSR may be chosen as 4. In this case, the probability that a logic cone which has 4 or fewer inputs separated by k bits (here, k = 5) may be calculated [Lempel and Cohn, 1985]. It should be noted that a logic cone may be tested in full even when it has not received all 2**n input permutations. BIST also requires ability to capture the test results without the need for an external tester. This is often achieved by using a multi-input signature register (MISR) to capture individual test results and compress these into an overall value called the test signature. Figure 85.22 shows a sample signature register that can compress test results captured from four separate outputs into a single 4-bit signature. Provided that the test circuit has deterministic behavior, a signature register can be started in a given starting state, and its final value may be compared to a known good signature to determine pass/fail status. However, compressing test results into a single overall signature may prevent proper fault detection if multiple erroneous outputs (which may result FIGURE 85.21Overlapping logic cones connected to a common scan path. FIGURE 85.22A four-bit parallel-input signature register. ? 2000 by CRC Press LLC from the same fault being detected on multiple test vectors) causes the final test signature to be correct even though interim signatures were wrong. The probability that a faulty circuit signature will be the same as the good circuit signature is known as aliasing probability. It can be shown that if the test length is sufficiently long, aliasing probability diminishes toward 2 -t , where t is the number of bits of the signature register [Dervi- soglu, 1985]. The two constructs of LFSR and the MISR can be merged into a single multipurpose register in a built-in logic block observation (BILBO) approach [Konemann et al., 1979] where each register can have multiple modes of operation including the LFSR mode, MISR mode, SCAN mode, and NORMAL mode. In this case an on- chip test-control circuit may be used to control the modes of operation of the BILBO registers so that, in turn, each register is used as a test pattern generator or signature register to test a digital component. Figure 85.23 illustrates how to use the BILBO scheme in a stepwise fashion to test a large digital circuit. Path-Delay Testing Path-delay testing is aimed at testing whether a given component/system operates at a specified performance level that is often measured as the maximum system clock frequency. For example, the lower bound for the maximum clock frequency which a microprocessor IC is specified that it can reach needs to be verified. However, due to the very large number of different operations that a microprocessor can perform it is not practical to verify correct behavior of such a component operating at maximum clock frequency for every possible single operation or sequence of operations that it is designed to perform. On the other hand, it may be possible to examine the structure of the design to discover its logic paths and verify that signals can be propagated along FIGURE 85.23Using BILBO technique to partition and test a large circuit. (a) Testing combinatorial circuit C 1 . (b) Testing combinatorial circuit C 2 . ? 2000 by CRC Press LLC these paths within a specified propagational delay time between the initiation of a signal transition at the beginning of the path and the arrival of the final values at the end of that path. This is called path-delay testing. A modern IC component with typical complexity would contain many hundreds of thousands of logic paths, so that it becomes impractical to test all of them for at-speed operation. All synchronous digital circuits are designed so that there is a fixed clock period resulting from the use-constant frequency clock signals to time their operation. Obviously, the clock period constitutes an upper bound for the propagational delay through any logic path, since otherwise clock pulses may arrive at the flip-flops while their data input signals may still be transitioning. On the other hand, propagational delay through some logic paths may be very close to this upper bound (i.e., clock period) value whereas others may have more slack in them. It is therefore important to identify the critical paths and perform path-delay testing on these. Hence path-delay testing can be broken into the two phases of critical-path selection and path-delay test pattern generation. Several different approaches can be used in identifying the critical paths, including: 1.Select sufficiently large number of paths selected at random from a list of all logic paths. 2.Calculate worst-case timing for all logic paths and select a certain percentage of the slowest paths. 3.First identify certain key nodes and then select paths that pass through those nodes using either of the two approaches listed in (1) and (2) above. The more challenging problem is to generate the test patterns to verify that none of the signal propagations along a given logic path require longer than the clock-period time to complete. A path-delay test pattern is a pair of patterns that generates the desired signal transition(s) and provides the sensitization of the signal paths whereby the generated transition(s) is (are) sensitized through the combinational circuit to the input of a flip- flop where it will be captured when the system clock is applied. For example, Fig. 85.24 shows a combinational circuit and identifies a specific signal path for which the path delay is to be measured. To determine the appropriate path-delay test patterns, a dummy AND gate is first added to the circuit as shown. An input to the AND gate is derived from the output of the combinational circuit through which the input signal transition is to be propagated. This signal is used in its true or complemented form depending upon whether the final value of the signal transition is a logic 1 or logic 0, respectively. Other inputs to the dummy AND gate come from all remaining inputs of gates through which the desired signal transitions must flow. If the desired signal transition is flowing through an AND or NAND gate, the remaining inputs of these gates are also fed to the inputs of the dummy AND gate, whereas if the desired signal transitions flow through OR or NOR gates, their remaining inputs are inverted and then connected to the inputs of the dummy AND gate. The dummy AND gate is not actually implemented as part of the combinational logic but rather acts as a convenient place to FIGURE 85.24Circuit example to illustrate path-delay test pattern generation (all flip-flops are clocked using a common clock signal that has not been shown). ? 2000 by CRC Press LLC collect all the necessary conditions for sensitizing the transitions. For example, in the example given above the first pattern requires input flip-flops A, B, and C all to be set to the logic 1 value in order to sensitize a low-to- high transition at the D input, whereas the second test pattern requires A, B, and C all to remain at logic 1 while D is changed from logic 0 to the logic 1 value. This way the transitions created on input D will travel through the identified signal path to reach the destination flip-flop Z. Path-delay test patterns become much easier to generate and also apply to a circuit if the circuit is designed using scannable flip-flops that are additionally capable of storing two arbitrarily selected values in them. This can be done in such a fashion that the initial value available at the flip-flop output will be replaced by the second value when a first clock pulse is applied, and the flip-flop will revert to its normal mode of operation before the second clock pulse is applied. This way the pair of test patterns that form a path-delay test are first loaded into the flip-flops (using scan) and then two clock pulses are applied at speed. The final result captured by the second clock pulse is then scanned out and examined to determine pass/fail status. It is also possible to get an actual measurement of the path delays by repeating the same test over and over again while systematically reducing the time distance between the two clock pulses to determine the minimum separation of the two clock pulses required for proper operation. Figure 85.25 shows a modified LSSD latch design [Malaiya and Narayanaswamy, 1983] that can be used to enable path-delay testing as described above. Using this design, it is possible to load any two arbitrary test vectors to the combinational circuit in rapid succession. First, test vector Q 1 , Q 2 ,…,Q n would be scanned into the L1 latches outputs by using clocks C 3 and C 2 . Next, the test vector would be moved into the L2 latches by applying a single C clock. This way the flip-flop outputs would be set to their initial values defined by Q 1 , Q 2 ,…,Q n . Following this, the second test vector Y 1 , Y 2 ,…,Y n would be scanned into the L1 latches using clock signals C 3 and C 2 . Now applying the C clock causes the first test vector (Q i ) to be replaced by the second test vector (Y i ), and if the C 1 clock is applied next, the response of the combinational circuit will be captured in the L1 latches. This way, the minimum delay between the clock signals C and C 1 that is necessary to allow the signals to propagate through the combinational circuit can be determined. Other flip-flop designs with built- in features to support double-strobe testing are also possible [Dervisoglu and Stong, 1991]. A different and more difficult-to-use approach for generating test patterns for path-delay measurement is to perform scan-in to load the internal flip-flops with a special pattern that prior circuit analysis will have determined will be transformed into the actually intended test pattern when the first functional clock pulse is FIGURE 85.25Using a three-latch flip-flop design to enable path-delay testing. ? 2000 by CRC Press LLC applied. The circuit analysis required to use this approach amounts to performing simulation in reverse time flow to determine what state the device under test should be placed in (using scan) so that its next state corresponds to the desired test pattern. Future for Design for Test Present-day trends for striving to achieve shorter time to market while at the same time meeting competitive cost demands are going to continue into the foreseeable future. Design for testability is one of several areas that manufacturers from IC components to complete systems are paying increased emphasis to in order to meet their product goals. Twenty years ago some product managers considered testing as being necessary to weed out the bad from the good but did not consider DFT to be adding value to a product. However, since testing is essential, the value of DFT is seen in reducing the cost of an essential item. Hence DFT adds value to a product at least by an amount equal to the savings in test costs that it brings about. Furthermore, DFT improves time to market by making it possible to identify initial production problems at an earlier point in time. For example, initial productions of high-performance ASIC components may contain flaws that prevent their at-speed operation under certain circumstances. If these flaws are not discovered in a timely manner, they may turn into “showstopper” issues causing serious delays in revenue shipments of products. Whereas no “guaranteed” solutions exist to prevent and/or find a solution for all types of problems, design for testability is a rapidly maturing field of digital design. Defining Terms Boundary scan: A technique for applying scan design concepts to control/observe values of signal pins of IC components by providing a dedicated boundary-scan register cell for each signal I/O pin. Built-in self-test (BIST): Any technique for applying prestored or real-time-generated test cases to a subcir- cuit, IC component, or system and computing an overall pass/fail signature without requiring external test equipment. Path-delay testing: Any one of several possible techniques to verify that signal transitions created by one clock event will travel through a particular logic/path in a subcircuit, IC component, or system and will reach their final steady-state values before a subsequent clock event. Pseudo-random testing: A technique that uses a linear feedback shift register (LFSR) or similar structure to generate binary test patterns with statistical distribution of values (0 and 1) across the bits; these patterns are generated without considering the implementation structure of the circuit to which they will be applied. Scan design: A technique whereby storage elements (i.e., flip-flops) in an IC are connected in series to form a shift-register structure that can be entered into a test mode to load/unload data values to/from the individual flip-flops. Related Topic 23.2 Testing References M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design, Rockville, Md.: Computer Science Press, 1990. Advanced Micro Devices Inc. [AMDI], “Am29C818 CMOS Pipeline Register with SSR Diagnostics,” product specification, Bus Interface Products Data Book, 1987, pp. 47–55. H. Ando, “Testing VLSI with random access scan,” in digest of papers, COMPCON, February 1980, pp. 50–52. P. H. Bardell and W. H. McAnney, “Parallel pseudorandom test sequences for built-in test,” in Proc. International Test Conference, October 1984, pp. 302–308. P. H. Bardell, W. H. McAnney, and J. Savir, Built-In Test for VLSI. Pseudorandom Techniques, New York: Wiley, 1978. ? 2000 by CRC Press LLC Z. Barzilai, D. Coppersmith, and A. L. Rosenberg, “Exhaustive generation of bit patterns with applications to VLSI self-testing,” IEEE Trans. on Computers, vol. C-32, no. 2, pp. 190–194, February 1985. M. A. Breuer and A. D. Friedman, Diagnosis and Reliable Design of Digital Systems, Rockville, Md.: Computer Science Press, 1976, pp. 139–146, 156–160. B. I. Dervisoglu, “VLSI self-testing using exhaustive bit patterns,” in Proc. IEEE International Conference on Computer Design, October 1985, pp. 558–561. B. I. Dervisoglu and G. E. Stong, “Design for testability: Using scanpath techniques for path-delay test and measurement,” in Proc. International Test Conference, October 1991, pp. 364–374. E. B. Eichelberger and T. W. Williams, “A logic design structure for LSI testability,” Journal of Design Automation and Fault-Tolerant Computing, vol. 2, no. 2, pp. 165–178, 1978. S. Funatsu, N. Wakatsuki, and T. Arima, “Test generation systems in Japan,” in Proc. 12th Design Automation Symposium, June 1975, pp. 114–122. T. Gheewala, “CrossCheck: A cell based VLSI testability solution,” in Proc. 26th Design Automation Conference, 1989, pp. 706–709. “IEEE Standard Test Access Port and Boundary-Scan Architecture,” IEEE Std. 1149.1-1990, May 1990. B. Konemann, J. Mucha, and G. Zwiehoff, “Built-in logic block observation technique,” in digest of papers, International Test Conference, October 1979, pp. 37–41. A. Lempel and M. Cohn, “Design of universal test sequences for VLSI,” IEEE Trans. on Information Theory, vol. IT-31, no. 1, pp. 10–17, 1985. Y. K. Malaiya and R. Narayanaswamy, “Testing for timing faults in synchronous sequential integrated circuits,” in Proc. International Test Conference, 1983, pp. 560–571. E. J. McCluskey, “Verification testing. A pseudoexhaustive test technique,” IEEE Trans. on Computers, vol. C-33, no. 6, pp. 541–546, June 1984. K. P. Parker, Integrating Design and Test, New York: IEEE Computer Society Press, 1987. J. H. Stewart, “Future testing of large LSI circuit cards,” in Proc. Semiconductor Test Symposium, Cherry Hill, N.J., October 1977, pp. 6–15. Further Information An excellent treatment of design for testability topics is found in Abramovici et al. [1990]. Also, Breuer and Friedman [1976] provide a very good treatment of pseudo-random test topics. C. M. Maunder and R. E. Tulloss (The Test Access Port and Boundary-Scan Architecture, IEEE Computer Society Press Tutorial, 1990) provide a user’s guide for boundary-scan and the IEEE 1149.1 Standard. B. I. Dervisoglu (“Using Scan Technology for Debug and Diagnostics in a Workstation Environment,” in Proc. International Test Conference, 1988, pp. 976–986) provides a very good example of applying DFT techniques all the way from the IC component level to the system level. Also, B. I. Dervisoglu (“Scan-Path Architecture for Pseudorandom Testing,” IEEE Design & Test of Computers, vol. 6, no. 4, pp. 32–48, August 1989) describes using pseudo-random testing at the system level. Similarly, P. H. Bardell and M. J. Lapointe (“Production Experience with Built-in Self-Test in the IBM ES/9000 System,” in Proc. International Test Conference, October 1991, pp. 28–36) describe application of BIST for testing a commercial product at the system level. ? 2000 by CRC Press LLC