电子工程师手册（英文版二）：ch024

Soclof, S., Watson, J., Brews, J.R. “Transistors” The Electrical Engineering Handbook Ed. Richard C. Dorf Boca Raton: CRC Press LLC, 2000 24 Transistors 24.1Junction Field-Effect Transistors JFET Biasing?Transfer Characteristics?JFET Output Resistance?Source Follower?Frequency and Time-Domain Response?Voltage-Variable Resistor 24.2Bipolar Transistors Biasing the Bipolar Transistor?Small-Signal Operation?A Small- Signal Equivalent Circuit?Low-Frequency Performance?The Emitter-Follower or Common-Collector (CC) Circuit?The Common-Emitter Bypass Capacitor C E ?High-Frequency Response?Complete Response?Design Comments?Integrated Circuits?The Degenerate Common-Emitter Stage?The Difference Amplifier?The Current Mirror?The Difference Stage with Current Mirror Biasing?The Current Mirror as a Load 24.3The Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) Current-Voltage Characteristics?Important Device Parameters?Limitations upon Miniaturization 24.1 Junction Field-Effect Transistors Sidney Soclof A junction field-effect transistor, or JFET, is a type of transistor in which the current flow through the device between the drain and source electrodes is controlled by the voltage applied to the gate electrode. A simple physical model of the JFET is shown in Fig. 24.1. In this JFET an n-type conducting channel exists between drain and source. The gate is a p + region that surrounds the n-type channel. The gate-to-channel pn junction is normally kept reverse-biased. As the reverse bias voltage between gate and channel increases, the depletion region width increases, as shown in Fig. 24.2. The depletion region extends mostly into the n-type channel because of the heavy doping on the p + side. The depletion region is depleted of mobile charge carriers and thus cannot contribute to the conduction of current between drain and source. Thus as the gate voltage increases, the cross-sectional areas of the n-type channel available for current flow decreases. This reduces the current flow between drain and source. As the gate voltage increases, the channel gets further constricted, and the current flow gets smaller. Finally when the depletion regions meet in the middle of the channel, as shown in Fig. 24.3, the channel is pinched off in its entirety between source and drain. At this point the current flow between drain and source is reduced to essentially zero. This voltage is called the pinch-off voltage, V P . The pinch-off voltage is also represented by V GS (off) as being the gate-to-source voltage that turns the drain-to- source current I DS off. We have been considering here an n-channel JFET. The complementary device is the p-channel JFET that has an n + gate region surrounding a p-type channel. The operation of a p-channel JFET is the same as for an n-channel device, except the algebraic signs of all dc voltages and currents are reversed. We have been considering the case for V DS small compared to the pinch-off voltage such that the channel is essentially uniform from drain to source, as shown in Fig. 24.4(a). Now let’s see what happens as V DS increases. As an example let’s assume an n-channel JFET with a pinch-off voltage of V P = –4 V. We will see what happens Sidney Soclof California State University, Los Angeles Joseph Watson University of Wales, Swansea John R. Brews The University of Arizona ? 2000 by CRC Press LLC for the case of V GS = 0 as V DS increases. In Fig. 24.4(a) the situation is shown for the case of V DS = 0 in which the JFET is fully “on” and there is a uniform channel from source to drain. This is at point A on the I DS vs. V DS curve of Fig. 24.5. The drain-to-source conductance is at its maximum value of g ds (on), and the drain-to- source resistance is correspondingly at its minimum value of r ds (on). Now let’s consider the case of V DS = +1 V, as shown in Fig. 24.4(b). The gate-to-channel bias voltage at the source end is still V GS = 0. The gate-to-channel bias voltage at the drain end is V GD = V GS –V DS = –1 V, so the depletion region will be wider at the drain end of the channel than at the source end. The channel will thus be narrower at the drain end than at the source end, and this will result in a decrease in the channel conductance g ds and, correspondingly, an increase in the channel resistance r ds . So the slope of the I DS vs. V DS curve that corresponds to the channel conductance will be smaller at V DS = 1 V than it was at V DS = 0, as shown at point B on the I DS vs. V DS curve of Fig. 24.5. In Fig. 24.4(c) the situation for V DS = +2 V is shown. The gate-to-channel bias voltage at the source end is still V GS = 0, but the gate-to-channel bias voltage at the drain end is now V GD = V GS – V DS = –2 V, so the depletion region will now be substantially wider at the drain end of the channel than at the source end. This leads to a further constriction of the channel at the drain end, and this will again result in a decrease in the channel conductance g ds and, correspondingly, an increase in the channel resistance r ds . So the slope of the I DS vs. V DS curve will be smaller at V DS = 2 V than it was at V DS = 1 V, as shown at point C on the I DS vs. V DS curve of Fig. 24.5. In Fig. 24.4(d) the situation for V DS = +3 V is shown, and this corresponds to point D on the I DS vs. V DS curve of Fig. 24.5. When V DS = +4 V, the gate-to-channel bias voltage will be V GD = V GS – V DS = 0 – 4 V = –4 V = V P . As a result the channel is now pinched off at the drain end but is still wide open at the source end since V GS = 0, as shown in Fig. 24.4(e). It is very important to note that the channel is pinched off just for a very short distance at the drain end so that the drain-to-source current I DS can still continue to flow. This is not at all the same situation as for the case of V GS = V P , where the channel is pinched off in its entirety, all the way from source to drain. When this happens, it is like having a big block of insulator the entire distance between source and drain, and I DS is reduced to essentially zero. The situation for V DS = +4 V = –V P is shown at point E on the I DS vs. V DS curve of Fig. 24.5. For V DS > +4 V, the current essentially saturates and doesn’t increase much with further increases in V DS . As V DS increases above +4 V, the pinched-off region at the drain end of the channel gets wider, which increases r ds . This increase in r ds essentially counterbalances the increase in V DS such that I DS does not increase much. This region of the I DS vs. V DS curve in which the channel is pinched off at the drain end is called the active region and is also known as the saturated region. It is called the active region because when the JFET is to be used as an amplifier, it should be biased and operated in this region. The saturated value of drain current up in the active region for the case of V GS = 0 is called the drain saturation current, I DSS (the third subscript S FIGURE 24.1 FIGURE 24.2 FIGURE 24.3 ? 2000 by CRC Press LLC refers to I DS under the condition of the gate shorted to the source). Since there is not really a true saturation of current in the active region, I DSS is usually specified at some value of V DS . For most JFETs, the values of I DSS fall in the range of 1 to 30 mA. The region below the active region where V DS < +4 V = –V P has several names. It is called the nonsaturated region, the triode region, and the ohmic region. The term triode region apparently originates from the similarity of the shape of the curves to that of the vacuum tube triode. The term ohmic region is due to the variation of I DS with V DS as in Ohm’s law, although this variation is nonlinear except for the region of V DS that is small compared to the pinch-off voltage where I DS will have an approximately linear variation with V DS . The upper limit of the active region is marked by the onset of the breakdown of the gate-to-channel pn junction. This will occur at the drain end at a voltage designated as BV DG , or BV DS , since V GS = 0. This breakdown voltage is generally in the 30- to 150-V range for most JFETs. So far we have looked at the I DS vs. V DS curve only for the case of V GS = 0. In Fig. 24.6 a family of curves of I DS vs. V DS for various constant values of V GS is presented. This is called the drain characteristics, also known as the output characteristics, since the output side of the JFET is usually the drain side. In the active region where I DS is relatively independent of V DS , a simple approximate equation relating I DS to V GS is the square-law transfer equation as given by I DS = I DSS [1 – (V GS /V P )] 2 . When V GS = 0, I DS = I DSS as expected, and as V GS ? V P , I DS ? 0. The lower boundary of the active region is controlled by the condition that the channel be pinched off at the drain end. To meet this condition FIGURE 24.4 FIGURE 24.5 ? 2000 by CRC Press LLC the basic requirement is that the gate-to-channel bias voltage at the drain end of the channel, V GD , be greater than the pinch-off voltage V P . For the example under consideration with V P = –4 V, this means that V GD = V GS – V DS must be more negative than –4 V. Therefore, V DS – V GS 3 +4 V. Thus, for V GS = 0, the active region will begin at V DS = +4 V. When V GS = –1 V, the active region will begin at V DS = +3 V, for now V GD = –4 V. When V GS = –2 V, the active region begins at V DS = +2 V, and when V GS = –3 V, the active region begins at V DS = +1 V. The dotted line in Fig. 24.6 marks the boundary between the nonsaturated and active regions. The upper boundary of the active region is marked by the onset of the avalanche breakdown of the gate-to-channel pn junction. When V GS = 0, this occurs at V DS = BV DS = BV DG . Since V DG = V DS – V GS and breakdown occurs when V DG = BV DG , as V GS increases the breakdown voltage decreases, as given by BV DG = BV DS – V GS . Thus BV DS = BV DG + V GS . For example, if the gate-to-channel breakdown voltage is 50 V, the V DS breakdown voltage will start off at 50 V when V GS = 0 but decrease to 46 V when V GS = –4 V. In the nonsaturated region I DS is a function of both V GS and V DS , and in the lower portion of the nonsaturated region where V DS is small compared to V P , I DS becomes an approximately linear function of V DS . This linear portion of the nonsaturated is called the voltage-variable resistance (VVR) region, for in this region the JFET acts like a linear resistance element between source and drain. The resistance is variable in that it is controlled by the gate voltage. This region and VVR application will be discussed in a later section. The JFET can also be operated in this region as a switch, and this will also be discussed in a later section. JFET Biasing Voltage Source Biasing Now we will consider the biasing of JFETs for operation in the active region. The simplest biasing method is shown in Fig. 24.7, in which a voltage source V GG is used to provide the quiescent gate-to-source bias voltage V GSQ . In the active region the transfer equation for the JFET has been given as I DS = I DSS [1 – (V GS /V P )] 2 , so for a quiescent drain current of I DSQ the corresponding gate voltage will be given by V GSQ = V P (1 – . For a Q point in the middle of the active region, we have that I DSQ = I DSS /2, so V GSQ = V P (1 – ) = 0.293 V P . The voltage source method of biasing has several major drawbacks. Since V P will have the opposite polarity of the drain supply voltage V DD , the gate bias voltage will require a second power supply. For the case of an n-channel JFET, V DD will come from a positive supply voltage and V GG must come from a separate negative power supply voltage or battery. A second, and perhaps more serious, problem is the “open-loop” nature of this biasing method. The JFET parameters of I DDS and V P will exhibit very substantial unit-to-unit variations, often by as much as a 2:1 factor. There is also a significant temperature dependence of I DDS and V P . These variations will lead to major shifts in the position of the Q point and the resulting distortion of the signal. A much better biasing method is shown in Fig. 24.8. Self-Biasing The biasing circuit of Fig. 24.8 is called a self-biasing circuit in that the gate-to- source voltage is derived from the voltage drop produced by the flow of drain current through the source biasing resistor R S . It is a closed-loop system in that variations in the JFET parameters can be partially compensated for by the biasing circuit. The gate resistor R G is used to provide a dc return path for the gate leakage current and is generally up in the megohm range. The voltage drop across R S is given by V S = I DS · R S . The voltage drop across the gate resistor R G is V G = I G · R G . Since I G is usually in the low nanoampere or even picoampere range, as long as R G is not extremely large FIGURE 24.6 FIGURE 24.7 Voltage source biasing. FIGURE 24.8Self-biasing. I DSQ I DSS ¤ 12¤ ? 2000 by CRC Press LLC the voltage drop across R G can be neglected, so V G @ 0. Thus, we have that V GS = V G – V S @ –V S = –I DS · R S . For example, if I DSS = 10 mA and V P = –4 V, and for a Q point in the middle of the active region with I DSQ = I DS S /2 = 5 mA, we have that V GSQ = 0.293V P = –1.17 V. Therefore the required value for the source biasing resistor is given by R S = –V GS /I DSQ = 1.17 V/5 mA = 234 W. This produces a more stable quiescent point than voltage source biasing, and no separate negative power supply is required. The closed-loop nature of this biasing circuit can be seen by noting that if changes in the JFET parameters were to cause I DS to increase, the voltage drop across R S would also increase. This will produce an increase in V GS (in the negative direction for an n-channel JFET), which will act to reduce the increase in I DS . Thus the net increase in I DS will be less due to the feedback voltage drop produced by the flow of I DS through R S . The same basic action would, of course, occur for changes in the JFET parameters that would cause I DS to decrease. Bias Stability Now let’s examine the stability of the Q point. We will start again with the basic transfer equation as given by I DS = I DSS [1 – (V GS /V P )] 2 . From this equation the change in the drain current, D I DS , due to changes in I DSS , V GS , and V P can be written as Since V GS = –I DS · R S , DV GS = –R S · DI DS , we obtain that Collecting terms in DI DS on the left side gives Now solving this for DI DS yields From this we see that the shift in the quiescent drain current, DI DS , is reduced by the presence of R S by a factor of 1 + g m R S . If I DS = I DSS /2, then Since V GS = 0.293V P , the source biasing resistor will be R S = –V GS /I DS = –0.293 V P /I DS . Thus so 1 + g m R S = 1.83. Thus the sensitivity of I DS due to changes in V P and I DSS is reduced by a factor of 1.83. DD D DIgVg V V V I I I DS m GS m GS P P DS DSS DSS =- + DD DDIgRIg V V V I I I DS m S DS m GS P P DS DSS DSS =- - + DDDIgRg V V V I I I DS m S m GS P P DS DSS DSS ()1 +=- + D DD I gV V V I I I gR DS mGS P P DS DSS DSS mS = -+ + ()/ 1 g II V II V I V m DS DSS P DS DS P DS P = × - = × - = - 222 22 gR I V V I mS DS P P DS = - ′ - =′ = 2 2 0 293 2 2 0 293 0 83 . .. ? 2000 by CRC Press LLC The equation for DI DS can now be written in the following form for the fractional change in I DS : so DI DS /I DS = –0.45 (DV P /V P ) + 0.77 (DI DSS /I DSS ), and thus a 10% change in V P will result in approximately a 4.5% change in I DS , and a 10% change in I DSS will result in an 8% change in I DS . Thus, although the situation is improved with the self-biasing circuit using R S , there will still be a substantial variation in the quiescent current with changes in the JFET parameters. A further improvement in bias stability can be obtained by the use of the biasing methods of Figs. 24.9 and 24.10. In Fig. 24.9 a gate bias voltage V GG is obtained from the V DD supply voltage by means of the R G1 –R G2 voltage divider. The gate-to-source voltage is now V GS = V G – V S = V GG – I DS R S . So now for R S we have R S = (V GG – V GS )/I DS . Since V GS is of opposite polarity to V GG , this will result in a larger value for R S than before. This in turn will result in a larger value for the g m R S product and hence improved bias stability. If we continue with the preceding examples and now let V GG = V DD /2 = +10 V, we have that R S = (V GG – V GS )/I DS = [+10V –(–1.17V)]/5 mA = 2.234 kW, as compared to R S = 234 W that was obtained before. For g m we have g m = = 3.54 mS, so g m R S = 3.54 mS · 2.234 kW = 7.90. Since 1 + g m R S = 8.90, we now have an improvement by a factor of 8.9 over the open-loop voltage source biasing and by a factor of 4.9 over the self- biasing method without the V GG biasing of the gate. Another biasing method that can lead to similar results is the method shown in Fig. 24.10. In this method the bottom end of the source biasing resistor goes to a negative supply voltage V SS instead of to ground. The gate-to-source bias voltage is now given by V GS = V G –V S = 0 – (I DS · R S + V SS ) so that for R S we now have R S = (–V GS – V SS )/I DS . If V SS = –10 V, and as before I DS = 5 mA and V GS = –1.17 V, we have R S = 11.7 V/5 mA = 2.34 kW, and thus g m R S = 7.9 as in the preceding example. So this method does indeed lead to results similar to that for the R S and V GG combination biasing. With either of these two methods the change in I DS due to a 10% change in V P will be only 0.9%, and the change in I DS due to a 10% change in I DSS will be only 1.6%. The biasing circuits under consideration here can be applied directly to the common-source (CS) amplifier configuration, and can also be used for the common-drain (CD), or source-follower, and common-gate (CG) JFET configurations. Transfer Characteristics Transfer Equation Now we will consider the transfer characteristics of the JFET, which is a graph of the output current I DS vs. the input voltage V GS in the active region. In Fig. 24.11 a transfer characteristic curve for a JFET with V P = –4 V and I DSS = +10 mA is given. This is approximately a square-law relationship as given by I DS = I DSS [1 – (V GS /V P )] 2 . This equation is not valid for V GS beyond V P (i.e., V GS < V P ), for in this region the channel is pinched off and I DS @ 0. FIGURE 24.9 FIGURE 24.10 FIGURE 24.11Transfer characteristic. DDDI I VV II DS DS P P DSS DSS = -+083 141 183 .( ).( ) . // 2I DS I DSS × V P –()¤ ? 2000 by CRC Press LLC At V GS = 0, I DS = I DSS . This equation and the corresponding transfer curve can actually be extended up to the point where V GS @ +0.5 V. In the region where 0 < V GS < +0.5 V, the gate-to-channel pn junction is forward-biased and the depletion region width is reduced below the width under zero bias conditions. This reduction in the depletion region width leads to a corresponding expansion of the conducting channel and thus an increase in I DS above I DSS . As long as the gate-to-channel forward bias voltage is less than about 0.5 V, the pn junction will be essentially “off” and very little gate current will flow. If V GS is increased much above +0.5 V, however, the gate-to-channel pn junction will turn “on” and there will be a substantial flow of gate voltage I G . This gate current will load down the signal source and produce a voltage drop across the signal source resistance, as shown in Fig. 24.12. This voltage drop can cause V GS to be much smaller than the signal source voltage V in . As V in increases, V GS will ultimately level off at a forward bias voltage of about +0.7 V, and the signal source will lose control over V GS , and hence over I DS . This can result in severe distortion of the input signal in the form of clipping, and thus this situation should be avoided. Thus, although it is possible to increase I DS above I DSS by allowing the gate-to-channel junction to become forward-biased by a small amount (￡0.5 V), the possible benefits are generally far outweighed by the risk of signal distortion. Therefore, JFETs are almost always operated with the gate-to-channel pn junction reverse-biased. Transfer Conductance The slope of the transfer curve, dI DS /dV GS , is the dynamic forward transfer conductance, or mutual transfer conductance, g m . We see that g m starts off at zero when V GS = V P and increases as I DS increases, reaching a maximum when I DS = I DSS . Since I DS = I DSS [1 – (V GS /V P )] 2 , g m can be obtained as Since we have that The maximum value of g m is obtained when V GS = 0 (I DS = I DSS ) and is given by g m (V GS = 0) = g m0 = 2I DS /(–V P ). Small-Signal AC Voltage Gain Let’s consider the CS amplifier circuit of Fig. 24.13. The input ac signal is applied between gate and source, and the output ac voltage is taken between drain and source. Thus the source electrode of this triode device is common to input and output, hence the designation of this JFET configuration as a CS amplifier. A good choice of the dc operating point or quiescent point (Q point) for an amplifier is in the middle of the active region at I DS = I DSS /2. This allows for the maximum symmetrical drain current swing, from the qui- escent level of I DSQ = I DSS /2, down to a minimum of I DS @ 0, and up to a maximum of I DS = I DSS . This choice for the Q point is also a good one from the standpoint of allowing for an adequate safety margin for the location FIGURE 24.12Effect of forward bias on V GS . g dI dV I V V V m DS GS DSS GS P P == - ? è ? ? ? ÷ - 2 1 1- ? è ? ? ? ÷ = V V I I GS P DS DSS gI II V II V m DSS DS DSS P DS DSS P = - = × - 22 / FIGURE 24.13 Common-source amplifier. ? 2000 by CRC Press LLC of the actual Q point due to the inevitable variations in device and component characteristics and values. This safety margin should keep the Q point well away from the extreme limits of the active region, and thus ensure operation of the JFET in the active region under most conditions. If I DSS = +10 mA, then a good choice for the Q point would thus be around +5.0 mA. If V P = –4 V, then If a small ac signal voltage v GS is superimposed on the dc gate bias voltage V GS , only a small segment of the transfer characteristic adjacent to the Q point will be traversed, as shown in Fig. 24.14. This small segment will be close to a straight line, and as a result the ac drain current i ds will have a waveform close to that of the ac voltage applied to the gate. The ratio of i ds to v GS will be the slope of the transfer curve as given by i ds /v GS @ dI DS /dV GS = g m . Thus i ds @ g m v GS . If the net load driven by the drain of the JFET is the drain load resistor R D , as shown in Fig. 24.13, then the ac drain current i ds will produce an ac drain voltage of v ds = –i ds · R D . Since i ds = g m v GS , this becomes v ds = –g m v GS · R D . The ac small-signal voltage gain from gate to drain thus becomes A V = v O /v in = v ds /v GS = –g m · R D . The negative sign indicates signal inversion as is the case for a CS amplifier. If the dc drain supply voltage is V DD = +20 V, a quiescent drain-to-source voltage of V DSQ = V DD /2 = +10 V will result in the JFET being biased in the middle of the active region. Since I DSQ = +5 mA in the example under consideration, the voltage drop across the drain load resistor R D is 10 V. Thus R D = 10 V/5 mA = 2 kW. The ac small-signal voltage gain A V thus becomes A V = –g m · R D = –3.54 mS · 2 kW = –7.07. Note that the voltage gain is relatively modest as compared to the much larger voltage gains that can be obtained in a bipolar-junction transistor (BJT) common-emitter amplifier. This is due to the lower transfer conductance of both JFETs and MOSFETs (metal-oxide semiconductor field-effect transistors) as compared to BJTs. For a BJT the transfer conductance is given by g m = I C /V T , where I C is the quiescent collector current and V T = kT/q @ 25 mV is the thermal voltage. At I C = 5 mA, g m = 5 mA/25 mV = 200 mS, as compared to only 3.5 mS for the JFET in this example. With a net load of 2 kW, the BJT voltage gain will be –400 as compared to the JFET voltage gain of only 7.1. Thus FETs do have the disadvantage of a much lower transfer conductance, and therefore voltage gain, than BJTs operating under similar quiescent current levels, but they do have the major advantage of a much higher input impedance and a much lower input current. In the case of a JFET the input signal is applied to the reverse-biased gate-to-channel pn junction and thus sees a very high impedance. In the case of a common- emitter BJT amplifier, the input signal is applied to the forward-biased base-emitter junction, and the input impedance is given approximately by r in = r BE @ 1.5 · b · V T /I C . If I C = 5 mA and b = 200, for example, then r in @ 1500 W. This moderate input resistance value of 1.5 kW is certainly no problem if the signal source resistance is less than around 100 W. However, if the source resistance is above 1 kW, then there will be a substantial signal loss in the coupling of the signal from the signal source to the base of the transistor. If the source resistance is in the range of above 100 kW, and certainly if it is above 1 MW, then there will be severe signal attenuation due to the BJT input impedance, and the FET amplifier will probably offer a greater overall voltage gain. Indeed, when high-impedance signal sources are encountered, a multistage amplifier with a FET input stage followed by cascaded BJT stages is often used. FIGURE 24.14Transfer characteristic. g II V m DS DSS P = × - = × == 2 25 10 354 354 mA mA 4 V mA/V mS.. ? 2000 by CRC Press LLC JFET Output Resistance Dynamic Drain-to-Source Conductance For the JFET in the active region the drain current I DS is a strong function of the gate-to-source voltage V GS but is relatively independent of the drain-to-source voltage V DS . The transfer equation has previously been stated as I DS = I DSS [1 – (V GS /V P )] 2 . The drain current will, however, increase slowly with increasing V DS . To take this dependence of I DS on V DS into account, the transfer equation can be modified to give where V A is a constant called the Early voltage and is a parameter of the transistor with units of volts. The early voltage V A is generally in the range of 30 to 300 V for most JFETs. The variation of the drain current with drain voltage is the result of the channel length modulation effect in which the channel length decreases as the drain voltage increases. This decrease in the channel length results in an increase in the drain current. In BJTs a similar effect is the base width modulation effect. The dynamic drain-to-source conductance is defined as g ds = dI DS /dV DS and can be obtained from the modified transfer equation I DS = I DSS [1 – (V GS /V P )] 2 [1 + V DS /V A ] as simply g ds = I DS /V A . The reciprocal of g ds is dynamic drain-to-source resistance r ds , so r ds = 1/g ds = V A /I DS . If, for example, V A = 100 V, we have that r ds = 100 V/I DS . At I DS = 1 mA, r ds = 100 V/1 mA = 100 kW, and at I DS = 10 mA, r ds = 10 kW. Equivalent Circuit Model of CS Amplifier Stage A small-signal equivalent circuit model of a CS FET amplifier stage is shown in Fig. 24.15. The ac small-signal voltage gain is given by A V = –g m · R net , where R net = [r ds **R D **RL] is the net load driven by the drain for the FET and includes the dynamic drain-to-source resistance r ds . Since r ds is generally much larger than [R D **R L ], it will usually be the case that R net @ [R D **R L ], and r ds can be neglected. There are, however, some cases in which r ds must be taken into account. This is especially true for the case in which an active load is used, as shown in Fig. 24.16. For this case R net = [r ds1 **r ds2 **R L ], and r ds can be a limiting factor in determining the voltage gain. Consider an example for the active load circuit of Fig. 24.16 for the case of identical JFETs with the same quiescent current. Assume that R L >> r ds so that R net @ [r ds1 **r ds2 ] = VA/(2I DSQ ). Let I DSQ = I DSS /2, so g m = – . The voltage gain is If V A = 100 V and V P = –2 V, we obtain A V = –70, so we see that with active loads relatively large voltage gains can be obtained with FETs. FIGURE 24.15Effect of r ds on R net . FIGURE 24.16Active load circuit. II V V V V DS DSS GS P DS A =- ? è ? ? ? ÷ + ? è ? ? ? ÷ 11 2 2I DSS I DSQ × V P –()¤ 22I DSQ V P –()¤= AgR I V V I V V Vm DSQ P A DSQ A P =-× = ′ = net 22 2 2 ? 2000 by CRC Press LLC Another circuit in which the dynamic drain-to-source resistance r ds is important is the constant-current source or current regulator diode. In this case the current regulation is directly proportional to the dynamic drain-to-source resistance. Source Follower Source-Follower Voltage Gain We will now consider the CD JFET configuration, which is also known as the source follower. A basic CD circuit is shown in Fig. 24.17. The input signal is supplied to the gate of the JFET. The output is taken from the source of the JFET, and the drain is connected directly to the V DD supply voltage, which is ac ground. For the JFET in the active region we have that i ds = g m v GS . For this CD circuit we also have that v GS = v G – v S and v S = i ds R net , where R net = [R S **R L ] is the net load resistance driven by the transistor. Since v GS = i ds /g m , we have that i ds /g m = v G – i ds R net . Collecting terms in i ds on the left side yields i ds [(1/g m ) + R net ] = v G , so The output voltage is and thus the ac small-signal voltage gain is Upon dividing through by g m this can be rewritten as From this we see that the voltage gain will be positive, and thus the source follower is a noninverting amplifier. We also note that A V will always be less than unity, although for the usual case of R net >> 1/g m , the voltage gain will be close to unity. The source follower can be represented as an amplifier with an open-circuit (i.e., no load) voltage transfer ratio of unity and an output resistance of r O = 1/g m . The equation for A V can be expressed as A V = R net /(R net + r O ), which is the voltage division ratio of the r O = R net circuit. FIGURE 24.17Source follower. i v gR gv gR ds G m mG m = + = +(/)11 net net vviR gRv gR OSds mG m == = + net net net 1 A v v gR gR V O G m m == + net net 1 A R gR V m = + net net /()1 ? 2000 by CRC Press LLC Source-Follower Examples Let’s consider an example of a JFET with I DSS = 10 mA and V P = –4 V. Let V DD = +20 V and I DSQ = I DSS /2 = 5 mA. For I DS = I DSS /2 the value of V GS is –1.17 V. To bias the JFET in the middle of the active region, we will let V GQ = V DD /2 = +10 V, so V SQ = V GQ – V GS = +10 V – (–1.17 V) = +11.17 V. Thus R S = V SQ /I DSQ = 11.17 V/5 mA = 2.23 kW. The transfer conductance at I DS = 5 mA is 3.54 mS so that r O = 1/g m = 283 W. Since g m R S = 7.9, good bias stability will be obtained. If R L >> R S , then A V @ R S /(r O + R S ) = 2.23 kW/(283 W + 2.23 kW) = 0.887. If R L = 1 kW, then R net = 690 W, and A V drops to 0.709, and if R L = 300 W, R net = 264 W and A V is down to 0.483. A BJT emitter-follower circuit has the same equations for the voltage gain as the FET source follower. For the BJT case, r O = 1/g m = V T /I C , where V T = thermal voltage = kT/q @ 25 mV and I C is the quiescent collector current. For I C = 5 mA, we get r O @ 25 mV/5 mA = 5 W as compared to r O = 283 W for the JFET case at the same quiescent current level. So the emitter follower does have a major advantage over the source follower since it has a much lower output resistance r O and can thus drive very small load resistances with a voltage gain close to unity. For example, with R L = 100 W, we get A V @ 0.26 for the source follower as compared to A V @ 0.95 for the emitter follower. The FET source follower does, however, offer substantial advantages over the emitter follower of a much higher input resistance and a much lower input current. For the case in which a very high-impedance source, up in the megohm range, is to be coupled to a low-impedance load down in the range of 100 W or less, a good combination to consider is that of a cascaded FET source follower followed by a BJT emitter follower. This combination offers the very high input resistance of the source follower and the very low output resistance of the emitter follower. For the source-follower circuit under consideration the input resistance will be R in = [R G1 **R G2 ] = 10 MW. If the JFET gate current is specified as 1 nA (max), and for good bias stability the change in gate voltage due to the gate current should not exceed *V P */10 = 0.4 V, the maximum allowable value for [R G1 **R G2 ] is given by I G · [R G1 **R G2 ] < 0.4 V. Thus [R G1 **R G2 ] < 0.4 V/1 nA = 0.4 GW = 400 MW. Therefore R G1 and R G2 can each be allowed to be as large as 800 MW, and very large values for R in can thus be obtained. At higher frequencies the input capacitance C in must be considered, and C in will ultimately limit the input impedance of the circuit. Since the input capacitance of the FET will be comparable to that of the BJT, the advantage of the FET source follower over the BJT emitter follower from the standpoint of input impedance will be obtained only at relatively low frequencies. Source-Follower Frequency Response The input capacitance of the source follower is given by C in = C GD + (1 – A V )C GS . Since A V is close to unity, C in will be approximately given by C in @ C GD . The source-follower input capacitance can, however, be reduced below C GD by a bootstrapping circuit in which the drain voltage is made to follow the gate voltage. Let’s consider a representative example in which C GD = 5 pF, and let the signal-source output resistance be R 1 = 100 kW. The input circuit is in the form of a simple RC low-pass network. The RC time constant is t = [RuuR G1 uuR G2 ] · C in @ R 1 · C in @ R 1 · C GD Thus t @ 100 kW · 5 pF = 500 ns = 0.5 ms. The corresponding 3-dB or half-power frequency is f H = 1/(2 pt) = 318 kHz. If R 1 = 1 MW, the 3-dB frequency will be down to about 30 kHz. Thus we see indeed the limitation on the frequency response that is due to the input capacitance. Frequency and Time-Domain Response Small-Signal CS Model for High-Frequency Response We will now consider the frequency- and time-domain response of the JFET CS amplifier. In Fig. 24.18 an ac representation of a CS amplifier is shown, the dc biasing not being shown. In Fig. 24.19 the JFET small-signal ac equivalent circuit model is shown including the junction capacitances C GS and C GD . The gate-to-drain capacitance C GD is a feedback capacitance in that it is connected between output (drain) and input (gate). Using ? 2000 by CRC Press LLC Miller’s theorem for shunt feedback this feedback capacitance can be transformed into an equivalent input capacitance C GD￠ = (1 – A V )C GD and an equivalent output capacitance C GD￠￠ = (1 – 1/A V )C GD , as shown in Fig. 24.20. The net input capacitance is now C in = C GS + (1 – A V )C GD and the net output capacitance is C O = (1 – 1/A V )C GD + C L . Since the voltage gain A V is given by A V = –g m R net , where R net represents the net load resistance, the equations for C in and C O can be written approximately as C in = C GS + (1 + g m R net )C GD and C O = [1 + 1/(g m R net )]C GD + C L . Since usually A V = g m R net >> 1, C O can be written as C O @ C GD + C L . Note that the voltage gain given by A V = –g m R net is not valid in the higher fre- quency, where A V will decrease with increasing frequency. Therefore the expressions for C in and C O will not be exact but will still be a useful approximation for the determination of the frequency- and time-domain responses. We also note that the contribution of C GD to the input capacitance is increased by the Miller effect factor of 1 + g m R net . The circuit in Fig. 24.21 is in the form of two cascaded RC low- pass networks. The RC time constant on the input side is t 1 = [R 1 uuR G ] · C in @ R 1 · C in , where R 1 is the signal-source resistance. The RC time constant on the output side is given by t 2 = R net · C O . The corresponding breakpoint frequencies are and The 3-dB or half-power frequency of this amplifier stage will be a function of f 1 and f 2 . If these two breakpoint frequencies are separated by at least a decade (i.e., 10:1 ratio), the 3-dB frequency will be approximately equal to the lower of the two breakpoint frequencies. If the breakpoint frequencies are not well separated, then the 3-dB frequency can be obtained from the following approx- imate relationship: (1/f 3dB ) 2 @ (1/f 1 ) 2 + (1/f 2 ) 2 . The time-domain response as expressed in terms of the 10 to 90% rise time is related to the frequency-domain response by the approximate relationship that t rise @ 0.35/f 3dB . We will now consider a representative example. We will let C GS = 10 pF and C GD = 5 pF. We will assume that the net load driven by the drain of the transistors is R net = 2 kW and C L = 10 pF. The signal-source resistance R 1 = 100 W. The JFET will have I DSS = 10 mA, I DSQ = I DSS /2 = 5 mA, and V P = –4 V, so g m = 3.535 mS. Thus the midfrequency gain is A V = –g m R net = –3.535 mS · 2 kW = –7.07. Therefore we have that C in @ C GS + (1 + g m R net )C GD = 10 pF + 8.07 · 5 pF = 50.4 pF and C O @ C GD + C L = 15 pF FIGURE 24.18Common-source amplifier. FIGURE 24.19AC small-signal model. FIGURE 24.20 FIGURE 24.21 f RC 1 11 1 2 1 2 == ×pt p in f RC 2 2 1 2 1 2 == ×pt p net O ? 2000 by CRC Press LLC Thus t 1 = R 1 · C in = 100 W · 50.4 pF = 5040 ps = 5.04 ns, and t 2 = R net · C O = 2 kW · 15 pF = 30 ns. The corresponding breakpoint frequencies are f 1 = 1/(2p · 5.04 ns) = 31.6 MHz and f 2 = 1/(2p · 30 ns)= 5.3 MHz. The 3-dB frequency of the amplifier can be obtained from (1/f 3dB ) 2 @ (1/f 1 ) 2 + (1/f 2 ) 2 = (1/31.6 MHz) 2 + (1/5.3 MHz) 2 , which gives f 3dB @ 5.2 MHz. The 10 to 90% rise time can be obtained from t rise @ 0.35/f 3dB = 0.35/5.2 MHz = 67 ns. In the preceding example the dominant time constant is the output circuit time constant of t 2 = 30 ns due to the combination of load resistance and output capacitance. If we now consider a signal-source resistance of 1 kW, the input circuit time constant will be t 1 = R 1 · C in = 1000 W · 50.4 pF = 50.4 ns. The corresponding breakpoint frequencies are f 1 = 1/(2p · 50.4 ns) = 3.16 MHz and f 2 = 1/(2p · 30 ns) = 5.3 MHz. The 3-dB frequency is now f 3dB @ 2.7 MHz, and the rise time is t rise @ 129 ns. If R 1 is further increased to 10 kW, we obtain t 1 = R 1 · C in = 10 kW · 50.4 pF = 504 ns, giving breakpoint frequencies of f 1 = 1/(2p · 504 ns) = 316 kHz and f 2 = 1/(2p · 30 ns) = 5.3 MHz. Now t 1 is clearly the dominant time constant, the 3-dB frequency is now down to f 3dB @ f 1 = 316 kHz, and the rise time is up to t rise @ 1.1 ms. Finally, for the case of R 1 = 1 MW, the 3-dB frequency will be only 3.16 kHz and the rise time will be 111 ms. Use of Source Follower for Impedance Transformation We see that large values of signal-source resistance can seriously limit the amplifier bandwidth and increase the rise time. In these cases, the use of an impedance transforming circuit such as an FET source fol- lower or a BJT emitter follower can be very useful. Let’s consider the use of a source follower as shown in Fig. 24.22. We will assume that both FETs are identical to the one in the preceding examples and are biased at I DSQ = 5 mA. The source follower Q 1 will have an input capacitance of C in = C GD + (1 – A V1 )C GS @ C GD = 5 pF, since A V will be very close to unity for a source follower that is driving a CS amplifier. The source-follower output resistance will be r O = 1/g m = 1/3.535 mS = 283 W. Let’s again consider the case of R 1 = 1 MW. The time constant due to the combination of R 1 and the input capacitance of the source follower is t SF = 1 MW · 5 pf = 5 ms. The time constant due to the combination of the source-follower output resistance r O and the input capacitance of the CS stage is t 1 = r O · C in = 283 W · 50.4 pF = 14 ns, and the time constant of the output circuit is t 2 = 30 ns, as before. The breakpoint frequencies are f SF = 31.8 kHz, f 1 = 11 MHz, and f 2 = 5.3 MHz. The 3-dB frequency of the system is now f 3dB @ f SF = 31.8 kHz, and the rise time is t rise @ 11 ms. The use of the source follower thus results in an improvement by a factor of 10:1 over the preceding circuit. Voltage-Variable Resistor Operation of a JFET as a Voltage-Variable Resistor We will now consider the operation of a JFET as a voltage-variable resistor (VVR). A JFET can be used as a VVR in which the drain-to- source resistance r ds of the JFET can be varied by variation of V GS . For values of V DS << V P the I DS vs. V DS characteristics are approximately linear, so the JFET looks like a resistor, the resistance value of which can be varied by the gate voltage as shown in Fig. 24.23. The channel conductance in the region where V DS << V P is given by g ds = As/L = WHs/L, where the channel height H is given by H = H 0 – 2W D . In this equation W D is the depletion region width and H 0 is the value of H as W D ? 0. The depletion region width is given by W D =K = K , where K is a constant, V J is the junction voltage, and f is the pn-junction contact potential (typically around 0.8 to 1.0 V). As V GS increases, W D increases and the channel height H decreases as given by H = H 0 – 2K . When V GS = V P , the channel is completely pinched off, so H = 0 and thus 2K = H 0 . Therefore 2K = H 0 / , and thus FIGURE 24.22 FIGURE 24.23 V J V GS f+ V GS f+ V P f+ V P f+ ? 2000 by CRC Press LLC THE INVENTION OF THE TRANSISTOR n 1907, the American Telephone and Telegraph Company (AT&T) and the Western Electric Company combined their engineering depart- ments and established the Bell Telephone Laboratory on West Street in New York City. By 1921, the labo- ratories constituted the largest industrial research organization in the country, occupying 400,000 square feet in a 13-story building in lower Manhattan and employing more than 1500 men and women. The organization was put on a more formal footing in 1925, when Frank B. Jewett was made President of I ? 2000 by CRC Press LLC Fo Wh r g ds we now have en V GS = 0, the channel is fully open or “on,” and HH H V V H V V GS P GS P =- + + =- + + ? è ? ? ? ÷00 0 1 f f f f g WH L WH L V V ds GS P == - + + ? è ? ? ? ÷ s s f f 0 1 gg WH ds ds == - ? ? ? ? ÷ ÷ (on) s f 0 1 Bell Telephone Laboratories, Inc. In the following decades, the labs distinguished themselves by contri- butions not only to communications technology, but to basic science as well. The awarding of the Nobel Prize in Physics to Clinton J. Davisson in 1937 was simply the most prominent recognition of the labo- ratories’ scientific work. The true importance of the fusion of science and engineering in the industrial laboratory was made apparent to all in the years after World War II. In 1947, three Bell Labs physicist-engineers produced the single most significant electronic invention of the era—the transistor. John Bardeen, Walter Brattain, and William Shockley were consciously seeking to exploit new technology about the behavior of semiconducting materials when they devised a way to make a crystal of germanium do the work of a triode vacuum tube, the most basic of electronic components. The first point-contact transistor developed at Bell Labs in 1947 by John Bardeen, William Shockley, and Walter Brattain, had a thin gold foil along the sides of a polysty- rene triangle. The foil was slit at the triangle’s apex and was pressed against a piece of germanium by the metal piece at the top of the photo (Photo courtesy of AT&T Bell Laboratories.) L V P + è ? f The drain-to-source conductance can now be expressed as The reciprocal quantity is the drain-to-source resistance r ds as given by r ds = 1/g ds , and r ds (on) = 1/g ds (on), so As V GS ? 0, r ds ? r ds (on), and as V GS ? V P ,r ds ?￥. This latter condition corresponds to the channel being pinched off in its entirety all the way from source to drain. This is like having a big block of insulator (i.e., the gg VV V ds ds GS P P = -+ + ( ) -+ ( ) (on) 1 1 ff ff rr V VV ds ds P GS P = -+ ( ) -+ + ( ) (on) 1 1 ff ff Their work built on the research of many before them, and much had to be done before the transistor and the solid-state devices that followed could become practical engineering tools, but in retrospect it is clear that the transistor gave the engineer the key to a whole new electronic world. (Courtesy of the IEEE Center for the History of Electrical Engineering.) This photograph taken in 1948 is of the three Bell Labs physicist-engineers, John Bardeen, William Shockley, and Walter Brattain, who invented the first transistor. (Photo courtesy of AT&T Bell Laboratories.) ? 2000 by CRC Press LLC depletion region) between source and drain. When V GS = 0, r ds is reduced to its minimum value of r ds (on), which for most JFETs is in the 20- to 400-W range. At the other extreme, when V GS > V P , the drain-to-source current I DS is reduced to a very small value, generally down into the low nanoampere or even picoampere range. The corresponding value of r ds is not really infinite but is very large, generally well up into the gigaohm (1000 MW) range. Thus by variation of V GS , the drain-to-source resistance can be varied over a very wide range. As long as the gate-to-channel junction is reverse-biased, the gate current will be very small, generally down in the low nanoampere or even picoampere range, so the gate as a control electrode draws very little current. Since V P is generally in the 2- to 5-V range for most JFETs, the V DS values required to operate the JFET in the VVR range are generally <0.1 V. In Fig. 24.23 the VVR region of the JFET I DS vs. V DS characteristics is shown. VVR Applications Applications of VVRs include automatic gain control (AGC) circuits, electronic attenuators, electronically variable filters, and oscillator amplitude control circuits. When using a JFET as a VVR, it is necessary to limit V DS to values that are small compared to V P to maintain good linearity. In addition V GS should preferably not exceed 0.8 V P for good linearity, control, and stability. This limitation corresponds to an r ds resistance ratio of about 10:1. As V GS approaches V P , a small change in V P can produce a large change in r ds . Thus unit-to-unit variations in V P as well as changes in V P with temperature can result in large changes in r ds as V GS approaches V P . The drain-to-source resistance r ds will have a temperature coefficient (TC) due to two causes: (1) the variation of the channel resistivity with temperature and (2) the temperature variation of V P . The TC of the channel resistivity is positive, whereas the TC of V P is negative due to the negative TC of the contact potential f. The positive TC of the channel resistivity will contribute to a positive TC of r ds . The negative TC of V P will contribute to a negative TC of r ds . At small values of V GS , the dominant contribution to the TC is the positive TC of the channel resistivity, so r ds will have a positive TC. As V GS gets larger, the negative TC contribution of V P becomes increasingly important, and there will be a value of V GS at which the net TC of r ds is zero, and above this value of V GS the TC will be negative. The TC of r ds (on) is typically +0.3%/°C for n-channel JFETs and +0.7%/°C for p-channel JFETs. For example, for a typical JFET with an r ds (on) = 500 W at 25°C and V P = 2.6 V, the zero TC point will occur at V GS = 2.0 V. Any JFET can be used as a VVR, although there are JFETs that are specifically made for this application. A simple example of a VVR application is the electronic gain control circuit of Fig. 24.24. The voltage gain is given by A V = 1 + (R F /r ds ). If, for example, R F = 19 kW and r ds (on) = 1 kW, then the maximum gain will be A Vmax = 1 + [R F /r ds (on)] = 20. As V GS approaches V P , r ds will increase and become very large such that r ds >> R F , so that A V will decrease to a minimum value of close to unity. Thus the gain can be varied over a 20:1 ratio. Note that V DS @ V in , so to minimize distortion the input signal amplitude should be small compared to V P . Defining Terms Active region: The region of JFET operation in which the channel is pinched off at the drain end but still open at the source end such that the drain-to-source current I DS approximately saturates. The condition for this is that *V GS * < *V P * and *V DS * > *V P *. The active region is also known as the saturated region. Ohmic, nonsaturated, or triode region: The three terms all refer to the region of JFET operation in which a conducting channel exists all the way between source and drain. In this region the drain current varies with both V GS and V DS . Drain saturation current, I DSS :The drain-to-source current flow through the JFET under the conditions that V GS = 0 and *V DS * > *V P * such that the JFET is operating in the active or saturated region. Pinch-off voltage, V P :The voltage that when applied across the gate-to-channel pn junction will cause the conducting channel between drain and source to become pinched off. This is also represented as V GS (off). Related Topic 28.1 Large Signal Analysis FIGURE 24.24Electronic gain control. ? 2000 by CRC Press LLC References R. Mauro, Engineering Electronics, Englewood Cliffs, N.J.: Prentice-Hall, 1989, pp. 199–260. J. Millman and A. Grabel, Microelectronics, 2nd ed., New York: McGraw-Hill, 1987, pp. 133–167, 425–429. F. H. Mitchell, Jr. and F.H. Mitchell, Sr., Introduction to Electronics Design, 2nd ed., Englewood Cliffs, N.J.: Prentice-Hall, 1992, pp. 275–328. C.J. Savant, M.S. Roden, and G.L. Carpenter, Electronic Design, 2nd ed., Menlo Park, Calif.: Benjamin- Cummings, 1991, pp. 171–208. A.S. Sedra and K.C. Smith, Microelectronic Circuits, 3rd ed., Philadelphia: Saunders, 1991, pp. 322–361. 24.2 Bipolar Transistors Joseph Watson Modern amplifiers abound in the form of integrated circuits (ICs), which contain transistors, diodes, and other structures diffused into single-crystal dice. As an introduction to these ICs, it is convenient to examine sing- transistor amplifiers, which in fact are also widely used in their own right as discrete circuits — and indeed much more complicated discrete signal-conditioning circuits are frequently found following sensors of various sorts. There are two basic forms of transistor, the bipolar family and the field-effect family, and both appear in ICs. They differ in their modes of operation but may be incorporated into circuits in quite similar ways. To understand elementary circuits, there is no need to become too familiar with the physics of transistors, but some basic facts about their electrical properties must be known. Consider the bipolar transistor, of which there are two types, npn and pnp. Electrically, they differ only in terms of current direction and voltage polarity. Figure 24.25(a) illustrates the idealized structure of an npn transistor, and diagram (b) implies that it corresponds to a pair of diodes with three leads. This representation does not convey sufficient information about the actual operation of the transistor, but it does make the point that the flow of conventional current (positive to negative) is easy from the base to the emitter, since it passes through a forward-biased diode, but difficult from the collector to the base, because flow is prevented by a reverse- biased diode. Figure 24.25(c) gives the standard symbol for the npn transistor, and diagram (d) defines the direction of current flow and the voltage polarities observed when the device is in operation. Finally, diagram (e) shows that for the pnp transistor, all these directions are reversed and the polarities are inverted. For a transistor, there is a main current flow between the collector and the emitter, and a very much smaller current flow between the base and the emitter. So, the following relations may be written: I E = I C + I B (24.1) (Note that the arrow on the transistor symbol defines the emitter and the direction of current flow—out for the npn device, and in for the pnp.) Also I C /I B = h FE (24.2) FIGURE 24.25The bipolar transistor. (a) to (d) npn transistor; (e) pnp transistor. ? 2000 by CRC Press LLC Here, h FE is called the dc common-emitter current gain, and because I C >> I B , then h FE is large, typically 50 to 300. The implication of this may be seen immediately: if the small current I B can be used to control the large current I C , then the transistor may obviously be used as a current amplifier. [This is why Fig. 24.25(b) is inadequate—it completely neglects this all-important current-gain property of the transistor.] Furthermore, if a load resistance is connected into the collector circuit, it will become a voltage amplifier, too. Unfortunately, h FE is an ill-defined quantity and varies not only from transistor to transistor but also changes with temperature. The relationship between the base-emitter voltage V BE and the collector current is much better defined and follows an exponential law closely over at least eight decades. This relationship is shown in both linear and logarithmic form in Fig. 24.26. Because the output current I C is dependent upon the input voltage V BE , the plot must be a transfer conductance or transconductance characteristic. The relevant law is (24.3) Here, I ES is an extremely small leakage current internal to the transistor, q is the electronic charge, k is Boltzmann’s constant, and T is the absolute temperature in kelvins. Usually, kT/q is called V T and is about 26 mV at a room temperature of 25°C. This implies that for any value of V BE over about 100 mV, then exp(V BE /V T ) >> 1, and for all normal operating conditions, Eq. (24.3) reduces to (24.4) The term “normal operating conditions” is easily interpreted from Fig. 24.26(a), which shows that when V BE has reached about 0.6 to 0.7 V, any small fluctuations in its value cause major fluctuations in I C . This situation is illustrated by the dashed lines enclosing DV BE and DI C , and it implies that to use the transistor as an amplifier, working values of V BE and I C must be established, after which signals may be regarded as fluctuations around these values. Under these quiescent, operating, or working conditions, I C = I Q and V CE = V Q and methods of defining these quiescent or operating conditions are called biasing. FIGURE 24.26The transconductance curve for a transistor on (a) linear and (b) logarithmic axes. IIe CES qkTV BE =-() ()/ 1 IIe V CES VV BE BE T => / for mV100 ? 2000 by CRC Press LLC Biasing the Bipolar Transistor A fairly obvious way to bias the transistor is to first establish a constant voltage V B using a potential divider R1 and R2 as shown in the biasing circuit of Fig. 24.27. Here, if I B is very small compared with the current through R2, which is usual. If it is not, this fact must be taken into account. This voltage will be much greater than V BE if a realistic power supply is used along with realistic values of R1 and R2. Hence, when the transistor is connected into the circuit, an emitter resistor must also be included so that V BE = V B – I E R E (24.5) Now consider what happens when the power supply is connected. As V B appears, a current I B flows into the base and produces a much larger current I C = h FE I B in the collector. These currents add in the emitter to give I E = I B + h FE I B = (1 + h FE )I B . h FE I B (24.6) Clearly, I E will build up until a fixed or quiescent value of base-emitter voltage V BEQ appears. Should I E try to build up further, V BE will fall according to Eq. (24.5) and, hence, so will I E . Conversely, should I E not build up enough, V BE will increase until it does so. This is actually a case of current-derived negative feedback, and it successfully holds the collector current near the quiescent value I Q . Furthermore, it does so in spite of different transistors with different values of h FE being used and in spite of temperature variations. Actually, V BE itself falls with temperature at about –2.2 mV/°C for constant I C , and the circuit will compensate for this, too. The degree of success of the negative feedback in holding I Q constant is called the bias stability. This is one example of a common-emitter (CE) circuit, so-called because the emitter is the common terminal for both base and collector currents. The behavior of the transistor in such a circuit may be illustrated by superimposing a load line on the output characteristics of the transistor, as shown in Fig. 24.28. If the collector current I C is plotted against the collector-to-emitter voltage V CE , a family of curves for various fixed values of V BE or I B results, as in Fig. 24.28. These curves show that as V CE increases, I C rises very rapidly and then turns over as it is limited by I B . In the CE circuit, if I B were reduced to zero, then I C would also be FIGURE 24.27A transistor biasing circuit. V VR RR B CC . 2 12+ ? 2000 by CRC Press LLC zero (apart from a small leakage current I CE0 ). Hence there would be no voltage drop in either R C or R E , and practically all of V CC would appear across the transistor. That is, under cut-off conditions, V CE ? V CC for I B = 0 (24.7) Conversely, if I B were large, I C would be very large, almost all of V CC would be dropped across R C + R E and (24.8) Actually, because the initial rise in I C for the transistor is not quite vertical, there is always a small saturation voltage V CES across the transistor under these conditions, where V CES means the voltage across the transistor in the common-emitter mode when saturated. In this saturated condition V CES . 0.3 V for small silicon transistors. Both these conditions are shown in Fig. 24.28. From the circuit of Fig. 24.27, V CE = V CC – I C (R C + R E ) (24.9a) which may be rewritten as I C = –V CE /(R C + R E ) + V CC /(R C + R E ) (24.9b) This is the straight-line equation to the dc load-line (compare y = mx + c), showing that its slope is –1/(R C + R E ) and that it crosses the I C axis at V CC /(R C + R E ) as expected. The actual position of a point is determined by where this load line crosses the output characteristic in use, that is, by what value of V BE or I B is chosen. For example, the quiescent point for the transistor is where the load line crosses the output curve defined by V BE = V BEQ (or I B = I BQ ) to give V CE = V Q and I C = I Q . FIGURE 24.28 The load-line diagram. I V RR I C CC CE B ? + for large ? 2000 by CRC Press LLC Note that because the transistor is nonohmic (that is, it does not obey Ohm’s law), the voltage across it may only be determined by using the (ohmic) voltage drop across the resistors R C and R E according to Eq. (24.9). At the quiescent point this is V Q = V CC – I Q (R C + R E ) A design example will illustrate typical values involved with a small-transistor CE stage. Example 1 A transistor is to be biased at a collector current of 1 mA when a 12-V power supply is applied. Using the circuit of Fig. 24.27, determine the values of R1, R2, and R E if 3.4 V is to be dropped across R E and if the current through R2 is to be 10 I BQ . Assume that for the transistor used, V BEQ = 0.6 V and h FE = 100. Solution. In this circuit I Q = 1 mA . I E (because I B << I C ). Hence Also, V B = V RE + V BE = 3.4 + 0.6 = 4 V. This gives where I BQ = I Q /h FE = 1/100 = 0.01 mA, so Now V R1 = V CC – V B = 12 – 4 = 8 V, and the current through R1 is 10 I BQ + I BQ = 11 I BQ , so In the above design example, the base current I BQ has been included in the current passing through R1. Had this not been done, R1 would have worked out at 80 kW. Usually, this difference is not very important because discrete (or individual) resistors are available only in a series of nominal values, and each of these is subject to a tolerance, including 10, 5, 2, and 1%. In the present case, the following (5%) values could reasonably be chosen: R E = 3.3 kW R1 = 75 kW R2 = 39 kW All this means that I Q cannot be predetermined very accurately, but the circuit nevertheless settles down to a value close to the chosen one, and, most importantly, stays there almost irrespective of the transistor used and the ambient temperature encountered. Having biased the transistor into an operating condition, it is possible to consider small-signal operation. R V I E R Q E === 34 1 34 . .kW R V I B BQ 2 10 = R2 4 10 0 01 40= ′ = . kW R V I R R 1 8 11 0 01 72 7 1 1 == ′ = . .kW ? 2000 by CRC Press LLC Small-Signal Operation In the biasing circuit of Fig. 24.27, the collector resistor R C had no discernible function, because it is simply the load resistor across which the signal output voltage is developed. However, it was included because it also drops a voltage due to the bias current flowing through it. This means that its value must not be so large that it robs the transistor of adequate operating voltage; that is, it must not be responsible for moving the operating point too far to the left in Fig. 24.28. If the chosen bias current and voltage are I Q and V Q , then small signals are actually only fluctuations in these bias (or average) values that can be separated from them using coupling capacitors. To inject an input signal to the base, causing V BE and I B to fluctuate by v be and i b , a signal source must be connected between the base and the common or zero line (also usually called ground or earth whether it is actually connected to ground or not!). However, most signal sources present a resis- tive path through themselves, which would shunt R2 and so change, or even destroy, the bias conditions. Hence, a coupling capacitor C c must be included, as shown in Fig. 24.29, in series with a signal source represented by a Thévenin equivalent. The emitter resistor R E was included for biasing reasons (although there are other bias circuits that omit it), but for signal amplification purposes it must be shunted by a high- value capacitor C E so that the signal current can flow down to ground without producing a signal voltage drop leading to negative feedback (as did the bias current). The value of C E must be much greater than is apparent at first sight, and this point will be developed later; for the present, it will be assumed that it is large enough to constitute a short circuit at all the signal frequencies of interest. So, for ac signals R E is short-circuited and only R C acts as a load. This implies that a signal or ac load line comes into operation with a slope of –1/R C , as shown in Fig. 24.30. The ways in which the small-signal quantities fluctuate may now be examined. If v be goes positive, this actually means that V BE increases a little. This in turn implies that I C increases by an amount i c , so the voltage drop in R C increases by v ce . Keeping in mind that the top of R C is held at a constant voltage, this means that the voltage at the bottom of R C must fall by v ce . This very important point shows that because v ce falls as v be rises, there is 180° phase shift through the stage. That is, the CE stage is an inverting voltage amplifier. However, because i c increases into the collector as i b increases into the base, it is also a noninverting current amplifier. FIGURE 24.30The signal or ac load line. FIGURE 24.29A complete common-emitter stage. ? 2000 by CRC Press LLC Now consider the amount by which v ce changes with v be , which is the terminal voltage gain of the stage. In Fig. 24.26, the slope of the transconductance curve at any point defines by how much I C changes with a fluctuation in V BE . That is, it gives the ratio i c /v be at any operating point Q. Equation (24.4) is so that or (24.10) Now the signal output voltage is v ce . –i c R C (Here, the approximation sign is because the collector-emitter path within the transistor does present a large resistance r ce through which a very small part of i c flows.) The terminal voltage gain is therefore (24.11) where the negative sign implies signal inversion. In practice, V T . 26 mV at room temperature, as has been mentioned, and this leads to a very simple numerical approximation. From Eq. (24.10) and using I C = I Q , if I Q is in mA and at room temperature. This shows that irrespective of the transistor used, the transconductance may be approximated knowing only the quiescent collector current. The magnitude and phase relationships between v ce and i c can easily be seen by including them on the signal load-line diagram as shown in Fig. 24.30, where the output characteristics of the transistor have been omitted for clarity. Sinusoidal output signals have been inserted, and either may be obtained from the other by following the signal load-line locus. Now consider the small-signal current gain. Because the value of h FE is not quite linear on the I C /I B graph, its slope too must be used for small-signal work. However, the departure from linearity is not great over normal working conditions, and the small-signal value h fe is usually quite close to that of h FE . Hence, (24.12) IIe CES VV BE T = dI dV V Ie C BE T ES VV BE T = 1 i v I V g c be C T m ===the transconductance A v v iR v gR v ce be cC be mC = - =-. g I V I I m Q T Q Q = .. 0026 39 . mA/V A i i h i c b fe = . ? 2000 by CRC Press LLC The small-signal or incremental input resistance to the base itself (to the right of point X in Fig. 24.29) may now be found: (24.13) Three of the four main (midfrequency) parameters for the CE stage have now been derived, all from a rather primitive understanding of the transistor itself. The fourth, R out , is the dynamic, incremental, or small-signal resistance of the transistor from collector to emitter, which is the slope of the output characteristic at the working point r ce . Being associated with a reverse-biased (CB) junction, this is high—typically about 0.5 MW—so that the transistor acts as a current source feeding a comparatively low load resistance R C . Sum- marizing, at mid frequency, Example 2 Using the biasing values for R1, R2, and R E already obtained in Example 1, calculate the value of R C to give a terminal voltage gain of –150. Then determine the input resistance R in if h fe for the transistor is 10% higher than h FE . Solution.Because I Q = 1 mA, g m . 3921 = 39 mA/V. Hence A v . –g m R C or –150 . –39 R C , giving R C = 150/39 . 3.9 kW (Note: This value must be checked to determine that it is reasonable insofar as biasing is concerned. In this case, it will drop I Q R C = 123.9 = 3.9 V. Because V RE = 3.4 V, this leaves 12 – 3.9 – 3.4 = 4.7 V across the transistor, which is reasonable.) Finally, A Small-Signal Equivalent Circuit The conclusions reached above regarding the performance of the bipolar transistor are sufficient for the development of a basic equivalent circuit, or model, relevant only to small-signal operation. Taking the operating CE amplifier, this may be done by first “looking into” the base, shown as b in Fig. 24.31. Between this point and the actual active part of the base region b￠, it is reasonable to suppose that the intervening (inactive) semiconductor material will present a small resistance r bb￠ . This is called the base spreading resistance, and it is also shown in Fig. 24.31. From b9 to the emitter e, there will be a dynamic or incremental resistance given by (24.14) so that the full resistance from the base to the emitter must be R v i v i i i h g be b be c c b fe m in == . Ah A gRR h g Rr ife v mC fe m ce .. .. in out - R h g fe m in k. ==W 110 39 28. r v i v i i i h g be be b be c c b fe m ￠ ￠￠ == = ? 2000 by CRC Press LLC (24.15) because r bb9 is only about 10 to 100 W, which is small compared with r b￠ e , this being several kilohms (as shown by the last example). It will now be understood why Eq. (24.13) gave R in . h fe /g m . The reverse-biased junction that exists from b9 to the collector ensures that the associated dynamic resistance r b9c will be very large indeed, which is fortunate, otherwise signal feedback from the output to the input would modify the gain characteristics of the amplifier. Typically, r b￠c will be some tens of megohms. However, because of transistor action, the dynamic resistance from collector to emitter, r ce , will be smaller than r b￠c and will typically be below a megohm. This “transistor action” may be represented by a current source from collector to emitter that is dependent upon either i b or v b￠e . That is, it will be either h fe i b or g m v b￠e . The latter leads to the well-known hybrid-p model, and it is this which is shown in Fig. 24.31. Where junctions or interfaces of any sort exist, there will always be distributed capacitances associated with them, and to make these easy to handle analytically, they may be “lumped” into single capacitances. In the present context, two lumped capacitances have been incorporated into the hybrid-p model, C b￠e from base to emitter and C b9c from base to collector, respectively. These now complete the model, and it will be appreciated that they make it possible to analyze high-frequency performance. Typically, C b￠e will be a few picofarads and will always be larger than C b9c . Figure 24.31 is the hybrid-p small-signal, dynamic, or incremental model for a bipolar transistor, and when external components are added and simplifications made, it makes possible the determination of the perfor- mance of an amplifier using that transistor not only at midfrequencies but at high and low frequencies, too. Low-Frequency Performance In Fig. 24.32 both a source and a load have been added to the hybrid-p equivalent circuit to model the complete CE stage of Fig. 24.29. Here, both C b9e and C b9c have been omitted because they are too small to affect the low-frequency performance, as has r b9c because it is large and so neither loads the source significantly compared to r bb￠ + r b9e nor applies much feedback. The signal source has been represented by a Thévenin equivalent that applies a signal via a coupling capacitor C c . Note that this signal source has been returned to the emitter, which implies that the emitter resistor bypass capacitor C E has been treated as a short circuit at all signal frequencies for the purposes of this analysis. Because the top of biasing resistor R1 (Fig. 24.29) is taken to ground via the power supply insofar as the signal is concerned, it appears in parallel with R2, and the emitter is also grounded to the signal via C E . That is, a composite biasing resistance to ground R B appears: Finally, the collector load is taken to ground via the power supply and hence to the emitter via C E . FIGURE 24.31The hybrid-p small-signal transistor equivalent circuit or model. Rrrr h g h g bb be bb fe m fe m in =+=+ ￠￠ ￠ . R RR RR B = × + 12 12 ? 2000 by CRC Press LLC Figure 24.32 shows that v be is amplified independently of frequency, so the terminal voltage gain A v may easily be determined: Now because r b￠e >> r bb￠ and r ce >> R L . So, A v . –g m R L which is as expected. The model shows that v be is amplified independently of frequency because there are no capacitances to its right, so an analysis of low-frequency response devolves down to determining v be in terms of e. Here, part of e will appear across the capacitive reactance X Cc , and the remainder is v be . So, to make the concept of reactance valid, a sinusoidal signal E must be postulated, giving a sinusoidal value for v be = V be . At midfrequencies, where the reactance of C c is small, the signal input voltage is (24.16) where R BP = R B R in /(R B + R in ) and R in = r bb￠ + r b￠e as before. At low frequencies, where the reactance of C c is significant, (24.17) Dividing (24.16) by (24.17) gives FIGURE 24.32 The loaded hybrid-p model for low frequencies. A v v iR v v ce be cL be == - v vr r r vi gv r rR gv be be bb be be be mbece ce L mbe = + = + ￠￠ ￠ ￠ ￠ ￠ ￠ () ..and c Vf ER RR be m BP gBP ()= × + Vf ER RR X be BP gBP C c () () low = × + + 22 Vf Vf RR X RR be m be gBP C gBP c () () () low = ++ + 22 ? 2000 by CRC Press LLC There will be a frequency f L at which uX Cc u = R g + R BP given by (24.18) At this frequency, V be (f m )/V be (f L ) = or V be (f L ) is 3 dB lower than V be (f m ). Example 3 Using the circuit components of the previous examples along with a signal source having an internal resistance of R g = 5 kW, find the value of a coupling capacitor that will define a low-frequency –3dB point at 42 Hz. Solution.Using Eq. (24.18), where R BP = R1uuR2uuR in = 75uu39uu2.8 = 2.5 kW. That is, Since a single RC time constant is involved, the voltage gain of the CE stage will appear to fall at 6 dB/octave as the frequency is reduced because more and more of the signal is dropped across C c . However, even if C E is very large, it too will contribute to a fall in gain as it allows more and more of the output signal to be dropped across the R E uuX CE combination, this being applied also to the input loop, resulting in negative feedback. So, at very low frequencies, the gain roll-off will tend to 12 dB/octave. The question therefore arises of how large C E should be, and this can be conveniently answered by considering a second basic form of transistor connection as follows. The Emitter-Follower or Common-Collector (CC) Circuit Suppose that R C is short-circuited in the circuit of Fig. 24.29. This will not affect the biasing because the collector voltage may take any value (the output characteristic is nearly horizontal, as seen in Fig. 24.28). However, the small-signal output voltage ceases to exist because there is now no load resistor across which it can be developed, though the output current i c will continue to flow as before. If now C E is removed, i c flows entirely through R E and develops a voltage which can be observed at the emitter i e R E (. i c R E ). Consider the magnitude of this voltage. Figure 24.26(a) shows that for a normally operating transistor, the signal component of the base-emitter voltage DV BE (or v be ) is very small indeed, whereas the constant component needed for biasing is normally about 0.6 to 0.7 V. That is, v be << V BE . This implies that the emitter voltage must always follow the base voltage but at a dc level about 0.6 to 0.7 V below it. So, if an output signal is taken from the emitter, it is almost the same as the input signal at the base. In other words, the voltage gain of an emitter follower is almost unity. If this is the case, what is the use of the emitter follower? The answer is that because the signal current gain is unchanged at i e /i b = (h fe + 1) . h fe , then the power gain must also be about h fe . This means in turn that the output resistance must be the resistance “looking into” the transistor from the emitter, divided by h fe . If the parallel combination of R g and the bias resistors is R G , then (24.19) where R G = R g uuR1uuR2 (or R g uuR B ). 1 2 1 2ppfC RR f CR R Lc gBP L cg BP =+ = + or () 2 C RRf c gBPL = + 1 2p() C= + m 10 25000 250042 05 6 p()( .. F R Rrr h CC Gb be fe out( ) = ++ ￠￠ ? 2000 by CRC Press LLC If a voltage generator with zero internal resistance (R g = 0) were applied to the input, then this would become and if r b￠e >> r bb￠ (which is usual), then (24.20) Consider the numerical implications of this: if I C = 1 mA, then g m . 39 mA/V (at room temperature), so 1/g m . 26 W, which is a very low output resistance indeed. In fact, though it appears in parallel with R E , it is unlikely that R E will make any significant contribution because it is usually hundreds or thousands of ohms. Example 4 Using the same bias resistors as for the CE examples, find the output resistance at the emitter of a CC stage. Solution. The parallel resistances to the left of the base are R G = R g uuR1uuR2 = 5uu75uu39 ? 4.2 kW Using Eq. (24.19), where g m ? 39I C , I Q = 1 mA, and h fe = 110, so From values like this, it is clear that the output of an emitter follower can be thought of as a good practical dependent voltage source of very low internal resistance. The converse is also true: the input at the base presents a high resistance. This is simply because whereas much the same signal voltage appears at the base as at the emitter, the base signal current i b is smaller than the emitter signal current i e by a factor of (h fe + 1) . h fe . Hence, the apparent resistance at the base must be at least h fe R E . To this must be added r bb￠ + r b￠e so that R in(CC) . r bb9 + r b9e + h fe R E (24.21a) Now h fe is rarely less than about 100, so h fe R E is usually predominant and R in(CC) . h fe R E (24.21b) The emitter-follower circuit is therefore a buffer stage because it can accept a signal at a high resistance level without significant attenuation and reproduce it at a low resistance level and with no phase shift (except at high frequencies). R rr h CC bb b e fe out( ) = + ￠￠ R r hg CC be fe m out( ) . ￠ = 1 R Rr h R hg r Gbe fe G fe m bbout (neglecting ? + =+ ￠ ￠ 1 ) R CCout( ) ?+?W 4200 110 1000 39 63 8. ? 2000 by CRC Press LLC In this configuration, the unbypassed emitter resistor R E is obvi- ously in series with the input circuit as well as the output circuit. Hence, it is actually a feedback resistor and so may be given the alternative symbol R F , as in Fig. 24.33. Because all the output signal voltage is fed back in series with the input, this represents 100% voltage-derived series negative feedback. The hybrid-p model for the bipolar transistor may now be inserted into the emitter-follower circuit of Fig. 24.33, resulting in Fig. 24.34, from which the four midfrequency parameters may be obtained. As an example of the procedures involved, consider the derivation of the voltage gain expression. Summing signal currents at the emitter, Now 1/r ce << 1/R F and so may be neglected, and v b9e = v in – v out , so or giving (24.22) which is a little less than unity as expected. FIGURE 24.34An emitter-follower equivalent circuit for low frequencies. FIGURE 24.33The emitter follower (or CC stage). v Rr v r g Fce be be mout 11 1 + ? è ? ? ? ÷ =+ ? è ? ? ? ÷￠ ￠ v R vv r g Fbe mout in out 11? è ? ? ? ÷ =- + ? è ? ? ? ÷ ￠ () v Rr gv r g Fbe m be mout in 11 1 ++ ? è ? ? ? ÷ =+ ? è ? ? ? ÷ ￠￠ A v v rg rgR gr gr rR gr gr rR gR gR vCC be m be m F mbe mbe be F mbe mbe be F mF mF () out in / // / / == + ++ = + ++ + = + ￠ ￠ ￠ ￠￠ ￠ ￠￠ 1 11 1 1 1 . ? 2000 by CRC Press LLC Similar derivations based on the equivalent circuit of Fig. 24.34 result in the other three basic midband operating parameters for the emitter follower, and all may be listed: and The Common-Emitter Bypass Capacitor C E In a CE circuit such as that of Fig. 24.29, suppose C c is large so that the low-frequency –3-dB point f L is defined only by the parallel combination of the resistance at the emitter and C E . It will now be seen why the emitter- follower work is relevant: the resistance appearing at the emitter of the CE stage is the same as the output resistance of the emitter-follower stage, and this will now appear in parallel with R E . If this parallel resistance is renamed R emitter , then, neglecting r bb9, and if C E were to define f L , then (24.23a) For design purposes, C E can be extracted for any given value of f L : (24.23b) Example 5 In Example 4, let C c be large so that only C E defines f L at 42 Hz, and find the value of C E . Solution.In the emitter-follower example, where R g = 5 kW, R out(CC) was found to be 63.8 W, and this is the same as R emitter in the present case. Therefore, () () in( ) AhA RrrhRhR iCC fe vCC CC bb be fe F fe F . .. ?+ ++ ￠￠ 1 R Rrr h R Rrr h g Rrr CC Gb be fe F Gb be fe m gb be out( ) if and .* . . ++ ++ ?< ￠￠ ￠￠ ￠￠ 1 0 RRR Rr h R Rr h CC E Gbe fe E Gbe fe emitter out = + + ￠ ￠ () ** .* . f RC L E = 1 2p emitter C Rf E L = 1 2p emitter C E = ′ m 10 263842 60 6 p. . F ? 2000 by CRC Press LLC This is the value of C E that would define f L if C c were large. However, if C E is to act as a short circuit at this frequency, so allowing C c to define f L , then its value would have to be one or two orders of magnitude greater, that is, 600 to 6000 mF. Summarizing, three possibilities exist: 1.If C E is very large, C c defines f L and a 6-dB/octave roll-off results. 2.If C c is large, C E defines f L and again a 6-dB/octave roll-off results. 3.If both C c and C E act together, a 12-dB/octave roll-off results. In point of fact, at frequencies much less than f L , both conditions (1) and (2) eventually produce 12-dB/octave roll-offs as the alternate “large” capacitors come into play at very low frequencies, but since the amplifier will not still have a useful gain at such frequencies, this is of little importance. High-Frequency Response Unlike the low-frequency response situation, the high-frequency response is governed by the small distributed capacitances inside the transistor structure, and these have been lumped together in the hybrid-p model of Fig. 24.31 as C b9e and C b9c . At high frequencies, r b9c may be neglected in comparison with the reactance of C b9c , so the model may be simplified as in Fig. 24.35(a). From this it will be seen that C b9c is a capacitance which appears from the output to the input so that it may be converted by the Miller Effect into a capacitance at the input of value: C b9c (1 – A v ) = C b9c (1 + g m R C ) This will now add to C b9e to give C in : C in = C b9e + C b9c (1 + g m R C ) (24.24) FIGURE 24.35(a) The high-frequency hybrid-p model and (b) its simplification. ? 2000 by CRC Press LLC This simplification is shown in Fig. 24.35(b), where C in is seen to be shunted by the input parts of the model. These input parts may be reduced by sequential use of Thévenin–Norton transformations to result in Fig. 24.36, which is a simple parallel RC circuit driven by a current source. The actual value of this current source is immaterial—what matters is that the input signal to be amplified, v b9e , will be progressively reduced as the frequency rises and the reactance of C in falls. Using a sinusoidal source, V b9e will be 3 dB down when R = *X C in *, which gives (24.25) where R = (R G + r bb9 )uur b9e from the circuit reduction. Complete Response Now that both the low- and high-frequency roll-offs have been related to single time constants (except when C c and C E act together), it is clear that the complete frequency response will look like Fig. 24.37, where the midband voltage gain is A v = –g m R C . Design Comments The design of a simple single-transistor amplifier stage has now been covered in terms of both biasing and small-signal performance. These two concepts have been kept separate, but it will have been noticed that they FIGURE 24.36Simplification of the input part of the high-frequency hybrid-p model. FIGURE 24.37The complete frequency response. RRrr CCC1gR Gb be in be bc mL =+ =++ ￠￠ ￠￠ ( ) ( ) R fC f RC H H == 1 2 1 2pp in in or ? 2000 by CRC Press LLC are bridged by the transconductance, because g m = (q/kT)I Q (. 39I Q at room temperature). That is, when I Q has been determined, then the small-signal performance follows from expressions involving g m . In fact, once the quiescent voltage across the load resistor of a CE stage has been determined, the voltage gain follows from this irrespective of the values of I Q and R C . If the quiescent voltage at the collector is V out , then in dc biasing terms, V RC = I Q R C = (V CC – V out ) and in small-signal terms, A v = –g m R C > –39I Q R C (at 25°C) = –39(V CC – V out ) Thus, g m really does act as a bridge between the bias and the small-signal conditions for the bipolar transistor amplifier stage. Unfortunately, however, there are serious problems with such a stage from a practical viewpoint. For example, it cannot amplify down to dc because of the existence of C c , and if a larger gain is needed, the cascading of such stages will present problems of phase shift and hence feedback stability. Furthermore, it cannot be produced in IC form because of the incorporation of large capacitances and somewhat critical and high-valued resistors. This leads to a reevaluation of the basic tenets of circuit design, and these may be summed up as follows: circuit design using discrete components is largely concerned with voltage drops across resistors (as has been seen), but the design of ICs depends extensively on currents and current sources and sinks. Integrated Circuits Monolithic ICs are fabricated on single chips of silicon or dice (the singular being die). This means that the active and passive structures on the chips are manufactured all at the same time, so it is easy to ensure that a large number of such structures are identical, or bear some fixed ratio to one another, but it is more difficult to establish precise values for such sets of structures. For example, a set of transistors may all exhibit almost the same values of h FE , but the actual numerical value of h FE may be subject to wider tolerances. Similarly, many pairs of resistors may bear a ratio n:1 to each other, but the actual values of these resistors are more difficult to define. So, in IC design, it is very desirable to exploit the close similarity of devices (or close ratios) rather than depend upon their having predictable absolute values. This approach has led to two ubiquitous circuit configurations, both of which depend upon device similarity: the long-tailed pair or difference amplifier (often called the differential amplifier), and the current mirror. This section will treat both, and the former is best introduced by considering the degenerate common-emitter stage. The Degenerate Common-Emitter Stage Consider two CE stages which are identical in every respect but which have no emitter resistor bypass capacitors, as shown in Fig. 24.38. Also, notice that in these diagrams, two power supply rails have been used, a positive one at V + CC and a negative one at V – CC . The reason for this latter, negative, rail is that the bases may be operated via signal sources referred to a common line or ground. (If, for example, V + CC and V – CC are obtained from batteries as shown, then the common line is simply the junction of the two batteries, as is also shown.) The absence of capacitors now means that amplification down to dc is possible. It is now very easy to find the quiescent collector currents I Q , because from a dc bias point of view the bases are connected to ground via resistances R g , which will be taken as having low values so that they drop negligibly small voltages. Hence, (24.26)I VV R Q CC BE F = - - ** ? 2000 by CRC Press LLC [For example, if industry-standard supplies of ±15 V are used, V BE = 0.6 V, and for R F = 15 kW, then I Q = (15 – 0.6)/15 = 0.96 . 1 mA.] Now suppose that identical signals e are applied. At each collector, this will result in an output signal voltage v c , where v c = –i c R C . Also, at each emitter, the output signal voltage will be v e = i e R F . i c R F . That is, If the voltage gain from base to collector of a degenerate CE stage is A v(dCE) and the voltage gain from base to emitter is simply the emitter-follower gain A v(CC) , then v c = A v(dCE) e and v e = A v(CC) e giving Now A v(CC) is known from Eq. (24.22) so that (24.27) Note that the input resistance to each base is as for the emitter-follower stage: R in(dCE) = r bb9 + r b9e + h fe R F . h fe R F Now consider what happens if the emitters are connected together as in Fig. 24.39, where the two resistors R F have now become R X , where R X = ?R F . The two quiescent emitter currents now combine to give I X = 2I E . 2I C , and otherwise the circuit currents and voltages remain undisturbed. So, if the two input signals are identical, then the two output signals will also FIGURE 24.38Two degenerate CE stages. v v iR iR R R c e cc cF C F . - =- A A R R vdCE vCC C F () () .- AA R R gR gR R R vdCE vCC C F mC mF C F () .-=- + - () 1 ? 2000 by CRC Press LLC be identical. This circuit is now called a difference amplifier, and the reason will become obvious as soon as the two input signals differ. The Difference Amplifier In Fig. 24.39, if e 1 = e 2 , these are called common-mode input signals, e in(CM) , and they will be amplified by –R C /R F as for the degenerate CE stage. However, if e 1 1 e 2 , then e 1 – e 2 = e in , the difference input signal. The following definitions now apply: and Hence, e 1 = e in(CM) + e in(diff) and e 2 = e in(CM) – e in(diff) . Consider the progress of a signal current driven by e 1 – e 2 and entering the base of Q1. It will first pass through R g , then into the resistance R in at the base of Q1, and will arrive at the emitter of Q2. Here, if R X is large, most of this signal current will pass into the resistance presented by the Q2 emitter and eventually out of the Q2 base via another R g to ground. The total series resistance is therefore R g + R in = R g + r bb￠ + r b￠e + h fe R emitter(2) But so R g + R in = 2(R g + r bb￠ + r b￠e ) FIGURE 24.39 The difference amplifier. ee e CM 12 2 + = in( ) the common mode component ±- = ()ee 12 2 in(diff ) 1 2 in the difference component, or R Rr r h gbb be fe emitter( )2 = ++ ￠￠ ? 2000 by CRC Press LLC which is the resistance between the two signal sources. Hence, giving so that the overall difference voltage gain to each collector is (24.28a) If the voltage gain with the input signal measured between the actual bases is needed, R g may be removed to give (24.28b) Finally, if the output signal is measured between the collectors (which will be twice that at each collector because they are in antiphase), the difference-in–to–difference-out voltage gain will be (24.28c) which is the same as for a single CE stage. Note that this is considerably larger than the gain for a common-mode input signal; that is, the difference stage amplifies difference signals well but largely rejects common-mode signals. This common-mode rejection property is very useful, for often, small signals appear across leads, both of which may contain identical electrical noise. So, the difference stage tends to reject the noise while still amplifying the signal. Furthermore, the difference stage has the advantage that it needs no coupling or bypass capacitors and so will amplify frequencies down to zero (dc). Also, it is very stable biaswise and lends itself perfectly to realization on a monolithic IC. To make the above derivation valid, the long-tail resistance R X should be as large as possible so that most of the signal current enters the emitter of Q2. However, R X must also carry the quiescent current, which would produce a very high quiescent voltage drop and so require a very high value of V CC –. To overcome this, another transistor structure may be used within a configuration known as a current mirror. The Current Mirror The two transistors in Fig. 24.40 are assumed to be identical, and Q1 has its base and collector connected so that it acts simply as a diode (formed by the base-emitter junction). The current through it is therefore (24.29) ii ee Rrr bb gb be () () () 12 12 2 =- = - ++ ￠￠ vv hRee Rrr cc fe C gb be () () () () 12 12 2 =- = - ++ ￠￠ A v ee hR Rrr ov c fe C gb be = - = ± ++ ￠￠12 2( ) A hR rr v fe C bb be = ± + ￠￠ 2( ) A hR rr hR r gR v fe C bb be fe C be mC(diff) = + = ￠￠ ￠ . I VV R CC BE = - ? 2000 by CRC Press LLC The voltage drop V BE so produced is applied to Q2 as shown so that it is forced to carry the same collector current I; that is, it mirrors the current in Q1. The transistor Q2 is now a device that carries a dc I C(2) = I but presents a large incremental resistance r ce at its collector. This is exactly what is required by the difference amplifier pair, so it may be used in place of R X . The Difference Stage with Current Mirror Biasing Figure 24.41 shows a complete difference stage complete with a current mirror substituting for the long-tail resistor R X , where the emitter quiescent currents combine to give I X : (24.30) This quiescent or bias current is very stable, because the change in V BE(3) due to temperature variations is exactly matched by that required by Q4 to produce the same current. The difference gain will be as discussed above, but the common-mode gain will be extremely low because of the high incremental resistance r ce presented by the long-tail transistor. FIGURE 24.40The current mirror. FIGURE 24.41Current mirror biasing. I VVV R I X CC CC BE = +- = ** ()3 ? 2000 by CRC Press LLC The Current Mirror as a Load A second current mirror may be used as a load for the difference amplifier, as shown in Fig. 24.42. This must utilize pnp transistor structures so that the Q6 collector loads the Q2 collector with a large incremental resistance r ce (6), making for an extremely high voltage gain. Furthermore, Q5 and Q6 combine the signal output currents of both Q1 and Q2 to perform a double-ended–to–single-ended conversion as follows. Taking signal currents, i out = i c (6) – i c (2) But i c (6) = i c (5) by current mirror action, and i c (5) = i c (1) so i c (6) = i c (1) Also, i c (2) = –i c (1) by difference amplifier action, so i out = i c (1) + i c (1) = 2i c (1) (24.31) Thus, both sides of the long-tailed pair are used to provide an output current that may then be applied to further stages to form a complete amplifier. Also, because no capacitors and only one resistor are needed, it is an easy circuit for monolithic integration on a single die. FIGURE 24.42A complete difference amplifier stage. ? 2000 by CRC Press LLC Summary It has been shown how a limited knowledge of bipolar operation can lead to properly biased amplifier stages using discrete transistors. An equivalent circuit—the hybrid-p model—was then derived, again from limited information, which made possible the analysis of such stages, and some purely practical design results were favorably compared with its predictions. Finally, the tenets of this equivalent circuit were used to evaluate the performance of the difference amplifier and current mirror circuits, which are the cornerstones of modern electronic circuit design in a very wide variety of its manifestations. These circuits are, in fact, the classic transconductance and translinear elements that are ubiquitous in modern IC signal conditioning and function networks. It should be recognized that there are many models other than the one introduced here, from the simple but very common h-parameter version to complex and comprehensive versions developed for computer-aided design (CAD) methods. However, the present elementary approach has been from a design rather than an analytical direction, for it is obvious that powerful modern computer-oriented methods such as the SPICE variants become useful only when a basic circuit configuration has been established, and at the time of writing, this is still the province of the human designer. Defining Terms Biasing circuit: A circuit that holds a transistor in an operating condition ready to receive signals. Common emitter: A basic transistor amplifier stage whose emitter is common to both input and output loops. It amplifies voltage, current, and hence power. Current mirror: An arrangement of two (or more) transistors such that a defined current passing into one is mirrored in another at a high resistance level. Degenerate common emitter: A combination of the common-emitter and emitter-follower stages with a very well-defined gain. Difference amplifier or long-tailed pair: An arrangement of two transistors that amplifies difference signals but rejects common-mode signals. It is often called a differential pair. Emitter follower or common collector: A basic transistor amplifier stage whose collector is common to both input and output loops. Its voltage gain is near unity, but it amplifies current and hence power. It is a high-input resistance, low-output resistance, or buffer, circuit. Related Topic 28.2 Small Signal Analysis Further Information The following list of recent textbooks covers topics mainly related to analog circuitry containing both integrated and discrete semiconductor devices. G. M. Glasford, Analog Electronic Circuits, Englewood Cliffs, N.J.: Prentice-Hall, 1986. P. R. Gray and R.G. Meyer, Analysis and Design of Analog Integrated Circuits, 2nd ed., New York: Wiley, 1984. J. Keown, PSPICE and Circuit Analysis, New York: Macmillan, 1991. R.B. Northrop, Analog Electronic Circuits, Reading, Mass.: Addison-Wesley, 1990. A.S. Sedra and K.C. Smith, Microelectronic Circuits, 3rd ed., Philadelphia: Saunders, 1991. T. Schubert and E. Kim, Active and Non-Linear Electronics, New York: Wiley, 1996. J. Watson, Analog and Switching Circuit Design, New York: Wiley, 1989. ? 2000 by CRC Press LLC 24.3 The Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) John R. Brews The MOSFET is a transistor that uses a control electrode, the gate, to capacitively modulate the conductance of a surface channel joining two end contacts, the source and the drain. The gate is separated from the semiconductor body underlying the gate by a thin gate insulator, usually silicon dioxide. The surface channel is formed at the interface between the semiconductor body and the gate insulator (see Fig. 24.43). The MOSFET can be understood by contrast with other field-effect devices, like the JFET, or junction field- effect transistor, and the MESFET, or metal semiconductor field-effect transistor [Hollis and Murphy, 1990]. These other transistors modulate the conductance of a majority-carrier path between two ohmic contacts by capacitive control of its cross section. (Majority carriers are those in greatest abundance in a field-free semi- conductor, electrons in n-type material and holes in p-type material.) This modulation of the cross section can take place at any point along the length of the channel, so the gate electrode can be positioned anywhere and need not extend the entire length of the channel. Analogous to these field-effect devices is the buried-channel, depletion-mode, or normally on MOSFET, which contains a surface layer of the same doping type as the source and drain (opposite type to the semiconductor body of the device). As a result, it has a built-in or normally on channel from source to drain with a conductance that is reduced when the gate depletes the majority carriers. FIGURE 24.43A high-performance n-channel MOSFET. The device is isolated from its neighbors by a surrounding thick field oxide under which is a heavily doped channel stop implant intended to suppress accidental channel formation that could couple the device to its neighbors. The drain contacts are placed over the field oxide to reduce the capacitance to the body, a parasitic that slows response times. These structural details are described later. (Source: After Brews, 1990.) ? 2000 by CRC Press LLC In contrast, the true MOSFET is an enhancement-mode or normally off device. The device is normally off because the body forms pn junctions with both the source and the drain, so no majority-carrier current can flow between them. Instead, minority-carrier current can flow, provided minority carriers are available. As discussed later, for gate biases that are sufficiently attractive, above threshold, minority carriers are drawn into a surface channel, forming a conducting path from source to drain. The gate and channel then form two sides of a capacitor separated by the gate insulator. As additional attractive charges are placed on the gate side, the channel side of the capacitor draws a balancing charge of minority carriers from the source and the drain. The more charges on the gate, the more populated the channel, and the larger the conductance. Because the gate creates the channel, to ensure electrical continuity the gate must extend over the entire length of the separation between source and drain. The MOSFET channel is created by attraction to the gate and relies upon the insulating layer between the channel and the gate to prevent leakage of minority carriers to the gate. As a result, MOSFETs can be made only in material systems that provide very good gate insulators, and the best system known is the silicon–silicon dioxide combination. This requirement for a good gate insulator is not so important for JFETs and MESFETs, where the role of the gate is to push away majority carriers rather than to attract minority carriers. Thus, in GaAs systems where good insulators are incompatible with other device or fabricational requirements, MESFETs are used. A more recent development in GaAs systems is the heterostructure field-effect transistor, or HFET [Pearton and Shaw, 1990], made up of layers of varying compositions of Al, Ga, and As or In, Ga, P, and As. These devices are made using molecular beam epitaxy or by organometallic vapor phase epitaxy, expensive methods still being refined for manufacture. HFETs include a variety of structures, the best known of which is the modulation doped FET, or MODFET. HFETs are field-effect devices, not MOSFETs, because the gate simply modulates the carrier density in a preexistent channel between ohmic contacts. The channel is formed spon- taneously, regardless of the quality of the gate insulator as a condition of equilibrium between the layers, just as a depletion layer is formed in a pn junction. The resulting channel is created very near to the gate electrode, resulting in gate control as effective as in a MOSFET. The silicon-based MOSFET has been successful primarily because the silicon–silicon dioxide system provides a stable interface with low trap densities, and because the oxide is impermeable to many environmental contaminants, has a high breakdown strength, and is easy to grow uniformly and reproducibly [Nicollian and Brews, 1982]. These attributes allow easy fabrication using lithographic processes, resulting in integrated circuits (ICs), with very small devices, very large device counts, and very high reliability at low cost. Because the importance of the MOSFET lies in this relationship to high-density manufacture, an emphasis of this article is to describe the issues involved in continuing miniaturization. An additional advantage of the MOSFET is that it can be made using either electrons or holes as channel carrier. Using both types of devices in so-called complementary MOS (CMOS) technology allows circuits that draw no dc power if current paths include at least one series connection of both types of device because, in steady state, only one or the other type conducts, not both at once. Of course, in exercising the circuit, power is drawn during switching of the devices. This flexibility in choosing n- or p-channel devices has enabled large circuits to be made that use low power levels. Hence, complex systems can be manufactured without expensive packaging or cooling requirements. Current-Voltage Characteristics The derivation of the current-voltage characteristics of the MOSFET can be found in several sources [Annara- tone, 1986; Brews, 1981; Pierret, 1990]. Here a qualitative discussion is provided. Strong-Inversion Characteristics In Fig. 24.44 the source-drain current I D is plotted versus drain-to-source voltage V D (the I-V curves for the MOSFET). At low V D the current increases approximately linearly with increased V D , behaving like a simple resistor with a resistance that is controlled by the gate voltage V G : as the gate voltage is made more attractive for channel carriers, the channel becomes stronger, more carriers are contained in the channel, and its resistance R ch drops. Hence, at larger V G the current is larger. ? 2000 by CRC Press LLC At large V D the curves flatten out, and the current is less sensitive to drain bias. The MOSFET is said to be in saturation. There are different reasons for this behavior, depending upon the field along the channel caused by the drain voltage. If the source-drain separation is short, near or below a micrometer, the usual drain voltage is sufficient to create fields along the channel of more than a few 210 4 V/cm. In this case the carrier energy is sufficient for carriers to lose energy by causing vibrations of the silicon atoms composing the crystal (optical phonon emission). Consequently, the carrier velocity does not increase much with increased field, saturating at a value u sat < 10 7 cm/s in silicon MOSFETs. Because the carriers do not move faster with increased V D , the current also saturates. For longer devices the current-voltage curves saturate for a different reason. Consider the potential along the insulator-channel interface, the surface potential. Whatever the surface potential is at the source end of the channel, it varies from the source end to a value larger at the drain end by V D because the drain potential is V D higher than the source. The gate, on the other hand, is at the same potential everywhere. Thus, the difference in potential between the gate and the source is larger than that between the gate and the drain. Correspondingly, the oxide field at the source is larger than that at the drain, and as a result less charge can be supported at the drain. This reduction in attractive power of the gate reduces the number of carriers in the channel at the drain end, increasing channel resistance. In short, we have I D ?V D /R ch , but the channel resistance R ch = R ch (V D ) is increasing with V D . As a result, the current-voltage curves do not continue along the initial straight line, but bend over and saturate. Another difference between the current-voltage curves for short devices and those for long devices is the dependence on gate voltage. For long devices, the current level in saturation, I D,sat , increases quadratically with gate bias. The reason is that the number of carriers in the channel is proportional to V G – V TH (where V TH is the threshold voltage), as is discussed later, the channel resistance R ch μ 1/(V G – V TH ), and the drain bias in saturation is approximately V G . Thus, I D,sat = V D /R ch μ (V G – V TH ) 2 , and we have quadratic dependence. When FIGURE 24.44 Drain current I D versus drain voltage V D for various choices of gate bias V G . The dashed-line curves are for a long-channel device for which the current in saturation increases quadratically with gate bias. The solid-line curves are for a short-channel device that is approaching velocity saturation and thus exhibits a more linear increase in saturation current with gate bias, as discussed in the text. ? 2000 by CRC Press LLC the carrier velocity is saturated, however, the dependence of the current on drain bias is suppressed because the speed of the carriers is fixed at u sat , and I D,sat μ u sat /R ch μ (V G – V TH ) u sat , a linear gate-voltage dependence. As a result, the current available from a short device is not as large as would be expected if we assumed it behaved like a long device. Subthreshold Characteristics Quite different current-voltage behavior is seen in subthreshold, that is, for gate biases so low that the channel is in weak inversion. In this case the number of carriers in the channel is so small that their charge does not affect the potential, and channel carriers simply must adapt to the potential set up by the electrodes and the dopant ions. Likewise, in subthreshold any flow of current is so small that it causes no potential drop along the interface, which becomes an equipotential. As there is no lateral field to move the channel carriers, they move by diffusion only, driven by a gradient in carrier density set up because the drain is effective in reducing the carrier density at the drain end of the channel. In subthreshold the current is then independent of drain bias once this bias exceeds a few tens of millivolts, enough to reduce the carrier density at the drain end of the channel to near zero. In short devices, however, the source and drain are close enough together to begin to share control of the potential with the gate. If this effect is too strong, a drain-voltage dependence of the subthreshold characteristic then occurs, which is undesirable because it increases the MOSFET off current, and can cause a drain-bias dependent threshold voltage. Although for a well-designed device there is no drain-voltage dependence in subthreshold, gate-bias depen- dence is exponential. The surface is lowered in energy relative to the semiconductor body by the action of the gate. If this surface potential is f S below that of the body, the carrier density is enhanced by a Boltzmann factor exp(qf S /kT) relative to the body concentration, where kT/q = the thermal voltage ? 25 mV at 290 K. As f S is roughly proportional to V G , this exponential dependence on f S leads to an exponential dependence upon V G for the carrier density and, hence, for the current in subthreshold. Important Device Parameters A number of MOSFET parameters are important to the performance of a MOSFET. In this subsection some of these parameters are discussed, particularly from the viewpoint of digital ICs. Threshold Voltage The threshold voltage is vaguely defined as the gate voltage V TH at which the channel begins to form. At this voltage devices begin to switch from “off” to “on,” and circuits depend on a voltage swing that straddles this value. Thus, threshold voltage helps in deciding the necessary supply voltage for circuit operation, and also it helps in determining the leakage or “off” current that flows when the device is in the off state. Threshold voltage is controlled by oxide thickness d and by body doping. To control the body doping, ion implantation is used so that the dopant-ion density is not simply a uniform extension of the bulk, background level N B ions/unit volume but has superposed upon it an implanted-ion density. To estimate the threshold voltage, we need a picture of what happens in the semiconductor under the gate as the gate voltage is changed from its off level toward threshold. If we imagine changing the gate bias from its off condition toward threshold, at first the result is to repel majority carriers, forming a surface depletion layer (refer to Fig. 24.43). In the depletion layer there are almost no carriers present, but there are dopant ions. In n-type material these dopant ions are positive donor impurities that cannot move under fields because they are locked in the silicon lattice, where they have been deliberately introduced to replace silicon atoms. In p-type material these dopant ions are negative acceptors. Thus, each charge added to the gate electrode to bring the gate voltage closer to threshold causes an increase in the depletion-layer width sufficient to balance the gate charge by an equal but opposite charge of dopant ions in the silicon depletion layer. This expansion of the depletion layer continues to balance the addition of gate charge until threshold is reached. Then this charge response changes: above threshold any additional gate charge is balanced by an increasingly strong inversion layer or channel. The border between a depletion-layer and an inversion-layer response, threshold, should occur when ? 2000 by CRC Press LLC (24.32) where df S is the small change in surface potential that corresponds to our incremental change in gate charge, qN inv is the inversion-layer charge/unit area, and Q D is the depletion-layer charge/unit area. According to Eq. (24.32), the two types of response are equal at threshold, so one is larger than the other on either side of this condition. To be more quantitative, the rate of increase in qN inv is exponential; that is, its rate of change is proportional to qN inv , so as qN inv increases, so does the left side of Eq. (24.32). On the other hand, Q D has a square-root dependence on f S , which means its rate of change becomes smaller as Q D increases. Thus, as surface potential is increased, the left side of Eq. (24.32) increases proportional to qN inv until, at threshold, Eq. (24.32) is satisfied. Then, beyond threshold, the exponential increase in qN inv with f S swamps Q D , making change in qN inv the dominant response. Likewise, below threshold, the exponential decrease in qN inv with decreasing f S makes qN inv negligible and change in Q D becomes the dominant response. The abruptness of this change in behavior is the reason for the term threshold to describe MOSFET switching. To use Eq. (24.32) to find a formula for threshold voltage, we need expressions for N inv and Q D . Assuming the interface is held at a lower energy than the bulk due to the charge on the gate, the minority-carrier density at the interface is larger than in the bulk semiconductor, even below threshold. Below threshold and even up to the threshold of Eq. (24.32), the number of charges in the channel/unit area N inv is given for n-channel devices approximately by [Brews, 1981]: (24.33) where the various symbols are defined as follows: n i = intrinsic carrier density/unit volume ? 10 10 /cm 3 in silicon at 290 K, and V S = body reverse bias, if any. The first factor, d INV , is an effective depth of minority carriers from the interface given by (24.34) where Q D = depletion-layer charge/unit area due to charged dopant ions in the region where there are no carriers and e s is the dielectric permittivity of the semiconductor. Equation (24.33) expresses the net minority-carrier density/unit area as the product of the bulk minority- carrier density/unit volume, n i 2 /N B , with the depth of the minority-carrier distribution d INV multiplied in turn by the customary Boltzmann factor exp[q(f S – V S )/kT] expressing the enhancement of the interface density over the bulk due to lower energy at the interface. The depth d INV is related to the carrier distribution near the interface using the approximation (valid in weak inversion) that the minority-carrier density decays exponen- tially with distance from the oxide-silicon surface. In this approximation, d INV is the centroid of the minority- carrier density. For example, for a uniform bulk doping of 10 16 dopant ions/cm 3 at 290 K, using Eq. (24.33) and the surface potential at threshold from Eq. (24.38) below (f TH = 0.69 V), there are Q D /q = 3210 11 charges/cm 2 in the depletion layer at threshold. This Q D corresponds to a d INV = 5.4 nm and a carrier density at threshold of N inv = 5.4210 9 charges/cm 2 . The next step in using the definition of threshold, Eq. (24.32), is to introduce the depletion-layer charge/unit area Q D . For the ion-implanted case, Q D is made up of two terms [Brews, 1981]: (24.35) dqN d dQ d S D S inv ff = Nd n N e i B qVkT SS inv INV / ? - 2 ()f d kT q Q s D INV / = e QqNLq kTm qD DBBTH I =-- []{} +21 1 12 f ( / ) ? 2000 by CRC Press LLC where the first term is Q B , the depletion-layer charge from bulk dopant atoms in the depletion layer with a width that has been reduced by the first moment of the implant, namely, m 1 given in terms of the centroid of the implant x C by (24.36) The second term is the additional charge due to the implanted-ion density within the depletion layer, D I ions per unit area. The Debye length L B is defined as (24.37) where e s is the dielectric permittivity of the semiconductor. The Debye length is a measure of how deeply a variation of surface potential penetrates into the body when D I = 0 and the depletion layer is of zero width. Approximating qN inv by Eq. (24.33) and Q D by Eq. (24.35), Eq. (24.32) determines the surface potential at threshold, f TH , to be (24.38) where the new symbols are defined as follows: Q B = depletion-layer charge/unit area due to bulk body dopant N B in the depletion layer, and qD I = depletion-layer charge/unit area due to implanted ions in the depletion layer between the inversion-layer edge and the depletion-layer edge. Because even a small increase in f S above f TH causes a large increase in qN inv , which can balance a rather large change in gate charge or gate voltage, f S does not increase much as V G – V TH increases. Nonetheless, in strong inversion N inv ? 10 12 charges/cm 2 , so in strong inversion f S will be about 10 kT/q larger than f TH . Equation (24.38) indicates for uniform doping (no implant, D I = 0) that threshold occurs approximately for f S = f TH = 2(kT/q)ln(N B /n i ) o 2f B , but for the nonuniformly doped case a larger surface potential is needed, assuming the case of a normal implant where D I is positive, increasing the dopant density. The implant increases the required surface potential because the field at the surface is larger, narrowing the inversion layer, and reducing the channel strength for f S = 2f B . Hence, a somewhat larger surface potential is needed to increase qN inv to the point that Eq. (24.32) is satisfied. Equation (24.38) would not apply if a significant fraction of the implant were confined to lie within the inversion layer itself. However, no realistic implant can be confined within a distance comparable to an inversion-layer thickness (a few tens of nanometers), so Eq. (24.38) covers practical cases. With the surface potential f TH known, the potential on the gate at threshold F TH can be found if we know the oxide field F ox by simply adding the potential drop across the semiconductor to that across the oxide. That is, F TH = f TH + F ox d, with d = oxide thickness and F ox given by Gauss’s law as (24.39) There are two more complications in finding the threshold voltage. First, the gate voltage V TH usually differs from the gate potential F TH at threshold because of a work-function difference between the body and the gate material. This difference causes a spontaneous charge exchange between the two materials as soon as the MOSFET is placed in a circuit allowing charge transfer to occur. Thus, even before any voltage is applied to the device, a potential difference exists between the gate and the body due to spontaneous charge transfer. The m Dx NL IC BB 1 2 = L kT qqN B s B 2 o e f TH B i I B kT q N n kT q qD Q =++ ? è ? ? ? ÷ 21ln ln e ox ox FQ D = ? 2000 by CRC Press LLC second complication affecting threshold voltage is the existence of charges in the insulator and at the insulator- semiconductor interface. These nonideal contributions to the overall charge balance are due to traps and fixed charges incorporated during the device processing. Ordinarily interface-trap charge is negligible (<10 10 /cm 2 in silicon MOSFETs), and the other nonideal effects upon threshold voltage are accounted for by introducing the flatband voltage V FB , which corrects the gate bias for these contributions. Then, using Eq. (24.39) with F ox = (V TH – V FB – f TH )/d we find (24.40) which determines V TH even for the nonuniformly doped case, using Eq. (24.38) for f TH and Q D at threshold from Eq. (24.35). If interface-trap charge/unit area is not negligible, then terms in the interface-trap charge/unit area Q IT must be added to Q D in Eq. (24.40). From Eqs. (24.35) and (24.38), the threshold voltage depends upon the implanted dopant-ion profile only through two parameters, the net charge introduced by the implant in the region between the inversion layer and the depletion-layer edge qD I , and the centroid of this portion of the implanted charge x C . As a result, a variety of implants can result in the same threshold, ranging from the extreme of a d-function spike implant of dose D I /unit area located at the centroid x C , to a box-type rectangular distribution with the same dose and centroid, namely, a rectangular distribution of width x W = 2x C and volume density D I /x W . (Of course, x W must be no larger than the depletion-layer width at threshold for this equivalence to hold true, and x C must not lie within the inversion layer.) This weak dependence on the details of the profile leaves flexibility to satisfy other requirements, such as control of off current. As already said, for gate biases V G > V TH any gate charge above the threshold value is balanced mainly by inversion-layer charge. Thus, the additional oxide field, given by (V G – V TH )/d, is related by Gauss’s law to the inversion-layer carrier density approximately by (24.41) which shows that channel strength above threshold is proportional to V G – V TH , an approximation often used in this article. Thus, the switch in balancing gate charge from the depletion layer to the inversion layer causes N inv to switch from an exponential gate-voltage dependence in subthreshold to a linear dependence above threshold. For circuit analysis Eq. (24.41) is a convenient definition of V TH because it fits current-voltage curves. If this definition is chosen instead of the charge-balance definition of Eq. (24.32), then Eqs. (24.32) and (24.38) result in an approximation to f TH . Driving Ability and I D,sat The driving ability of the MOSFET is proportional to the current it can provide at a given gate bias. One might anticipate that the larger this current, the faster the circuit. Here this current is used to find some response times governing MOSFET circuits. MOSFET current is dependent upon the carrier density in the channel, or upon V G – V TH , see Eq. (24.41). For a long-channel device, driving ability depends also on channel length. The shorter the channel length, L, the greater the driving ability, because the channel resistance is directly proportional to the channel length. Although it is an oversimplification, let us suppose that the MOSFET is primarily in saturation during the driving of its load. This simplification will allow a clear discussion of the issues involved in making faster MOSFET’s without complicated mathematics. Assuming the MOSFET to be saturated over most of the switch- ing period, driving ability is proportional to current in saturation, or to (24.42) VV Q d TH FB TH D =++f e ox e ox inv VV d qN GTH - ? I Z dL VV DGTH,sat ox =- ( ) em 2 2 ? 2000 by CRC Press LLC where the factor of two results from the saturating behavior of the I-V curves at large drain biases and Z is the width of the channel normal to the direction of current flow. Evidently, for long devices driving ability is quadratic in V G – V TH , and inversely proportional to d. The result of Eq. (24.42) holds for long devices. For short-channel devices, as explained for Fig. 24.44, the larger fields exerted by the drain electrode cause velocity saturation and, as a result, I D,sat is given roughly by [Einspruch and Gildenblat, 1989] (24.43) where u sat is the carrier saturation velocity, about 10 7 cm/s for silicon at 290 K, F sat is the field at which velocity saturation sets in, about 5210 4 V/cm for electrons and not well established as *10 5 V/cm for holes in silicon MOSFETs. For Eq. (24.43) to agree with Eq. (24.42) at long L, we need m ? 2u sat /F sat ? 400 cm 2 (V·s) for electrons in silicon MOSFETs, which is only roughly correct. Nonetheless, we can see that for devices in the submicron channel length regime, I D,sat tends to become independent of channel length L and becomes more linear with V G – V TH and less quadratic (see Fig. 24.44). Equation (24.43) shows that velocity saturation is significant when V G /L * F sat for example, when L & 0.5 mm if V G - V TH = 2.5 V. To relate I D,sat to a gate response time, t G , consider one MOSFET driving an identical MOSFET as load capacitance. Then the current from Eq. (24.43) charges this capacitance to a voltage V G in a gate response time t G given by [Shoji, 1988] (24.44) where C G is the MOSFET gate capacitance C G = C ox + C par , with C ox = e ox ZL/d the MOSFET oxide capacitance, and C par the parasitic component of the gate capacitance [Chen, 1990]. The parasitic capacitance C par is due mainly to overlap of the gate electrode over the source and drain and partly to fringing-field and channel-edge capacitances. For short-channel lengths, C par is a significant part of C G , and keeping C par under control as L is reduced is an objective of gate-drain alignment technology. Typically, V TH ? V G /4, so (24.45) Thus, on an intrinsic level, the gate response time is closely related to the transit time of an electron from source to drain, which is L/u sat in velocity saturation. At shorter L, a linear reduction in delay with L is predicted, while for longer devices the improvement can be quadratic in L, depending upon how V G is scaled as L is reduced. The gate response time is not the only delay in device switching, because the drain-body pn junction also must charge or discharge for the MOSFET to change state [Shoji, 1988]. Hence, we must also consider a drain response time t D . Following Eq. (24.44), we suppose that the drain capacitance C D is charged by the supply voltage through a MOSFET in saturation so that (24.46) I Z d VV VVFL D GTH GTH , () sat ox sat sat ? - -+ eu 2 t u G GG D GG TH GTH CV I L C C VVV FL VV = =+ ? è ? ? ? ÷ -+ - , () () sat sat par ox sat 1 2 t u G G L C C FL V ? ? è ? ? ? ÷ + ? è ? ? ? ÷ + ? è ? ? ? ÷ sat par ox sat 11318.. tt D DG D D G G CV I C C == ,sat ? 2000 by CRC Press LLC Equation (24.46) suggests that t D will show a similar improvement to t G as L is reduced, provided that C D /C G does not increase as L is reduced. However, C ox μ L/d, and the major component of C par , namely, the overlap capacitance contribution, leads to C par μ L ovlp /d where L ovlp is roughly three times the length of overlap of the gate over the source or drain [Chen, 1990]. Then C G μ (L + L ovlp )/d and, to keep the C D /C G ratio from increasing as L is reduced, either C D or oxide-thickness d must be reduced along with L. Clever design can reduce C D . For example, various raised-drain designs reduce the drain-to-body capacitance by separating much of the drain area from the body using a thick oxide layer. The contribution to drain capacitance stemming from the sidewall depletion-layer width next to the channel region is more difficult to handle, because the sidewall depletion layer is deliberately reduced during miniaturization to avoid short-channel effects, that is, drain influence upon the channel in competition with gate control. As a result this sidewall contribution to the drain capacitance tends to increase with miniaturization unless junction depth can be shrunk. Equations (24.45) and (24.46) predict reduction of response times by reduction in channel length L. Decreas- ing oxide thickness leads to no improvement in t G , but Eq. (24.46) shows a possibility of improvement in t D , because C D is independent of d while C G increases as d decreases. The ring oscillator, a closed loop of an odd number of inverters, is a test circuit whose performance depends primarily on t G and t D . Gate delay/stage for ring oscillators is found to be near 12 ps/stage at 0.1 mm channel length, and 60 ps/stage at 0.5 mm. For circuits, interconnection capacitances and fan-out (multiple MOSFET loads) will increase response times beyond the device response time, even when parasitics are taken into account. Thus, we are led to consider interconnection delay, t INT . Although a lumped model suggests, as with Eq. (24.46), that t INT ? (C INT /C G ) t G , the length of interconnections requires a distributed model. Interconnection delay is then (24.47) where the new symbols are R INT = interconnection resistance, C INT = interconnection capacitance, and we have assumed that the interconnection joins a MOSFET driver in saturation to a MOSFET load C G . For small R INT , t INT is dominated by the last term, which resembles Eqs. (24.44) and (24.46). However, unlike the ratio C D /C G in Eq. (24.46), it is difficult to reduce or even maintain the ratio C IN T /C G in Eq. (24.47) as L is reduced. Remember, C G μ Z (L + L ovlp )/d. Reduction of L therefore tends to increase C IN T /C G , especially because interconnect cross sections cannot be reduced without impractical increases in R INT . What is worse, along with reduction in L, chip sizes usually increase, making line lengths longer, increasing R INT even at constant cross section. As a result, interconnection delay becomes a major problem as L is reduced. The obvious way to keep C IN T /C G under control is to increase the device width Z so that C G μ Z (L + L ovlp )/d remains constant as L is reduced. A better way is to cascade drivers of increasing Z [Chen, 1990; Shoji, 1988]. Either solution requires extra area, however, reducing the packing density that is a major objective in decreasing L in the first place. An alternative is to reduce the oxide thickness d, a major technology objective today. Transconductance Another important device parameter is the small-signal transconductance g m [Sedra and Smith, 1991; Haznedar, 1991], which determines the amount of output current swing at the drain that results from a given input voltage variation at the gate, that is, the small-signal gain: (24.48) Using the chain rule of differentiation, the transconductance in saturation can be related to the small-signal transition or unity-gain frequency, which determines at how high a frequency w the small-signal current gain *i out /i in * = g m /(wC G ) drops to unity. Using the chain rule, tt INT INT INT INT INT =+++ ? è ? ? ? ÷ RC RC C C G G G 2 1 g I V m D G V D = = ? ? const ? 2000 by CRC Press LLC (24.49) where C G is the oxide capacitance of the device, C G = ?Q G /?V G *V D with Q G = the charge on the gate electrode. The frequency w T is a measure of the small-signal, high-frequency speed of the device, neglecting parasitic resistances. Using Eq. (24.43) in Eq. (24.49) we find that the transition frequency also is related to the transit time L/u sat of Eq. (24.45), so that both the digital and small-signal circuit speeds are related to this parameter. Output Resistance and Drain Conductance For small-signal circuits the output resistance r o of the MOSFET [Sedra and Smith, 1991] is important in limiting the gain of amplifiers. This resistance is related to the small-signal drain conductance g D in saturation by (24.50) If the MOSFET is used alone as a simple amplifier with a load line set by a resistor R L , the gain becomes (24.51) showing how gain is reduced if r o is reduced to a value approaching R L . As devices are miniaturized, r o is decreased, g D increased, due to several factors. At moderate drain biases, the main factor is channel-length modulation, the reduction of the channel length with increasing drain voltage that results when the depletion region around the drain expands toward the source, causing L to become drain- bias dependent. At larger drain biases, a second factor is drain control of the inversion-layer charge density, which can compete with gate control in short devices. This is the same mechanism discussed later in the context of subthreshold behavior. At rather high drain bias, carrier multiplication further lowers r o . In a digital inverter, a lower r o widens the voltage swing needed to cause a transition in output voltage. This widening increases power loss due to current spiking during the transition, and reduces noise margins [Annaratone, 1986]. It is not, however, a first-order concern in device miniaturization for digital applications. Because small-signal circuits are more sensitive to r o than digital circuits, MOSFETs designed for small-signal applications cannot be made as small as those for digital applications. Limitations upon Miniaturization A major factor in the success of the MOSFET has been its compatibility with processing useful down to very small dimensions. Today channel lengths (source-to-drain spacings) of 0.5 mm are manufacturable, and further reduction to 0.1 mm has been achieved for limited numbers of devices in test circuits such as ring oscillators. In this section some of the limits that must be considered in miniaturization are outlined [Brews, 1990]. Subthreshold Control When a MOSFET is in the “off” condition, that is, when the MOSFET is in subthreshold, the off current drawn with the drain at supply voltage must not be too large in order to avoid power consumption and discharge of ostensibly isolated nodes [Shoji, 1988]. In small devices, however, the source and drain are closely spaced, so there exists a danger of direct interaction of the drain with the source, rather than an interaction mediated by the gate and channel. In an extreme case, the drain may draw current directly from the source, even though the gate is “off” (punchthrough). A less extreme but also undesirable case occurs when the drain and gate jointly control the carrier density in the channel (drain-induced barrier lowering, or drain control of threshold voltage). g I Q Q V C m D G G G TG == ? ? ? ? w ,sat r g V I o D D D V G == = 1 ? ? ,sat const u u o m Lo Lo mL g Rr Rr gR in = + ￡ ? 2000 by CRC Press LLC In such a case, the on–off behavior of the MOSFET is not controlled by the gate alone, and switching can occur over a range of gate voltages dependent on the drain voltage. Reliable circuit design under these circumstances is very complicated, and testing for design errors is prohibitive. Hence, in designing MOSFETs, a drain-bias independent subthreshold behavior is necessary. A measure of the range of influence of the source and drain is the depletion-layer width of the associated pn junctions. The depletion layer of such a junction is the region in which all carriers have been depleted, or pushed away, due to the potential drop across the junction. This potential drop includes the applied bias across the junction and a spontaneous built-in potential drop induced by spontaneous charge exchange when p and n regions are brought into contact. The depletion-layer width W of an abrupt junction is related to potential drop V and dopant-ion concentration/unit volume N by (24.52) To avoid subthreshold problems, a commonly used rule of thumb is to make sure that the channel length is longer than a minimum length L min related to the junction depth r j , the oxide thickness d, and the depletion- layer widths W S and W D of the source and drain by [Brews, 1990] (24.53) where the empirical constant A = 0.88 nm –1/3 if r j , W S , and W D are in micrometers and d is in nanometers. Equation (24.53) shows that smaller devices require shallower junctions (smaller r j ), thinner oxides (smaller d), or smaller depletion-layer widths (smaller voltage levels or heavier doping). These requirements introduce side effects that are difficult to control. For example, if the oxide is made thinner while voltages are not reduced proportionately, then oxide fields increase, requiring better oxides. If junction depths are reduced, better control of processing is required, and the junction resistance is increased due to smaller cross sections. To control this resistance, various self-aligned contact schemes have been developed to bring the source and drain contacts closer to the gate [Brews, 1990; Einspruch and Gildenblat, 1989], reducing the resistance of these connections. If depletion-layer widths are reduced by increasing the dopant-ion density the driving ability of the MOSFET suffers because the threshold voltage increases. That is, Q D increases in Eq. (24.40), reducing V G – V TH . Thus, for devices that are not velocity-saturated, that is, devices where V G /L & F sat , increasing V TH results in slower circuits. As secondary consequences of increasing dopant-ion density, channel conductance is further reduced due to the combined effects of increased scattering of electrons from the dopant atoms and increased oxide fields that pin carriers in the inversion layer closer to the insulator–semiconductor interface, increasing scattering at the interface. These effects also reduce driving ability, although for shorter devices they are important only in the linear region (that is, below saturation), assuming that mobility m is more strongly affected than saturation velocity u sat . Hot-Electron Effects Another limit upon how small a MOSFET can be made is a direct result of the larger fields in small devices. Let us digress to consider why proportionately larger voltages, and thus larger fields, are used in smaller devices. First, according to Eq. (24.45), t G is shortened if voltages are increased, at least so long as V G /L & F sat 5210 4 V/cm. If t G is shortened this way, then so are t D and t INT , Eqs. (24.46) and (24.47). Thus, faster response is gained by increasing voltages into the velocity saturation region. Second, the fabricational control of smaller devices has not improved proportionately as L has shrunk, so there is a larger percentage variation in device parameters with smaller devices. Thus, disproportionately larger voltages are needed to ensure that all devices operate in the circuit, to overcome this increased fabricational “noise.” Thus, to increase speed and to cope with fabricational variations, fields go up in smaller devices. W V qN s = ? è ? ? ? ÷ 2 12 e / LArdWW jS Dmin [( )]=+ 2 13/ ? 2000 by CRC Press LLC As a result of these larger fields along the channel direction, a small fraction of the channel carriers have enough energy to enter the insulating layer near the drain. In silicon-based p-channel MOSFETs, energetic holes can become trapped in the oxide, leading to a positive oxide charge near the drain that reduces the strength of the channel, degrading device behavior. In n-channel MOSFETs, energetic electrons entering the oxide create interface traps and oxide wear-out, eventually leading to gate-to-drain shorts [Pimbley et al., 1989]. To cope with these problems “drain-engineering” has been tried, the most common solution being the lightly doped drain [Chen, 1990; Einspruch and Gildenblat, 1989; Pimbley et al., 1989]. In this design, a lightly doped extension of the drain is inserted between the channel and the drain proper. To keep the field moderate and reduce any peaks in the field, the lightly doped drain extension is designed to spread the drain-to-channel voltage drop as evenly as possible. The aim is to smooth out the field at a value close to F sat so that energetic carriers are kept to a minimum. The expense of this solution is an increase in drain resistance and a decreased gain. To increase packing density, this lightly doped drain extension can be stacked vertically alongside the gate, rather than laterally under the gate, to control the overall device area. Thin Oxides According to Eq. (24.53), thinner oxides allow shorter devices and therefore higher packing densities for devices. In addition, driving ability is increased, shortening response times for capacitive loads, and output resistance and transconductance are increased. There are some basic limitations upon how thin the oxide can be made. For instance, there is a maximum oxide field that the insulator can withstand. It is thought that the intrinsic breakdown voltage of SiO 2 is of the order of 10 7 V/cm, a field that can support ? 2210 13 charges/cm 2 , a large enough value to make this field limitation secondary. Unfortunately, as they are presently manufactured, the intrinsic breakdown of MOSFET oxides is much less likely to limit fields than defect-related leakage or breakdown, and control of these defects has limited reduction of oxide thicknesses in manufacture to about 5 nm to date. If defect-related problems could be avoided, the thinnest useful oxide would probably be about 3 nm, limited by direct tunneling of channel carriers to the gate. This tunneling limit is not well established, and also is subject to oxide-defect enhancement due to tunneling through intermediate defect levels. Thus, the manufacture of thin oxides is a very active area of exploration. Dopant-Ion Control As devices are made smaller, the precise positioning of dopant inside the device is critical. At high temperatures during processing, dopant ions can move. For example, source and drain dopants can enter the channel region, causing position dependence of threshold voltage. Similar problems occur in isolation structures that separate one device from another [Pimbley et al., 1989; Einspruch and Gildenblat, 1989; Wolf, 1995]. To control these thermal effects, process sequences are carefully designed to limit high-temperature steps. This design effort is shortened and improved by the use of computer modeling of the processes. Dopant-ion movement is complex, however, and its theory is made more difficult by the growing trend to use rapid thermal processing that involves short-time heat treatments. As a result, dopant response is not steady state, but transient. Computer models of transient response are primitive, forcing further advance in small-device design to be more empirical. Other Limitations Besides limitations directly related to the MOSFET, there are some broader difficulties in using MOSFETs of smaller dimension in chips involving even greater numbers of devices. Already mentioned is the increased delay due to interconnections that are lengthening due to increasing chip area and increasing complexity of connec- tion. The capacitive loading of MOSFETs that must drive signals down these lines can slow circuit response, requiring extra circuitry to compensate. Another limitation is the need to isolate devices from each other [Brews, 1990; Chen 1990; Einspruch and Gildenblat, 1989; Pimbley et al., 1989; Wolf, 1995], so their actions remain uncoupled by parasitics. As isolation structures are reduced in size to increase device densities, new parasitics are discovered. A developing solution to this problem is the manufacture of circuits on insulating substrates, silicon-on-insulator technology [Colinge, 1991]. To succeed, this approach must deal with new problems, such as the electrical quality of the underlying silicon–insulator interface and the defect densities in the silicon layer on top of this insulator. ? 2000 by CRC Press LLC Defining Terms Channel: The conducting region in a MOSFET between source and drain. In an enhancement-mode (or normally off) MOSFET, the channel is an inversion layer formed by attraction of minority carriers toward the gate. These carriers form a thin conducting layer that is prevented from reaching the gate by a thin gate-oxide isulating layer when the gate bias exceeds threshold. In a buried-channel, or depletion-mode (or normally on) MOSFET, the channel is present even at zero gate bias, and the gate serves to increase the channel resistance when its bias is nonzero. Thus, this device is based on majority-carrier modulation, like a MESFET. Gate: The control electrode of a MOSFET. The voltage on the gate capacitively modulates the resistance of the connecting channel between the source and drain. Source, drain: The two output contacts of a MOSFET, usually formed as pn junctions with the substrate or body of the device. Strong inversion: The range of gate biases corresponding to the “on” condition of the MOSFET. At a fixed gate bias in this region, for low drain-to-source biases the MOSFET behaves as a simple gate-controlled resistor. At larger drain biases, the channel resistance can increase with drain bias, even to the point that the current saturates, or becomes independent of drain bias. Substrate or body: The portion of the MOSFET that lies between the source and drain and under the gate. The gate is separated from the body by a thin gate insulator, usually silicon dioxide. The gate modulates the conductivity of the body, providing a gate-controlled resistance between the source and drain. The body is sometimes dc-biased to adjust overall circuit operation. In some circuits the body voltage can swing up and down as a result of input signals, leading to “body-effect” or “back-gate bias” effects that must be controlled for reliable circuit response. Subthreshold: The range of gate biases corresponding to the “off” condition of the MOSFET. In this regime the MOSFET is not perfectly “off” but conducts a leakage current that must be controlled to avoid circuit errors and power consumption. Threshold: The gate bias of a MOSFET that marks the boundary between “on” and “off” conditions. Related Topic 13.2 Parameter Extraction for Analog Circuit Simulation References The following references are not to the original sources of the ideas discussed in this article, but have been chosen to be generally useful to the reader. M. Annaratone, Digital CMOS Circuit Design, Boston: Kluwer Academic, 1986. J. R. Brews, “Physics of the MOS transistor” in Applied Solid State Science, Supplement 2A, D. Kahng, Ed., New York: Academic, 1981. J. R. Brews, “The submicron MOSFET” in High-Speed Semiconductor Devices, S. M. Sze, Ed., New York: Wiley, 1990, pp. 139–210. J. Y. Chen, CMOS Devices and Technology for VLSI, Englewood Cliffs, N.J.: Prentice-Hall, 1990. J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, Boston: Kluwer Academic, 1991. H. Haznedar, Digital Microelectronics, Redwood City, Calif.: Benjamin-Cummings, 1991. M.A. Hollis and R.A. Murphy, “Homogeneous field-effect transistors,” in High-Speed Semiconductor Devices, S. M. Sze, Ed., New York: Wiley, 1990, pp. 211–282. N.G. Einspruch and G. Sh. Gildenblat, Eds., VLSI Microstructure Science, vol. 18, Advanced MOS Device Physics, New York: Academic, 1989. N.R. Malik, Electronic Circuits: Analysis, Simulation, and Design, Englewood Cliffs, N.J.: Prentice-Hall, 1995. E.H. Nicollian and J.R. Brews, MOS Physics and Technology, New York: Wiley, 1982, chap. 1. S.J. Pearton and N.J. Shaw, “Heterostructure field-effect transistors” in High-Speed Semiconductor Devices, S.M. Sze, Ed., New York: Wiley, 1990, pp. 283–334. ? 2000 by CRC Press LLC R.F. Pierret, Modular Series on Solid State Devices, Field Effect Devices, 2nd ed., vol. 4, Reading, Mass.: Addison- Wesley, 1990. J.M. Pimbley, M. Ghezzo, H.G. Parks, and D.M. Brown, VLSI Electronics Microstructure Science, Advanced CMOS Process Technology, vol. 19, N. G. Einspruch, Ed., New York: Academic, 1989. S.S. Sedra and K.C. Smith, Microelectronic Circuits, 3rd ed., Philadelphia: Saunders, 1991. M. Shoji, CMOS Digital Circuit Technology, Englewood Cliffs, N.J.: Prentice-Hall, 1988. S. Wolf, Silicon Processing for the VLSI era: volume 3 — the submicron MOSFET, Sunset Beach, CA: Lattice Press, 1995. Further Information The references given in this section have been chosen to provide more detail than is possible to provide in the limited space of this article. In particular, Annaratone [1986] and Shoji [1988] provide much more detail about device and circuit behavior. Chen [1990], Pimbley et al. [1989], and Wolf [1995] provide many technological details of processing and its device impact. Haznedar [1991], Sedra and Smith [1991], and Malik [1995] provide much information about circuits. Brews [1981] and Pierret [1990] provide good discussions of the derivation of the device current-voltage curves and device behavior in all bias regions. ? 2000 by CRC Press LLC