Carpenter, G.L., Choma, Jr., J. “Amplifiers” The Electrical Engineering Handbook Ed. Richard C. Dorf Boca Raton: CRC Press LLC, 2000 28 Amplifiers 28.1Large Signal Analysis DC Operating Point?Graphical Approach?Power Amplifiers 28.2Small Signal Analysis Hybrid-Pi Equivalent Circuit?Hybrid-Pi Equivalent Circuit of a Monolithic BJT?Common Emitter Amplifier?Design Considerations for the Common Emitter Amplifier?Common Base Amplifier?Design Considerations for the Common Base Amplifier?Common Collector Amplifier 28.1 Large Signal Analysis Gordon L. Carpenter Large signal amplifiers are usually confined to using bipolar transistors as their solid state devices because of the large linear region of amplification required. One exception to this is the use of VMOS for large power outputs due to their ability to have a large linear region. There are three basic configurations of amplifiers: common emitter (CE) amplifiers, common base (CB) amplifiers, and common collection(CC) amplifiers. The basic configuration of each is shown in Fig. 28.1. In an amplifier system, the last stage of a voltage amplifier string has to be considered as a large signal amplifier, and generally EF amplifiers are used as large signal amplifiers. This then requires that the dc bias or dc operating point (quiescent point) be located near the center of the load line in order to get the maximum output voltage swing. Small signal analysis can be used to evaluate the amplifier for voltage gain, current gain, input impedance, and output impedance, all of which are discussed later. DC Operating Point Each transistor connected in a particular amplifier configuration has a set of characteristic curves, as shown in Fig. 28.2. When amplifiers are coupled together with capacitors, the configuration is as shown in Fig. 28.3. The load resistor is really the input impedance of the next stage. To be able to evaluate this amplifier, a dc equivalent circuit needs to be developed as shown in Fig. 28.4. This will result in the following dc bias equation: where beta (h FE ) is the current gain of the transistor and V BE is the conducting voltage across the base-emitter junction. This equation is the same for all amplifier configurations. Looking at Fig. 28.3, the input circuit can be reduced to the dc circuit shown in Fig. 28.4 using circuit analysis techniques, resulting in the following equations: I VV RR h CQ BB BE BE FE = - + >> beta Assume 1 Gordon L. Carpenter California State University, Long Beach John Choma, Jr. University of Southern California ? 2000 by CRC Press LLC FIGURE 28.1 Amplifier circuits. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 80. With permission.) FIGURE 28.2 Transistor characteristic curves. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 82. With permission.) FIGURE 28.3 Amplifier circuit. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cum- mings, 1991, p. 92. With permission.) FIGURE 28.4 Amplifier equivalent circuit. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Ben- jamin-Cummings, 1991, p. 82. With permission.) ? 2000 by CRC Press LLC V BB = V TH = V CC (R 1 )/(R 1 + R 2 ) R B = R TH = R 1 //R 2 For this biasing system, the Thévenin equivalent resistance and the Thévenin equivalent voltage can be deter- mined. For design with the biasing system shown in Fig. 28.3, then: R 1 = R B /(1 – V BB /V CC ) R 2 = R B (V CC /V BB ) Graphical Approach To understand the graphical approach, a clear understanding of the dc and ac load lines is necessary. The dc load line is based on the Kirchhoff’s equation from the dc power source to ground (all capacitors open) V CC = v CE + i C R DC where R DC is the sum of the resistors in the collector-emitter loop. The ac load line is the loop, assuming the transistor is the ac source and the source voltage is zero, then V￠ CC = v ce + i C R ac where R ac is the sum of series resistors in that loop with all the capacitors shorted. The load lines then can be constructed on the characteristic curves as shown in Fig. 28.5. From this it can be seen that to get the maximum output voltage swing, the quiescent point, or Q point, should be located in the middle of the ac load line. To place the Q point in the middle of the ac load line, I CQ can be determined from the equation I CQ = V CC /(R DC + R ac ) FIGURE 28.5 Load lines. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 94. With permission.) ? 2000 by CRC Press LLC To minimize distortion caused by the cutoff and saturation regions, the top 5% and the bottom 5% are discarded. This then results in the equation (Fig. 28.6): V o (peak to peak) = 2 (0.9) I CQ (R C //R L ) If, however, the Q point is not in the middle of the ac load line, the output voltage swing will be reduced. Below the middle of the ac load line [Fig. 28.7(a)]: V o (peak to peak) = 2 (I CQ – 0.05 I CMax ) R C //R L Above the middle of the ac load line [Fig. 28.7(b)]: V o (peak to peak) = 2 (0.95 I CMax – I CQ ) R C //R L These values allow the highest allowable input signal to be used to avoid any distortion by dividing the voltage gain of the amplifier into the maximum output voltage swing. The preceding equations are the same for the CB configuration. For the EF configurations, the R C is changed to R E in the equations. FIGURE 28.6 Q point in middle of load line. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 135. With permission.) FIGURE 28.7 Reduced output voltage swing. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 136. With permission.) ? 2000 by CRC Press LLC Power Amplifiers Emitter followers can be used as power amplifiers. Even though they have less than unity voltage gain they can provide high current gain. Using the standard linear EF amplifier for a maximum output voltage swing provides less than 25% efficiency (ratio of power in to power out). The dc current carrying the ac signal is where the loss of efficiency occurs. To avoid this power loss, the Q point is placed at I CQ equal to zero, thus using the majority of the power for the output signal. This allows the efficiency to increase to as much as 70%. Full signal amplification requires one transistor to amplify the positive portion of the input signal and another transistor to amplify the negative portion of the input signal. In the past, this was referred to as push-pull operation. A better system is to use an NPN transistor for the positive part of the input signal and a PNP transistor for the negative part. This type of operation is referred to as Class B complementary symmetry operation (Fig. 28.8). In Fig. 28.8, the dc voltage drop across R 1 provides the voltage to bias the transistor at cutoff. Because these are power transistors, the temperature will change based on the amount of power the transistor is absorbing. This means the base-emitter junction voltage will have to change to keep I CQ = 0. To compensate for this change in temperature, the R 1 resistors are replaced with diodes or transistors connected as diodes with the same turn- on characteristics as the power transistors. This type of configuration is referred to as the complementary symmetry diode compensated (CSDC) amplifier and is shown in Fig. 28.9. To avoid crossover distortion, small resistors can be placed in series with the diodes so that I CQ can be raised slightly above zero to get increased amplification in the cutoff region. Another problem that needs to be addressed is the possibility of thermal runaway. This can be easily solved by placing small resistors in series with the emitters of the power transistors. For example, if the load is an 8-W speaker, the resistors should not be greater than 0.47 W to avoid output signal loss. To design this type of amplifier, the dc current in the bias circuit must be large enough so that the diodes remain on during the entire input signal. This requires the dc diode current to be equal to or larger than the zero to peak current of the input signal, or I D 3 I ac (0 to peak) (V CC /2 – V BE )/R 2 = I B (0 to peak) + V L (0 to peak)/R 2 FIGURE 28.8 Complementary symmetry power amplifier. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 248. With permission.) ? 2000 by CRC Press LLC When designing to a specific power, both I B and V L can be determined. This allows the selection of the value of R 2 and the equivalent circuit shown in Fig. 28.10 can be developed. Using this equivalent circuit, both the input resistance and the current gain can be shown. R f is the forward resistance of the diodes. R in = (R f + R 2 )//[R f + (R 2 //BetaR L )] P o = I Cmax R L /2 The power rating of the transistors to be used in this circuit should be greater than P rating =V 2 CC /(4Pi 2 R L ) C 1 = 1/(2Pi f low R L ) C 2 = 10/[2Pi f low (R in + R i )] where R i is the output impedance of the previous stage and f low is the desired low frequency cutoff of the amplifier. Related Topics 24.1 Junction Field-Effect Transistors?30.1 Power Semiconductor Devices FIGURE 28.9 Complimentary symmetry diode compensated power amplifier. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 251. With permission.) FIGURE 28.10 AC equivalent circuit of the CSDC amplifier. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 255. With permission.) ? 2000 by CRC Press LLC References P.R. Gray and R.G. Meyer, Analysis and Design of Analog Integrated Circuits, New York: Wiley, 1984. J. Millman and A. Grabel, Microelectronics, New York: McGraw-Hill, 1987. P.O. Neudorfer and M. Hassul, Introduction to Circuit Analysis, Needham Heights, Mass.: Allyn and Bacon, 1990. C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991. D.L. Schilling and C. Belove, Electronic Circuits, New York: McGraw-Hill, 1989. 28.2 Small Signal Analysis John Choma, Jr. This section introduces the reader to the analytical methodologies that underlie the design of small signal, analog bipolar junction transistor (BJT) amplifiers. Analog circuit and system design entails complementing basic circuit analysis skills with the art of architecting a circuit topology that produces acceptable input-to- output (I/O) electrical characteristics. Because design is not the inverse of analysis, analytically proficient engineers are not necessarily adept at design. However, circuit and system analyses that conduce an insightful understanding of meaningful topological structures arguably foster design creativity. Accordingly, this section focuses more on the problems of interpreting analytical results in terms of their circuit performance implica- tions than it does on enhancing basic circuit analysis skills. Insightful interpretation breeds engineering understanding. In turn, such an understanding of the electrical properties of circuits promotes topological refinements and innovations that produce reliable and manufacturable, high performance electronic circuits and systems. Hybrid-Pi Equivalent Circuit In order for a BJT to function properly in linear amplifier applications, it must operate in the forward active region of its volt–ampere characteristic curves. Two conditions ensure BJT operation in the forward domain. First, the applied emitter-base terminal voltage must forward bias the intrinsic emitter-base junction diode at all times. Second, the instantaneous voltage established across the base-collector terminals of the transistor must preclude a forward biased intrinsic base-collector diode. The simultaneous satisfaction of these two conditions requires appropriate biasing subcircuits, and it imposes restrictions on the amplitudes of applied input signals [Clarke and Hess, 1978]. The most commonly used BJT equivalent circuit for investigating the dynamical responses to small input signals is the hybrid-pi model offered in Fig. 28.11 [Sedra and Smith, 1987]. In this model, R b , R c , and R e , respectively, represent the internal base, collector, and emitter resistances of the considered BJT. Although these series resistances vary somewhat with quiescent operating point [de Graaf, 1969], they can be viewed as constants in first-order manual analyses. FIGURE 28.11The small signal equivalent circuit (hybrid-pi model) of a bipolar junction transistor. ? 2000 by CRC Press LLC The emitter-base junction diffusion resistance, R p , is the small signal resistance of the emitter-base junction diode. It represents the inverse of the slope of the common emitter static input characteristic curves. Analytically, R p is given by (28.1) where h FE is the static common emitter current gain of the BJT, N F is the emitter-base junction injection coefficient, V T is the Boltzmann voltage corresponding to an absolute junction operating temperature of T, and I CQ is the quiescent collector current. The expression for the resistance, R o , which accounts for conductivity modulation in the neutral base, is (28.2) where V AF is the forward Early voltage, V ￠ CEQ is the quiescent voltage developed across the internal collector- emitter terminals, and I KF symbolizes the forward knee current. The knee current is a measure of the onset of high injection effects [Gummel and Poon, 1970] in the base. In particular, a collector current numerically equal to I KF implies that the forward biasing of the emitter-base junction promotes a net minority carrier charge injected into the base from the emitter that is equal to the background majority charge in the neutral base. The Early voltage is an inverse measure of the slope of the common emitter output characteristic curves. The final low frequency parameter of the hybrid-pi model is the forward transconductance, g m . This parameter, which is a measure of the forward small signal gain available at a quiescent operating point, is given by (28.3) Two capacitances, C p and C m , are incorporated in the small signal model to provide a first-order approxi- mation of steady-state transistor behavior at high signal frequencies. The capacitance, C p , is the net capacitance of the emitter-base junction diode and is given by (28.4) where the first term on the right-hand side represents the depletion component and the second term is the diffusion component of C p . In Eq. (28.4), t f is the average forward transit time of minority carriers in the field- neutral base, C JE is the zero bias value of emitter-base junction depletion capacitance, V JE is the built-in potential of the junction, V E is the forward biasing voltage developed across the intrinsic emitter-base junction, and M JE is the grading coefficient of the junction. The capacitance, C m , has only a depletion component, owing to the reverse R hNV I FE F T CQ p = R VV I I I o CEQ AF CQ CQ KF = ￠ + - ? è ? ? ? ÷ 1 g I NV I I V V m CQ FT CQ KF CEQ AF = - + ? è ? ? ? ? ? ? ÷ ÷ ÷ ÷ ￠ 1 1 C C V VV g JE E JE T M fm JE p t= - - ? è ? ? ? ÷ + 1 2 ? 2000 by CRC Press LLC (or at most zero) bias impressed across the internal base-collector junction. Accordingly, its analytical form is analogous to the first term on the right-hand side of Eq. (28.4). Specifically, (28.5) where the physical interpretation of C JC , V JC , and M JC is analogous to C JE , V JE , and M JE , respectively. A commonly invoked figure of merit for assessing the high speed, small signal performance attributes of a BJT is the common emitter, short circuit gain-bandwidth product, w T , which is given by (28.6) The significance of Eq. (28.6) is best appreciated by studying the simple circuit diagram of Fig. 28.12(a), which depicts the grounded emitter configuration of a BJT biased for linear operation at a quiescent base current of I BQ and a quiescent collector-emitter voltage of V CEQ . Note that the battery supplying V CEQ grounds the collector for small signal conditions. The small signal model of the circuit at hand is resultantly seen to be the topology offered in Fig. 28.12(b), where i BS and i CS , respectively, denote the signal components of the net instantaneous base current, i B , and the net instantaneous collector current, i C . For negligibly small internal collector (R c ) and emitter (R e ) resistances, it can be shown that the small signal, short circuit, high frequency common emitter current gain, b ac (jw), is expressible as (28.7) where b ac , the low frequency value of b ac (jw), or simply the low frequency beta, is FIGURE 28.12(a) Schematic diagram pertinent to the evaluation of the short circuit, common emitter, small signal current gain. (b) High frequency small signal model of the circuit in part (a). C C V VV JC C JC T M JC m = - - ? è ? ? ? ÷ 1 2 w pm T m g CC = + bw b w w w m b ac CS BS ac m j i i jC g j ()D= - ? è ? ? ? ÷ + 1 1 ? 2000 by CRC Press LLC b ac = b ac (0) = g m R p (28.8) and (28.9) symbolizes the so-called beta cutoff frequency of the BJT. Because the frequency, g m /C m , is typically much larger than w b , w b is the approximate 3-dB bandwidth of b ac (jw); that is, (28.10) It follows that the corresponding gain-bandwidth product, w T , is the product of b ac and w b , which, recalling Eq. (28.8), leads directly to the expression in Eq. (28.6). Moreover, in the neighborhood of w T , (28.11) which suggests that w T is the approximate frequency at which the magnitude of the small signal, short circuit, common emitter current gain degrades to unity. Hybrid-Pi Equivalent Circuit of a Monolithic BJT The conventional hyprid-pi model in Fig. 28.11 generally fails to provide sufficiently accurate predictions of the high frequency response of monolithic diffused or implanted BJTs. One reason for this modeling inaccuracy is that the hybrid-pi equivalent circuit does not reflect the fact that monolithic transistors are often fabricated on lightly doped, noninsulating substrates that establish a distributed, large area, pn junction with the collector region. Since the substrate-collector pn junction is back biased in linear applications of a BJT, negligible static and low frequency signal currents flow from the collector to the substrate. At high frequencies, however, the depletion capacitance associated with the reverse biased substrate-collector junction can cause significant susceptive loading of the collector port. In Fig. 28.13, the lumped capacitance, C bb , whose mathematical definition is similar to that of C m in Eq. (28.5), provides a first-order account of this collector loading. Observe that this substrate capacitance appears in series with a substrate resistance, R bb , which reflects the light doping nature of the substrate material. For monolithic transistors fabricated on insulating or semi-insulating sub- strates, R bb is a very large resistance, thereby rendering C bb unimportant with respect to the problem of predicting steady-state transistor responses at high signal frequencies. A problem that is even more significant than parasitic substrate dynamics stems from the fact that the hybrid- pi equivalent circuit in Fig. 28.11 is premised on a uniform transistor structure whose emitter-base and base- collector junction areas are identical. In a monolithic device, however, the effective base-collector junction area is much larger than that of the emitter-base junction because the base region is diffused or implanted into the collector [Glaser and Subak-Sharpe, 1977]. The effect of such a geometry is twofold. First, the actual value of C m is larger than the value predicated on the physical considerations that surround a simplified uniform structure BJT. Second, C m is not a single lumped capacitance that is incident with only the intrinsic base-collector junction. Rather, the effective value of C m is distributed between the intrinsic collector and the entire base-collector junction interface. A first-order account of this capacitance distribution entails partitioning C m in Fig. 28.11 into two capacitances, say C m1 and C m2 , as indicated in Fig. 28.13. In general, C m2 is 3 to 5 times larger than C m1 . Whereas C m1 is proportional to the emitter-base junction area, C m2 is proportional to the net base-collector junction area, less the area of the emitter-base junction. w b pp m = + 1 RCC() **bw b bac ac j()@ 2 bw bw w w w b ac ac T j jj ()@= ? 2000 by CRC Press LLC Just as C m1 and C m2 superimpose to yield the original C m in the simplified high frequency model of a BJT, the effective base resistances, R b1 and R b2 , sum to yield the original base resistance, R b . The resistance, R b1 , is the contact resistance associated with the base lead and the inactive BJT base region. It is inversely proportional to the surface area of the base contact. On the other hand, R b2 , which is referred to as the active base resistance, is nominally an inverse function of emitter finger length. Because of submicron base widths and the relatively light average doping concentrations of active base regions, R b2 is significantly larger than R b1 . Common Emitter Amplifier The most commonly used canonic cell of linear BJT amplifiers is the common emitter amplifier, whose basic circuit schematic diagram is depicted in Fig. 28.14(a). In this diagram, R ST is the Thévenin resistance of the applied signal source, V ST , and R LT is the effective, or Thévenin, load resistance driven by the amplifier. The signal source has zero average, or dc, value. Although requisite biasing is not shown in the figure, it is tacitly assumed that the transistor is biased for linear operation. Hence, the diagram at hand is actually the ac schematic diagram; that is, it delineates only the signal paths of the circuit. Note that in the common emitter orientation, the input signal is applied to the base of the transistor, while the resultant small signal voltage response, V OS , is extracted at the transistor collector. The hybrid-pi model of Fig. 28.11 forms the basis for the small signal equivalent circuit of the common emitter cell, which is given in Fig. 28.14(b). In this configuration, the capacitance, C o , represents an effective output port capacitance that accounts for both substrate loading of the collector port (if the BJT is a monolithic device) and the net effective shunt capacitance associated with the load. FIGURE 28.13The hybrid-pi equivalent circuit of a monolithic bipolar junction transistor. FIGURE 28.14(a) AC schematic diagram of a common emitter amplifier. (b) Modified small signal, high frequency equivalent circuit of common emitter amplifier. ? 2000 by CRC Press LLC At low signal frequencies, the capacitors, C p , C m , and C o in the model of Fig. 28.14(b), can be replaced by open circuits. A straightforward circuit analysis of the resultantly simplified equivalent circuit produces ana- lytical expressions for the low frequency values of the small signal voltage gain, A vCE = V OS /V ST ; the driving point input impedance, Z inCE ; and the driving point output impedance, Z outCE . Because the Early resistance, R o , is invariably much larger than the resistance sum (R c + R e + R LT ), the low frequency voltage gain of the common emitter cell is expressible as (28.12) For large R o , conventional circuit analyses also produce a low frequency driving point input resistance of R inCE = Z inCE (0) @ R b + R p + (b ac + 1)R e (28.13) and a low frequency driving point output resistance of (28.14) At high signal frequencies, the capacitors in the small signal equivalent circuit of Fig. 28.14(b) produce a third-order voltage gain frequency response whose analytical formulation is algebraically cumbersome [Singhal and Vlach, 1977; Haley, 1988]. However, because the poles produced by these capacitors are real, lie in the left half complex frequency plane, and generally have widely separated frequency values, the dominant pole approx- imation provides an adequate estimate of high frequency common emitter amplifier response in the usable passband of the amplifier. Accordingly, the high frequency voltage gain, say A vCE (s), of the common emitter amplifier can be approximated as (28.15) In this expression, T pCE is of the form, T pCE = R Cp C p + R Cm C m + R Co C o (28.16) where R C p , R C m , and R Co , respectively, represent the Thévenin resistances seen by the capacitors, C p , C m , and C o , under the conditions that (1) all capacitors are supplanted by open circuits and (2) the independent signal generator, V ST , is reduced to zero. Analogously, T zCE is of the form T zCE = R Cpo C p + R Cmo C m + R Coo C o (28.17) where R C po , R C mo , and R Coo , respectively, represent the Thévenin resistances seen by the capacitors, C p , C m , and C o , under the conditions that (1) all capacitors are supplanted by open circuits and (2) the output voltage response, V OS , is constrained to zero while maintaining nonzero input signal source voltage. It can be shown that when R o is very large and R c is negligibly small, A R RRR R vCE ac LT ST b ac e () () 0 1 @- +++ + é ? ê ê ù ? ú ú b b p RZ R RRRR R CE CE ac e eb ST oout out =@ +++ + ? è ? ? ? ÷ ()01 b p As A sT sT vCE vCE zCE pCE () ( )@ + + é ? ê ê ù ? ú ú 0 1 1 ? 2000 by CRC Press LLC (28.18) (28.19) and R Co = R LT (28.20) Additionally, R C po = R Coo = 0, and (28.21) Once T pCE and T zCE are determined, the 3-dB voltage gain bandwidth, B CE , of the common emitter amplifier can be estimated in accordance with (28.22) The high frequency behavior of both the driving point input and output impedances, Z inCE (s) and Z outCE (s), respectively, can be approximated by mathematical functions whose forms are analogous to the gain expression in Eq. (28.15). In particular, (28.23) and (28.24) where R inCE and R outCE are defined by Eqs. (28.13) and (28.14). The dominant time constants, T pCE1 , T zCE1 , T pCE2 , and T zCE2 , derive directly from Eqs. (28.16) and (28.17) in accordance with [Choma and Witherspoon, 1990] (28.25) R RR R R R RRRR C ST b e ac e ST b e p = ++ + +++ p p b **() 1 RRRRRR R RR RR C LT c ST b ac e ac LT c ac e mp p b b b =++ + ++ + + ++ é ? ê ê ù ? ú ú (){()[ ()]} () () ** 11 1 R RR Co ac e ac m p b b =- ++()1 B T T T CE pCE zCE pCE @ - ? è ? ? ? ÷ 1 12 2 ZsR sT sT CE CE zCE pCE in in ()@ + + é ? ê ê ù ? ú ú 1 1 1 1 ZsR sT sT CE CE zCE pCE out out 1 2 ()@ + + é ? ê ê ù ? ú ú 1 1 TT pCE R pCE ST 1 = ?￥ lim [] ? 2000 by CRC Press LLC (28.26) (28.27) and (28.28) For reasonable values of transistor model parameters and terminating resistances, T pCE1 > T zCE1 , and T pCE2 > T zCE2 . It follows that both the input and output ports of a common emitter canonic cell are capacitive at high signal frequencies. Design Considerations for the Common Emitter Amplifier Equation (28.12) underscores a serious shortcoming of the canonical common emitter configuration. In par- ticular, since the internal emitter resistance of a BJT is small, the low frequency voltage gain is sensitive to the processing uncertainties that accompany the numerical value of the small signal beta. The problem can be rectified at the price of a diminished voltage gain magnitude by inserting an emitter degeneration resistance, R EE , in series with the emitter lead, as shown in Fig. 28.15(a). Since R EE appears in series with the internal emitter resistance, R e , as suggested in Fig. 28.15(b), the impact of emitter degeneration can be assessed analyt- ically by replacing R e in Eqs. (28.12) through (28.28) by the resistance sum (R e + R EE ). For sufficiently large R EE , such that (28.29) the low frequency voltage gain becomes (28.30) where a ac , which symbolizes the small signal, short circuit, common base current gain, or simply the ac alpha, of the transistor is given by FIGURE 28.15 (a) AC schematic diagram of a common emitter amplifier using an emitter degeneration resistance. (b) Small signal, high frequency equivalent circuit of amplifier in part (a). T T zCE R pCE ST 1 = ?0 lim [] T T pCE R pCE LT 2 = ?￥ lim [] T T zCE R pCE LT 2 0 = ? lim [] RRR RRR eE E ST b ac +@> ++ + p b 1 A R R vCE ac LT EE ()0@- a ? 2000 by CRC Press LLC (28.31) Despite numerical uncertainties in b ac , minimum values of b ac are much larger than one, thereby rendering the voltage gain in Eq. (28.30) almost completely independent of small signal BJT parameters. A second effect of emitter degeneration is an increase in both the low frequency driving point input and output resistances. This contention is confirmed by Eq. (28.13), which shows that if R o remains much larger than (R c + R e + R EE + R LT ), a resistance in the amount of (b ac + 1)R EE is added to the input resistance established when the emitter of a common emitter amplifier is returned to signal ground. Likewise, Eq. (28.14) verifies that emitter degeneration increases the low frequency driving point output resistance. In fact, a very large value of R EE produces an output resistance that approaches a limiting value of (b ac + 1)R o . It follows that a common emitter amplifier that exploits emitter degeneration behaves as a voltage-to-current converter at low signal frequencies. In particular, its high input resistance does not incur an appreciable load on signal voltage sources that are characterized by even moderately large Thévenin resistances, while its large output resistance comprises an almost ideal current source at its output port. A third effect of emitter degeneration is a decrease in the effective pole time constant, T pCE , as well as an increase in the effective zero time constant, T zCE , which can be confirmed by reinvestigating Eqs. (28.18) through (28.21) for the case of R e replaced by the resistance sum (R e + R EE ). The use of an emitter degeneration resistance therefore promotes an increased 3-dB circuit bandwidth. Unfortunately, it also yields a diminished circuit gain-bandwidth product; that is, a given emitter degeneration resistance causes a degradation in the low frequency gain magnitude that is larger than the corresponding bandwidth increase promoted by this resistance. This deterioration of circuit gain-bandwidth product is a property of all negative feedback circuits [Choma, 1984]. For reasonable values of the emitter degeneration resistance, R EE , the Thévenin time constant, R Cm C m , is likely to be the dominant contribution to the effective first-order time constant, T pCE , attributed to the poles of a common emitter amplifier. Hence, C m is the likely device capacitance that dominantly imposes an upper limit to the achievable 3-dB bandwidth of a common emitter cell. The reason for this substantial bandwidth sensitivity to C m is the so-called Miller multiplication factor, say M, which appears as the last bracketed term on the right-hand side of Eq. (28.19), namely, (28.32) The Miller factor, M, which effectively multiplies C m in the expression for R Cm C m , increases sharply with the load resistance, R LT , and hence with the gain magnitude of the common emitter amplifier. Note that in the limit of a large emitter degeneration resistance (which adds directly to R e ), Eq. (28.30) reduces Eq. (28.32) to the factor M @ 1 + *A vCE (0)* (28.33) Common Base Amplifier A second canonic cell of linear BJT amplifiers is the common base amplifier, whose ac circuit schematic diagram appears in Fig. 28.16(a). In this diagram, R ST , V ST , R LT , and V OS retain the significance they respectively have in the previously considered common emitter configuration. Note that in the common base orientation, the input signal is applied to the base, while the resultant small signal voltage response is extracted at the collector of a transistor. The relevant small signal model is shown in Fig. 28.16(b). A straightforward application of Kirchhoff’s circuit laws gives, for the case of large R o , a low frequency voltage gain, A vCB (0) = V OS /V ST , of a b b ac ac ac = +1 M RR RR ac LT c ac e =+ + ++ 1 1 b b p () () ? 2000 by CRC Press LLC (28.34) where R inCB is the low frequency value of the common base driving point input impedance, (28.35) Moreover, it can be shown that the low frequency driving point output resistance is (28.36) The preceding three equations underscore several operating characteristics that distinguish the common base amplifier from its common emitter counterpart. For example, Eq. (28.35) suggests a low frequency input resistance that is significantly smaller than that of a common emitter unit. To underscore this contention, consider the case of two identical transistors, one used in a common emitter amplifier and the other used in a common base configuration, that are biased at identical quiescent operating points. Under this circumstance, Eqs. (28.35) and (28.13) combine to deliver (28.37) which shows that the common base input resistance is a factor of (b ac + 1) times smaller than the input resistance of the common emitter cell. The resistance reflection factor, (b ac + 1), in Eq. (28.37) represents the ratio of small signal emitter current to small signal base current. Accordingly, Eq. (28.37) is self-evident when it is noted that the input resistance of a common base stage is referred to an input emitter current, whereas the input resistance of its common emitter counterpart is referred to an input base current. A second difference between the common emitter and common base amplifiers is that the voltage gain of the latter displays no phase inversion between source and response voltages. Moreover, for the same load and source terminations and for identical transistors biased identically, the voltage gain of the common base cell is likely to be much smaller than that of the common emitter unit. This contention is verified by substituting Eq. (28.37) into Eq. (28.34) and using Eqs. (28.31), (28.13), and (28.12) to write FIGURE 28.16 (a) AC schematic diagram of a common base amplifier. (b) Small signal, high frequency equivalent circuit of amplifier in part (a). A R RR vCB ac LT ST CB ()0 @ + a in RZ R RR CB CB e b ac in in =@+ + + ()0 1 p b RZ RR RRRR R CB CB ac e ST eb ST oout out =@ + +++ + é ? ê ê ù ? ú ú () () 01 b p R R CB CE ac in in @ +b 1 ? 2000 by CRC Press LLC (28.38) At high signal frequencies, the voltage gain, driving point input impedance, and driving point output impedance can be approximated by functions whose analytical forms mirror those of Eqs. (28.15), (28.23), and (28.24). Let T pCB and T zCB designate the time constants of the effective dominant pole and the effective dominant zero, respectively, of the common base cell. An analysis of the structure of Fig. 28.16(b) resultantly produces, with R o and R c ignored, T pCB = R Cp C p + R Cm C m + R Co C o (28.39) where (28.40) (28.41) and R Co remains given by Eq. (28.20). Moreover, (28.42) Design Considerations for the Common Base Amplifier An adaptation of Eqs. (28.25) through (28.28) to the common base stage confirms that the driving point input impedance is capacitive at high signal frequencies. On the other hand, g m R b > 1 renders a common base driving point input impedance that is inductive at high frequencies. This impedance property can be gainfully exploited to realize monolithic shunt peaked amplifiers in which the requisite circuit inductance is synthesized as the driving point input impedance of a common base stage (or the driving point output impedance of a common collector cell) [Grebene, 1984]. The common base stage is often used to broadband the common emitter amplifier by forming the common emitter–common base cascode, whose ac schematic diagram is given in Fig. 28.17. The broadbanding afforded by the cascode structure stems from the fact that the effective low frequency load resistance, say R Le , seen by the common emitter transistor, QE, is the small driving point input resistance of the common base amplifier, QB. This effective load resistance, as witnessed by C m of the common emitter transistor, is much smaller than the actual load resistance that terminates the output port of the amplifier, thereby decreasing the Miller multiplication of the C m in QE. If the time constant savings afforded by decreased Miller multiplication is larger than the sum of the additional time constants presented to the circuit by the common base transistor, an enhancement of common emitter bandwidth occurs. Note that such bandwidth enhancement is realized without compromising the common emitter gain-bandwidth product, since the voltage gain of the common emit- ter–common base unit is almost identical to that of the common emitter amplifier alone. A A R RR vCB vCE ac ST ST CE () () 0 0 1 @ + + ** b in R RRRR RR RRRR C ST b e ac ST e ST b e p p p b = ++ + + +++ **() () 1 RRR RR R R RR RR C b ac ST e LT ac b bacSTe mp p b b b =+++ ++ +++ + é ? ê ê ù ? ú ú **[ ( )( )] ()() 1 1 1 T RC zCB b ac = m a ? 2000 by CRC Press LLC Common Collector Amplifier The final canonic cell of linear BJT amplifiers is the common collector amplifier. The ac schematic diagram of this stage, which is often referred to as an emitter follower, is given in Fig. 28.18(a). In emitter followers, the input signal is applied to the base, and the resultant small signal output voltage is extracted at the transistor emitter. The small signal equivalent circuit corresponding to the amplifier in Fig. 28.18(a) is shown in Fig. 28.18(b). A straightforward circuit analysis gives, for the case of large R o , a low frequency voltage gain, A vCC (0) = V OS /V ST , of (28.43) where R outCC is the low frequency value of the driving point output impedance, (28.44) The low frequency driving point output resistance is R inCC = Z inCC (0) @ R b + R p + (b ac + 1)(R e + R LT ) (28.45) FIGURE 28.17AC schematic diagram of a common emitter–common base cascode amplifier. FIGURE 28.18 (a) AC schematic diagram of a common collector (emitter follower) amplifier. (b) Small signal, high frequency equivalent circuit of amplifier in part (a). A R RR vCC LT LT CC ()0@ + out RZ R RRR CC CC e bST ac out out =@+ ++ + ()0 1 p b ? 2000 by CRC Press LLC The facts that the voltage gain is less than one and is without phase inversion, the output resistance is small, and the input resistance is large make the emitter follower an excellent candidate for impedance buffering applications. As in the cases of the common emitter and the common base amplifiers, the high frequency voltage gain, driving point input resistance, and driving point output resistance can be approximated by functions having analytical forms that are similar to those of Eqs. (28.15), (28.23), and (28.24). Let T pCC and T zCC designate the time constants of the effective dominant pole and the effective dominant zero, respectively, of the emitter follower. Since the output port capacitance, C o , appears across a short circuit, T pCC is expressible as T pCC = R Cp C p + R Cm C m (28.46) With R o ignored, (28.47) and (28.48) The time constant of the effective dominant zero is (28.49) Although the emitter follower possesses excellent wideband response characteristics, it should be noted in Eq. (28.48) that the internal collector resistance, R c , incurs some Miller multiplication of the base-collector junction capacitance, C m . For this reason, monolithic common collector amplifiers work best in broadband impedance buffering applications when they exploit transistors that have collector sinker diffusions and buried collector layers, which collectively serve to minimize the parasitic internal collector resistance. Defining Terms ac schematic diagram: A circuit schematic diagram, divorced of biasing subcircuits, that depicts only the dynamic signal flow paths of an electronic circuit. Driving point impedance: The effective impedance presented at a port of a circuit under the condition that all other circuit ports are terminated in the resistances actually used in the design realization. Hybrid-pi model: A two-pole linear circuit used to model the small signal responses of bipolar circuits and circuits fabricated in other device technologies. Miller effect: The deterioration of the effective input impedance caused by the presence of feedback from the output port to the input port of a phase-inverting voltage amplifier. Short circuit gain-bandwidth product: A measure of the frequency response capability of an electronic circuit. When applied to bipolar circuits, it is nominally the signal frequency at which the magnitude of the current gain degrades to one. R RR RR R RR RRRRR C ST b LT e ac LT e ST b LT e p p p b = ++ + + + +++ + **() () 1 RRRR RR RR RRR RR R C ST b ac LT e ac ST b ST b ac LT e c mp p b b b =+ ++ + ++ + +++ + + é ? ê ê ù ? ú ú ( ) [ ( )( ) () ()( ) ** 1 1 1 T RC zCC ac = + pp b 1 ? 2000 by CRC Press LLC Three-decibel bandwidth: A measure of the frequency response capability of low-pass and bandpass elec- tronic circuits. It is the range of signal frequencies over which the maximum gain of the circuit is constant to within a factor of the square root of two. Related Topic 24.2 Bipolar Transistors References W.K. Chen, Circuits and Filters Handbook, Boca Raton, Fla: CRC Press, 1995. J. Choma, “A generalized bandwidth estimation theory for feedback amplifiers,” IEEE Transactions on Circuits and Systems, vol. CAS-31, Oct. 1984. J. Choma and S. Witherspoon, “Computationally efficient estimation of frequency response and driving point impedances in wide-band analog amplifiers,” IEEE Transactions on Circuits and Systems, vol. CAS-37, June 1990. K.K. Clarke and D.T. Hess, Communication Circuits: Analysis and Design, Reading, Mass.: Addison-Wesley, 1978. H.C. de Graaf, “Two New Methods for Determining the Collector Series Resistance in Bipolar Transistors With Lightly Doped Collectors,” Phillips Research Report, 24, 1969. A.B. Glaser and G.E. Subak-Sharpe, Integrated Circuit Engineering: Design, Fabrication, and Applications, Read- ing, Mass.: Addison-Wesley, 1977. A.B. Grebene, Bipolar and MOS Analog Integrated Circuit Design, New York: Wiley Interscience, 1984. H.K. Gummel and H.C. Poon, “An integral charge-control model of bipolar transistors,” Bell System Technical Journal, 49, May–June 1970. S. B. Haley, “The general eigenproblem: pole-zero computation,” Proc. IEEE, 76, Feb. 1988. J.D. Irwin, Industrial Electronics Handbook, Boca Raton, Fla.: CRC Press, 1997. A.S. Sedra and K.C. Smith, Microelectronic Circuits, 3rd ed., New York: Holt, Rinehart and Winston, 1991. K. Singhal and J. Vlach, “Symbolic analysis of analog and digital circuits,” IEEE Transactions on Circuits and Systems, vol. CAS-24, Nov. 1977. Further Information The IEEE Journal of Solid-State Circuits publishes state-of-the-art articles on all aspects of integrated electronic circuit design. The December issue of this journal focuses on analog electronics. The IEEE Transactions on Circuits and Systems also publishes circuit design articles. Unlike the IEEE Journal of Solid-State Circuits, this journal addresses passive and active, discrete component circuits, as well as integrated circuits and systems, and it features theoretic research that underpins circuit design strategies. The Journal of Analog Integrated Circuits and Signal Processing publishes design-oriented papers with emphasis on design methodologies and design results. ? 2000 by CRC Press LLC