Blackwell, G.R. “Surface Mount Technology” The Electrical Engineering Handbook Ed. Richard C. Dorf Boca Raton: CRC Press LLC, 2000 26 Surface Mount Technology 26.1Introduction 26.2Definition and Considerations Considerations in the Implementation of SMT 26.3SMT Design, Assembly, and Test Overview 26.4Surface Mount Device (SMD) Definitions 26.5Substrate Design Guidelines 26.6Thermal Design Considerations 26.7Adhesives 26.8Solder Paste and Joint Formation 26.9Parts Inspection and Placement Parts Placement 26.10Reflow Soldering Post-Reflow Inspection 26.11Cleaning 26.12Prototype Systems 26.1 Introduction This section on surface mount technology (SMT) will familiarize the reader with the process steps in a successful SMT design. The new user of SMT is referred to Mims [1987] and Leibson [1987] for introductory material. Being successful with the implementation of SMT means the engineers involved must commit to the principles of concurrent engineering. It also means that a continuing commitment to a quality techniques is necessary, whether that is Taguchi, TQM, SPC, DOE, another technique, or a combination of several quality techniques, lest you too have quality problems with SMT (Fig. 26.1). 26.2 Definition and Considerations SMT is a collection of scientific and engineering methods needed to design, build, and test products made with electronic components that mount to the surface of the printed circuit board without holes for leads [Higgins, 1991]. This definition notes the breadth of topics necessary to understand SMT, and also clearly says that the successful implementation of SMT will require the use of concurrent engineering [Classon, 1993; Shina, 1991]. Concurrent engineering means that a team of design, manufacturing, test, and marketing people will concern themselves with board layout, parts and parts placement issues, soldering, cleaning, test, rework, and packaging, before any product is made. The careful control of all these issues improves both yield and reliability of the final product. In fact, SMT cannot be reasonably implemented without the use of concurrent engineering, and/or the principles contained in Design for Manufacturability (DFM) and Design for Testability (DFT), and therefore any facility that has not embraced these principles should do so if implementation of SMT is its goal. Glenn R. Blackwell Purdue University ? 2000 by CRC Press LLC Considerations in the Implementation of SMT Main reasons to consider implementation of SMT include: ?reduction in circuit board size ?reduction in circuit board weight ?reduction in number of layers in the circuit board ?reduction in trace lengths on the circuit board, with correspondingly shorter signal transit times and potentially higher-speed operation However, not all these reductions may occur in any given product redesign from through-hole technology (THT) to SMT. Most companies that have not converted to SMT are considering doing so. All is of course not golden in SMT Land. During the assembly of a through-hole board, either the component leads go through the holes or they do not, and the component placement machines can typically detect the difference in force involved. During SMT board assembly, the placement machine does not have such direct feedback, and accuracy of final soldered placement becomes a stochastic (probability-based) process, dependent on such items as component pad design, accuracy of the PCB artwork and fabrication which affects the accuracy of trace location, accuracy of solder paste deposition location and deposition volume, accuracy of adhesive deposition location and volume if adhesive is used, accuracy of placement machine vision system(s), variations in component sizes from the assumed sizes, and thermal issues in the solder reflow process. In THT test, there is a through-hole at every potential test point, making it easy to align a bed-of-nails tester. In SMT designs, there are not holes corre- sponding to every device lead. The design team must consider form, fit and function, time-to-market, existing capabilities, testing, rework capabilities, and the cost and time to characterize a new process when deciding on a change of technologies. 26.3 SMT Design, Assembly, and Test Overview ?Circuit design (not covered in this chapter) ?Substrate [typically Printed Circuit Board (PCB)] design ?Thermal design considerations ?Bare PCB fabrication and tests (not covered in this chapter) ?Application of adhesive, if necessary ?Application of solder paste ?Placement of components in solder paste ?Reflowing of solder paste ?Cleaning, if necessary ?Testing of populated PCB (not covered in this chapter) Once circuit design is complete, substrate design and fabrication, most commonly of a printed circuit board (PCB), enters the process. Generally, PCB assembly configurations using surface mount devices (SMDs) are classified as shown in Fig. 26.2. Type I — only SMDs are used, typically on both sides of the board. No through-hole components are used. Top and bottom may contain both large and small active and passive SMDs. This type board uses reflow soldering only. Type II — a double-sided board, with SMDs on both sides. The top side may have all sizes of active and passive SMDs, as well as through-hole components, while the bottom side carries passive SMDs and FIGURE 26.1Placement misalignment of an SMT chip resistor. (Source: Phillips Semiconductors, Surface Mount Process and Application Notes, Sunnyvale, Calif.: Phillips Semiconductors, 1991. With permission.) ? 2000 by CRC Press LLC small active components such as transistors. This type board requires both reflow and wave soldering, and will require placement of bottom-side SMDs in adhesive. Type III — top side has only through-hole components, which may be active and/or passive, while the bottom side has passive and small active SMDs. This type board uses wave soldering only, and also requires placement of the bottom-side SMDs in adhesive. It should be noted that with the ongoing increase in usage of various techniques to place IC dice directly on circuit boards, Type III in some articles means a mix of packaged SMT ICs and bare die on the same board. A Type I bare board will first have solder paste applied to the component pads on the board. Once solder paste has been deposited, active and passive parts are placed in the paste. For prototype and low-volume lines this can be done with manually guided X–Y tables using vacuum needles to hold the components, while in medium and high-volume lines automated placement equipment is used. This equipment will pick parts from FIGURE 26.2 Type I, II, and III SMT circuit boards. (Source: Intel Corporation, Packaging, Santa Clara, Calif.: Intel Corporation, 1994. With permission.) ? 2000 by CRC Press LLC reels, sticks, or trays, then place the components at the appropriate pad locations on the board, hence the term “pick and place” equipment. After all parts are placed in the solder paste, the entire assembly enters a reflow oven to raise the temperature of the assembly high enough to reflow the solder paste and create acceptable solder joints at the component lead/pad transitions. Reflow ovens most commonly use convection and IR heat sources to heat the assembly above the point of solder liquidus, which for 63/37 tin-lead eutectic solder is 183°C. Due to the much higher thermal conductivity of the solder paste compared to the IC body, reflow soldering temperatures are reached at the leads/pads before the IC chip itself reaches damaging temperatures. The board is inverted and the process repeated. If mixed-technology Type II is being produced, the board will then be inverted, an adhesive will be dispensed at the centroid of each SMD, parts placed, the adhesive cured, the assembly re-righted, through-hole components mounted, and the circuit assembly will then be wave-soldered which will create acceptable solder joints for both the through-hole components and bottom-side SMDs. A Type III board will first be inverted, adhesive dispensed, SMDs placed on the bottom-side of the board, the adhesive cured, the board re-righted, through-hole components placed, and the entire assembly wave- soldered. It is imperative to note that only passive components and small active SMDs can be successfully bottom-side wave-soldered without considerable experience on the part of the design team and the board assembly facility. It must also be noted that successful wave soldering of SMDs requires a dual-wave machine with one turbulent wave and one laminar wave. It is common for a manufacturer of through-hole boards to convert first to a Type II or Type III substrate design before going to an all-SMD Type I design. This is especially true if amortization of through-hole insertion and wave-soldering equipment is necessary. Many factors contribute to the reality that most boards are mixed- technology Type II or Type III boards. While most components are available in SMT packages, through-hole connectors are still commonly used for the additional strength the through-hole soldering process provides, and high-power devices such as three-terminal regulators are still commonly through-hole due to off-board heat-sinking demands. Both of these issues are actively being addressed by manufacturers and solutions exist which allow Type I boards with connectors and power devices [Holmes, 1993]. Again, it is imperative that all members of the design, build, and test teams be involved from the design stage. Today’s complex board designs mean that it is entirely possible to exceed the ability to adequately test a board if the test is not designed-in, or to robustly manufacture the board if in-line inspections and handling are not adequately considered. Robustness of both test and manufacturing are only assured with full involvement of all parties to overall board design and production. It cannot be overemphasized that the speed with which packaging issues are moving requires anyone involved in SMT board or assembly issues to stay current and continue to learn about the processes. Subscribe to one or more of the industry-oriented journals noted in the “Further Information” section at the end of this Chapter, obtain any IC industry references, and purchase several SMT reference books. 26.4 Surface Mount Device (SMD) Definitions The new user of SMDs must rapidly learn the packaging sizes and types for SMDs. Resistors, capacitors, and most other passive devices come in two-terminal packages which have end-terminations designed to rest on substrate pads/lands (Fig. 26.3). SMD ICs come in a wide variety of packages, from 8-pin Small Outline Packages (SOLs) to 1000+ connection packages in a variety of sizes and lead configurations, as shown in Fig. 26.4. The most common commercial packages currently include Plastic Leaded Chip Carriers (PLCCs), Small Outline packages (SOs), Quad Flat Packs (QFPs), and Plastic Quad Flat Packs (PQFPs) also know as Bumpered Quad Flat Packs (BQFPs). Add in Tape Automated Bonding (TAB), Ball Grid Array (BGA) and other newer technologies, and the IC possibilities become overwhelming. Space prevents examples of all these technologies from being included here. The reader is referred to the standards of the Institute for Interconnecting and Packaging Electronic Circuits (IPC) 1 to find the latest package standards, and to the proceedings of the most recent National Electronics Production and 1 IPC, 7380 N. Lincoln Ave, Lincolnwood, IL 60646-1705, 708-677-2850. ? 2000 by CRC Press LLC Productivity (NEPCON) Conference 1 for information on industry uses of the latest SMT packages. A good overview of package styles is found in Appendix A of Hollomon [1995] and (for ICs only) in Signetics [1991b] which is being updated as of this writing. Each IC manufacturer’s data books will have packaging information for their products. The engineer should be familiar with the term “lead pitch”, which means the center-to-center distance between IC leads. Pitch may be in thousandths of an inch, also known as mils, or in millimeters. Common pitches are 0.050 in. (50 mil pitch), 0.025 in. (25 mil pitch) frequently called “fine pitch”, and 0.020 in. and smaller frequently called “ultra- fine pitch”. Metric equivalents are 1.27 mm, 0.635 mm, and 0.508 mm and smaller. Conversions from metric to inches are easily approximated if one remembers that 1 mm approximately equals 40 mils. For process control, design teams must consider the minimum and maximum package size variations allowed by their part suppliers, the moisture content of parts as-received, and the relative robustness of each lead type. Incoming inspection should consist of both electrical and mechanical tests. Whether these are spot checks, lot checks, or no checks will depend on the relationship with the vendor. 26.5 Substrate Design Guidelines As noted previously, substrate (typically PCB) design has an effect not only on board/component layout, but also on the actual manufacturing process. Incorrect land design or layout can negatively affect the placement process, the solder process, the test process or any combination of the three. Substrate design must take into account the mix of SMDs that are available for use in manufacturing. The considerations noted here as part of the design process are neither all-encompassing, nor in sufficient detail for a true SMT novice to adequately deal with all the issues involved in the process. They are intended to guide an engineer through the process, allowing him/her to access more detailed information as necessary. General references are noted at the end of this chapter, and specific references will be noted as applicable. In addition, conferences such as the NEPCON, and SMI 2 are invaluable sources of information for both the beginner and the experienced SMT engineer. Although these guidelines are noted as “steps”, they are not necessarily in an absolute order, and may require several iterations back-and-forth among the steps to result in a final satisfactory process and product. After the circuit design (schematic capture) and analysis, Step 1 in the process is to determine whether all SMDs will be used in the final design making a Type I board, or whether a mix of SMDs and through-hole parts will be used, leading to a Type II or Type III board. This decision will be governed by some or all of the following considerations: ? Current parts stock ? Existence of current through-hole placement and/or wave solder equipment 1 NEPCON, rep. by Reed Exhibition Co., Norwalk, CT. 2 Surface Mount Technology Association, 5200 Wilson Rd., Suite 100, Minneapolis, MN 55424. FIGURE 26.3 Example of passive component sizes (top view)(not to scale). ? 2000 by CRC Press LLC ? 2000 by CRC Press LLC FIGURE 26.4 Examples of SMT plastic packages. ( Sour ce: I n t e l C o r p or ation, P a ckag ing, Santa Clar a, Calif.: I n t e l C o r p or ation, 1994. W ith per mission.) ?Amortization of current through-hole placement and solder equipment ?Existence of reflow soldering equipment, or cost of new reflow soldering equipment ?Desired size of the final product ?Panellization of smaller Type I boards ?Thermal issues related to high power circuit sections on the board It may be desirable to segment the board into areas based on function: RF, low power, high power, etc. using all SMDs where appropriate, and mixed-technology components as needed. Power and connector portions of the circuit may point to the use of through-hole components, although as mentioned both these issues are being addressed by circuit board material and connector manufacturers. Using one solder technique (reflow or wave) simplifies processing, and may outweigh other considerations. Step 2 in the SMT process is to define all the footprints of the SMDs under consideration for use in the design. The footprint is the copper pattern or “land”, on the circuit board upon which the SMD will be placed. Footprint examples are shown in Figs. 26.5a and 26.5b, and footprint recommendations are available from IC manufacturers and in the appropriate data books. They are also available in various ECAD packages used for the design process, or in several references that include an overview of the SMT process [Electronic Packaging and Production, 1994]. However, the reader is seriously cautioned about using the general references for anything other than the most common passive and active packages. Even the position of pin 1 may be different among IC manufacturers of the “same” chip. The footprint definition may also include the position of the solder resist pattern surrounding the copper pattern. Footprint definition sizing will vary depending on whether reflow or wave solder process is used. Wave solder footprints will require recognition of the direction of travel of the board through the wave, to minimize solder shadowing in the final fillet, as well as requirements for solder thieves. The copper footprint must allow for the formation of an appropriate, inspectable solder fillet. If done as part of the EDA process (electronic design automation, using appropriate electronic CAD software), the software will automatically assign copper directions to each component footprint, as well as appropriate coordinates and dimensions. These may need adjustment based on considerations related to wave soldering, test points, RF and/or power issues, and board production limitations. Allowing the software to select 5 mil traces when the board production facility to be used can only reliably do 10 mil traces would be inappropriate. Likewise, the solder resist patterns must be governed by the production capabilities. Final footprint and trace decisions will: ?allow for optimal solder fillet formation ?minimize necessary trace and footprint area ?allow for adequate test points ?minimize board area, if appropriate ?set minimum inter-part clearances for placement and test equipment to safely access the board (Fig. 26.6) FIGURE 26.5 (a) Footprint land and resist. (Source: Phillips Semiconductors, Surface Mount Process and Application Notes, Sunnyvale, Calif.: Phillips Semiconductors, 1991. With permission.) (b) QFP footprint. (Source: Intel Corporation, Packaging, Santa Clara, Calif.: Intel Corporation, 1994. With permission.) ? 2000 by CRC Press LLC ?allow adequate distance between components for post-reflow operator inspections ?allow room for adhesive dots on wave-soldered boards ?minimize solder bridging Decisions that will provide optimal footprints include a number of mathematical issues, including: ?component dimension tolerances ?board production capabilities, both artwork and physical tolerances across the board relative to a 0–0 fiducial ?how much artwork/board shrink or stretch is allowable ?solder deposition volume consistencies with respect to fillet sizes ?placement machine accuracies ?test probe location controls and bed-of-nails grid pitch Design teams should restrict wave-solder-side SMDs to passive components and transistors. While small SMT ICs can be successfully wave-soldered, this is inappropriate for an initial SMT design, and is not recom- mended by some IC manufacturers (Fig. 26.2). These decisions may require a statistical computer program, if available to the design team. The stochastic nature of the overall process suggests a statistical programmer will be of value. 26.6 Thermal Design Considerations Thermal management issues remain major concerns in the successful design of an SMT board and product. Consideration must be taken of the variables affecting both board temperature and junction temperature of the IC. The reader is referred to Chapter 33 in this Handbook for the basics of Thermal Management, and to Bar-Cohen and Kraus [1988] for a more detailed treatment on thermal issues affecting ICs and PCB design. The design team must understand the basic heat transfer characteristics of most SMT IC packages [Capillo, 1993]. Since the silicon chip of an SMD is equivalent to the chip in an identical-function DIP package, the smaller SMD package means the internal lead frame metal has a smaller mass than the lead frame in a DIP package. This lesser ability to conduct heat away from the chip is somewhat offset by the leadframe of many SMDs being constructed of copper, which has a lower thermal resistance than the Kovar and Alloy 42 materials FIGURE 26.6 Minimum land-to-land clearance examples. (Source: Intel Corporation, Packaging, Santa Clara, Calif.: Intel Corporation, 1994. With permission.) ? 2000 by CRC Press LLC commonly used for DIP packages. However, with less metal and shorter lead lengths to transfer heat to ambient air, more heat is typically transferred to the circuit board itself. Several board thermal analysis software packages are available, and are highly recommended for boards that are expected to develop high thermal gradients [Flotherm, 1995]. Since all electronics components generate heat in use, and elevated temperatures negatively affect the reli- ability and failure rate of semiconductors, it is important that heat generated by SMDs be removed as efficiently as possible. The design team needs to have expertise with the variables related to thermal transfer: ?junction temperature: T j ?thermal resistances: Q jc , Q ca , Q cs , Q sa ?temperature sensitive parameter (TSP) method of determining Qs ?power dissipation: P D ?thermal characteristics of substrate material SMT packages have been developed to maximize heat transfer to the substrate. These include PLCCs with integral heat spreaders, the SOT-89 power transistor package, the DPAK power transistor package, and many others. Analog ICs are also available in power packages. Note that all of these devices are designed primarily for processing with the solder paste process, and some specifically recommend against their use with wave- solder applications. Heat sinks and heat pipes should also be considered for high-power ICs. In the conduction process, heat is transferred from one element to another by direct physical contact between the elements. Ideally the material to which heat is being transferred should not be adversely affected by the transfer. As an example, the glass transition temperature T g of FR-4 is 125°C. Heat transferred to the board has little or no detrimental affect as long as the board temperature stays at least 50°C below T g . Good heat sink material exhibits high thermal conductivity, which is not a characteristic of fiberglass. Therefore, the traces must be depended on to provide the thermal transfer path [Choi et al., 1994]. Conductive heat transfer is also used in the transfer of heat from IC packages to heat sinks, which also requires use of thermal grease to fill all air gaps between the package and the “flat” surface of the sink. The previous discussion of lead properties of course does not apply to leadless devices such as Leadless Ceramic Chip Carriers (LCCCs). Design teams using these and similar packages must understand the better heat transfer properties of the alumina used in ceramic packages, and must match TCEs between the LCCC and the substrate, since there are no leads to bend and absorb mismatches of expansion. Since the heat transfer properties of the system depend on substrate material properties, it is necessary to understand several of the characteristics of the most common substrate material, FR-4 fiberglass. The glass transition temperature has already been noted, and board designers must also understand that multi-layer FR- 4 boards do not expand identically in the X-, Y-, and Z-directions as temperature increases. Plate-through- holes will constrain z-axis expansion in their immediate board areas, while non-through-hole areas will expand further in the z-axis, particularly as the temperature approaches and exceeds T g [Lee et al., 1984]. This unequal expansion can cause delamination of layers and plating fracture. If the design team knows that there will be a need for higher abilities to dissipate heat and/or a need for higher glass transition temperatures and lower coefficients of thermal expansion (TCE) than FR-4 possesses, many other materials are available, examples of which will follow. Note in Table 26.1 that copper-clad Invar has both variable T g and variable thermal conductivity depending on the volume mix of copper and Invar in the substrate. Copper has a high TCE and Invar has a low TCE, so the TCE increases with the thickness of the copper layers. In addition to heat transfer considerations, board material decisions must also be based on the expected vibration, stress, and humidity in the application. Convective heat transfer involves transfer due to the motion of molecules, typically airflow over a heat sink, and depends on the relative temperatures of the two media involved. It also depends on the velocity of air flow over the boundary layer of the heat sink. Convective heat transfer is primarily effected when forced air flow is provided across a substrate, and when convection effects are maximized through the use of heat sinks. The rules that designers are familiar with when designing THT heat-sink device designs also apply to SMT design. The design team must consider whether passive conduction and convection will be adequate to cool a populated substrate or whether forced-air cooling or liquid cooling will be needed. Passive conductive cooling ? 2000 by CRC Press LLC is enhanced with thermal layers in the substrate, such as the previously mentioned copper/Invar. There will also be designs that will rely on the traditional through-hole device with heat sink to maximize heat transfer. An example of this would be the typical three-terminal voltage regulator mounted on a heat sink or directly to a metal chassis for heat conduction, for which standard calculations apply [Lee et al., 1993]. Many specific examples of heat transfer may need to be considered in board design, and of course most examples involve both conductive and convective transfer. For example, the air gap between the bottom of a standard SMD and the board effects the thermal resistance from the case to ambient, Q ca . A wider gap will result in a higher resistance, due to poorer convective transfer, whereas filling the gap with a thermal-conductive epoxy will lower the resistance by increasing conductive heat transfer. Thermal-modeling software is the best way to deal with these types of issues, due to the need for rigorous application of computational fluid dynamics (CFD) [Lee, 1994]. 26.7 Adhesives In the surface mount assembly process, Type II and Type III boards will always require adhesive to mount the SMDs for passage through the solder wave. This is apparent when one envisions components on the bottom side of the substrate with no through-hole leads to hold them in place. Adhesives will stay in place after the soldering process, and throughout the life of the substrate and the product, since there is no convenient means for adhesive removal once the solder process is complete. This means the adhesive used must meet a number of both physical and chemical characteristics that should be considered during the three phases of adhesive use in SMT production: pre-application properties relating to storage and dispensing issues, curing properties relating to time and temperature needed for cure, and post-curing properties: relating to final strength, mechan- ical stability, and reworkability. Among these characteristics are: ? electrically non-conductive ? thermal coefficient of expansion similar to the substrate and the components ? stable in both storage and after application, prior to curing ? stable physical drop shape — retains drop height and fills z-axis distance between the board and the bottom of the component; thixotropic with no adhesive migration ? non-corrosive to substrate and component materials ? chemically inert to flux, solder, and cleaning materials used in the process ? cureable as appropriate to the process: UV, oven, or air-cure ? removable for rework and repair ? once cured, unaffected by temperatures in the solder process ? adhesive color, for easy identification by operators One-part adhesives are easier to work with than two-part adhesives because an additional process step is not required. The user must verify that the adhesive has sufficient shelf life and pot life for the user’s perceived process requirements. Both epoxy and acrylic adhesives are available as one- or two-part systems, and must be cured thermally. Generally, epoxy adhesives are cured by oven-heating, while acrylics may be formulated to be cured by long-wave UV light or heat. TABLE 26.1 Substrate Material T g – Glass Transition Temperature TCE – Thermal Coefficient of X–Y Expansion Thermal Conductivity Moisture Absorption (Units) (°C) (PPM/°C) (W/M°C) (%) FR-4 Epoxy glass 125 13–18 0.16 0.10 Polymide glass 250 12–16 0.35 0.35 Copper-clad invar Depends on resin 5–7 160XY — 15–20Z NA Poly Aramid fiber 250 3–8 0.15 1.65 Alumina/ceramic NA 5–7 20–45 NA ? 2000 by CRC Press LLC Adhesive can be applied by screening techniques similar to solder paste screen application, by pin transfer techniques, and by syringe deposition. Screen and pin-transfer techniques are suitable for high-volume production lines with few product changes over time. Syringe deposition using an X–Y table riding over the board with a volumetric pump and syringe tip is more suitable for lines with a varying product mix, prototype lines, and low- volume lines where the open containers of adhesive necessary in pin-transfer and screen techniques are avoided. Newer syringe systems are capable of handling high-volume lines. See Fig. 26.8 for methods of adhesive deposition. If Type II or Type III assemblies are used, and thermal transfer between components and the substrate is a concern, the design team should consider thermally conductive adhesives. Regardless of the type of assembly, the type of adhesive used, or the curing technique used, adhesive volume and height must be carefully controlled. Slump of adhesive after application is undesirable because the adhesive must stay high enough to solidly contact the bottom of the component, and must not spread and contaminate any pad associated with the component. If adhesive dot height = X, substrate metal height = Y, and SMD termination thickness = Z, then X>Y+Z, allowing for all combinations of potential errors, e.g., end termination min and max thickness, adhesive dot min and max height, and substrate metal min and max height: Typically, end termination thickness variations are available from the part manufacturer. Solder pad thickness variations are a result of the board manufacturing process, and will vary not only on the type of board metallization (standard etch vs. plated-through-hole) but also on the variations within each type. For adequate dot height, which will allow for some dot compression by the part, X should be between 1.5X and 2.5X of the total Y+Z, or just Z when dummy tracks are used. If adhesive dots are placed on masked areas of the board, mask thickness must also be considered. A common variation on the above design is to place “dummy” copper pads under the center of the part. Since these pads are etched and plated at the same time as the actual solder pads, the variation in metal height Y is eliminated as an issue. Adhesive dots are placed on the dummy pads and X > Z is the primary concern. Adhesive dispensing quality issues are addressed by considerations of: ?type of adhesive to be used ?process-area ambient temperature and humidity ?incoming quality control ?no voids in cured adhesive to prevent trapping of flux, dirt, etc. ?volume control ?location control ?as in Fig. 26.7, all combinations of termination, dot, and substrate height/thicknesses Prasad [1997] has an excellent in-depth discussion of adhesives in SMT production. 26.8 Solder Paste and Joint Formation Solder joint formation is the culmination of the entire process. Regardless of the quality of the design, or any other single portion of the process, if high-quality reliable solder joints are not formed, the final product is not reliable. It is at this point that PPM levels take on their finest meaning. For a medium-size substrate (nominal FIGURE 26.7 Relation of adhesive dot, substrate, and component. (Source: Phillips Semiconductors, Surface Mount Process and Application Notes, Sunnyvale, Calif.: Phillips Semiconductors, 1991. With permission.) ? 2000 by CRC Press LLC 6” X 8”), with a medium density of components, a typical mix of active and passive parts on the topside and only passive and 3- or 4-terminal active parts on bottomside, there may be in excess of 1000 solder joints per board. If solder joints are manufactured at the 3 sigma level (99.73% good joints, or 0.27% defect rate, or 2700 defects per 1 million joints), there will be 2.7 defects per board!! At the 6 sigma level, of 3.4 PPM, there will be a defect on 1 board out of every 294 boards produced. If your anticipated production level is 1000 units per day, you will have 3.4 rejects based solely on solder joint problems, not counting other sources of defects. Solder paste may be deposited by syringe, or by screen or stencil printing techniques. Stencil techniques are best for high-volume/speed production although they do require a specific stencil for each board design. Syringe and screen techniques may be used for high-volume lines and are also suited to mixed-product lines where only small volumes of a given board design are to have solder paste deposited. Syringe deposition is the only solder paste technique that can be used on boards which already have some components mounted. It is also well suited for prototype lines and for any use requires only software changes to develop a different deposition pattern. FIGURE 26.8 Methods of adhesive deposition. ? 2000 by CRC Press LLC Solder joint defects have many possible origins: ?poor or inconsistent solder paste quality ?inappropriate solder pad design/shape/size/trace connections ?substrate artwork or production problems, e.g., mismatch of copper and mask, warped substrate ?solder paste deposition problems, e.g., wrong volume or location ?component lead problems, e.g., poor coplanarity or poor tinning of leads ?placement errors, e.g., part rotation or X–Y offsets ?reflow profile, e.g., preheat ramp too fast or too slow; wrong temperatures created on substrate ?board handling problems, e.g., boards getting jostled prior to reflow. Once again, a complete discussion of all of the potential problems that can affect solder joint formation is beyond the scope of this chapter. Many references are available which address the issues. An excellent overview of solder joint formation theory is found in Lau [1991]. Update information this and all SMT topics is available each year at conferences such as SMI and NEPCON. While commonly used solder paste for both THT and SMT production contains 63-37 eutectic tin-lead solder, other metal formulations are available, including 96-4 tin-silver (a.k.a. silver solder). The fluxes available include RMA, water-soluble, and no-clean. The correct decision rests as much on the choice of flux as it does on the proper metal mixture. A solder paste supplier can best advise on solder pastes for specific needs. Many studies are in process to determine a no-lead replacement for lead-based solder in commercial electronic assemblies. The design should investigate the current status of these studies as well as the status of no-lead legislation as part of the decision-making process. To better understand solder joint formation, one must understand the make-up of solder paste used for SMT soldering. The solder paste consists of microscopic balls of solder, most commonly tin-lead with the accompanying oxide film, flux, and activator and thickener solvents as shown in Fig. 26.9. The fluxes are an integral part of the solder paste, and are discussed further in Section 26.11. RMA, water soluble, and no-clean flux/pastes are available. An issue directly related to fluxes, cleaning and fine-pitch components (25 mil pitch and less) is reflowing in an inert environment. Inert gas blanketing the oven markedly reduces the development of oxides in the elevated temperatures present. Oxide reduction needs are greater with the smaller metal balls in paste designed for fine-pitch parts because there is more surface area on which oxides can form. No-clean fluxes are not as active as other fluxes and therefore have a lesser ability to reduce the oxides formed on both the paste metal and substrate metallizations. Inerting the oven tends to solve these problems. However, it brings with it control issues that must be considered. Regardless of the supplier, frequent solder paste tests are advisable, especially if the solder is stored for prolonged periods before use. At a minimum, viscosity, percent metal, and solder sphere formation should be tested [Capillo, 1990]. Solder sphere formation is particularly important because acceptable particle sizes will vary depending on the pitch of the smallest-pitch part to be used, and the consistency of solder sphere formation will effect the quality of the final solder joint. Round solder spheres have the smallest surface area for a given FIGURE 26.9 Make-up of SMT solder paste. ? 2000 by CRC Press LLC volume. Therefore, they will have the least amount of oxide formation. Uneven distribution of sphere sizes within a given paste can lead to uneven heating during the reflow process, with the result that the unwanted solder balls will be expelled from the overall paste mass at a given pad/lead site. Fine-pitch paste has smaller ball sizes and consequently more surface area on which oxides can form. It should be noted at this point that there are three distinctly different “solder balls” referred to in this chapter and in publications discussing SMT. The solder sphere test refers to the ability of a volume of solder to form a ball shape due to its inherent surface tension when reflowed (melted) on a non-wettable surface. This ball formation is dependent on minimum oxides on the microscopic metal balls which make up the paste — the second type of “solder ball”. It is also dependent on the ability of the flux to reduce the oxides that are present, as well the ramp-up of temperature during the preheat and drying phases of the reflow oven profile. Too steep a time/temperature slope can cause rapid escape of entrapped volatile solvents, resulting in expulsion of small amounts of metal that will form undesirable “solder balls” of the third type, small metal balls scattered around the solder joint(s) on the substrate itself rather than on the tinned metal of the joint. This third type of ball can also be formed by excess solder paste on the pad, and by mis-deposition on non-wettable areas of the substrate. The reader is referred to Lau [1991] for discussions of finite element modeling of solder joints, and detailed analytical studies of most aspects of basic joints and of joint failures. Various articles by Engelmaier et al. also address many solder joint reliability issues and their analytical analysis. These and other sources will discuss in detail the quality issues that effect solder paste: ?viscosity and its measurement ?printability ?open time ?slump ?metal content ?particle/ball size in mesh ?particle/ball size consistency ?wetting ?storage conditions Note with regard to viscosity measurements, some paste manufacturers will prefer the spindle technique and some the spiral technique. To properly compare the paste manufacturer’s readings with your tests, the same technique must be used. 26.9 Parts Inspection and Placement Briefly, all parts must be inspected prior to use. Functional parts testing should be performed on the same basis as for through-hole devices. Each manufacturer of electronic assemblies is familiar with the various processes used on through-hole parts, and similar processes must be in place on SMDs. Problems with solderability of leads and lead planarity are two items that can lead to the largest number of defects in the finished product. Solderability is even more important with SMDs than with through- hole parts because all electrical and mechanical strength rests within the solder joint, there being no hole-with-lead to add mechanical strength. Lead coplanarity is defined as follows. If a multi-lead part, e.g., IC, is placed on a planar surface, lack of ideal coplanarity exists if the lowest solderable part of any lead does not touch that surface. Coplanarity requirements vary depending on the pitch of the component leads and their shape, but generally out-of-plane measurements should not exceed 4 mils (0.004 in.) for 50-mil pitch devices, and 2 mils for 25-mil pitch devices. All SMDs undergo thermal shocking during the soldering process, particularly if the SMDs are to be wave- soldered (Type II or Type III boards), which means they will be immersed in the molten solder wave for 2 to 4 s. Therefore, all plastic-packaged parts must be controlled for moisture content. If the parts have not been stored in a low-humidity environment (<25%RH), then the absorbed moisture will expand during the solder process and crack the package — a phenomenon know as “popcorning” because the crack is accompanied by a loud “pop” and the package expands due to the expansion of moisture, just like real popcorn. IC suppliers have strict recommendations on storage ambient humidity and temperature, and also on the baking procedures ? 2000 by CRC Press LLC necessary to allow safe reflow soldering if those recommendations are not heeded. Follow them carefully. Typically if storage RH is above 20%, baking must be considered prior to reflow. Parts Placement Proper parts placement not only places the parts within an acceptable window relative to the solder pad pattern on the substrate, but the placement machine will apply enough downward pressure on the part to force it halfway into the solder paste as well (Fig. 26.10a and 26.10b). This assures both that the part will sit still when the board is moved, and that coplanarity offsets within limits will still result in an acceptable solder joint. The effects of coplanarity can be done mathematically by considering: ?the thickness of the solder paste deposit ?maximum coplanarity offsets among leads ?lead penetration in paste If T is the thickness of paste, C is maximum allowable coplanarity, and P is penetration in paste (as a percentage of overall average paste thickness), then: % Parts placement may be done manually for prototype or low-volume operations, although this author suggests the use of guided X–Y tables with vacuum part pickup for even the smallest operation. Manual placement of SMDs does not lend itself to repeatable work. For medium and high volume work, a multitude of machines are available. See Fig. 26.11 for the four general categories of automated placement equipment. One good source for manufacturer’s information on placement machines and most other equipment used in the various SMT production and testing phases is the annual “Directory of Suppliers to the Electronics Manufacturing Industry”, published by Electronic Packaging and Production. Among the elements to consider in the selection of placement equipment, whether fully automated or X–Y-vacuum assist tables, are: ?volume of parts to be placed per hour ?conveyorized links to existing equipment ?packaging of components to be handled: tubes, reels, trays, bulk, etc. ?ability to download placement information from CAD/CAM systems ?ability to modify placement patterns by the operator ?vision capability needed, for board fiducials and/or fine-pitch parts FIGURE 26.10a Part placed into solder paste with a passive part. FIGURE 26.10b Part placed into solder paste with an active part. P C T --- 100′= ? 2000 by CRC Press LLC Checks of new placement equipment, or in-place equipment when problems occur, should include: ? X-accuracy ? Y-accuracy ? Z-accuracy ? placement pressure ? vision system checks both downward and upward It must be emphasized that placement accuracy checks cannot be made using standard circuit boards. Special glass plates with engraved measurement patterns and corresponding glass parts must be used because standard circuit boards and parts vary too widely to allow accurate X-, Y-, and Q-measurements. 26.10 Reflow Soldering Once SMDs have been placed in solder paste, the assembly will be reflow soldered. This can be done in either batch-type ovens or conveyorized continuous-process ovens. The choice depends primarily on the board throughput per hour required. While many early ovens were of the vapor phase type, most ovens today use FIGURE 26.11 Four major categories of placement equipment. (Source: Intel Corporation, Packaging, Santa Clara, Calif.: Intel Corporation, 1994. With permission.) ? 2000 by CRC Press LLC infrared (IR) heating, convection heating, or a combination of the two. In IR ovens the absorbance of the paste, parts, glue, etc. as a function of color should considered. Convection ovens tend to be more forgiving with variations in color and thermal masses on the substrates. This author does not recommend vapor phase (condensation heating) ovens to new users of SMT. All ovens are zoned to provide a thermal profile necessary for successful SMD soldering. An example of an oven profile is shown in Fig. 26.12, and the phases of reflow soldering that are reflected in that example include: ?Preheat: The substrate, components and solder paste preheat. ?Dry: Solvents evaporate from the solder paste. Flux activates, reduces oxides, and evaporates. Both low- and high-mass components have enough soak time to reach temperature equilibrium. ?Reflow: The solder paste temperature exceeds the liquidus point and reflows, wetting both the com- ponent leads and the board pads. Surface tension effects occur, minimizing wetted volume. ?Cooling: The solder paste cools below the liquidus point, forming acceptable (shiny and appropriate volume) solder joints. The setting of the reflow profile is not trivial. It will vary on whether the flux is RMA, water soluble, or no clean, and it will vary depending on both the mix of low- and high-thermal mass components, and on how those components are laid out on the board. The profile should exceed the liquidus temperature of the solder paste by 20 to 25°C. While final setting of the profile will depend on actual quality of the solder joints formed FIGURE 26.12 Typical thermal profile for SMT reflow soldering (Type I or II assemblies). (Source: Cox, N.R., Reflow Technology Handbook, Minneapolis, Minn.: Research, Inc., 1992. With permission.) FIGURE 26.13 Conveyorized reflow oven showing zones which create the profile. (Source: Intel Corporation, Packaging, Santa Clara, Calif.: Intel Corporation, 1994. With permission.) ? 2000 by CRC Press LLC in the oven, initial profile setting should rely heavily on information from the solder paste vendor, as well as the oven manufacturer. Remember that the profile shown is the profile to be developed on the substrate, and the actual control settings in various stages of the oven itself may be considerably different, depending on the thermal inertia of the product in the oven and the heating characteristics of the particular oven being used. This should be determined not by the oven settings but by instrumenting actual circuit boards with thermo- couples and determining that the profiles at various locations on the circuit board meet the specifications necessary for good soldering. Defects as a result of poor profiling may include: ?component thermal shock ?solder splatter ?solder balls formation ?dewetted solder ?cold or dull solder joints It should be noted that many other problems may contribute to defective solder joint formation. One example would be place- ment misalignment which contributes to the formation of solder bridges, as shown in Fig. 26.14. Other problems that may contribute to defective solder joints include poor solder mask adhesion, and unequal solder land areas at opposite ends of passive parts, which creates unequal moments as the paste liquifies and develops surface tension. Wrong solder paste volumes, whether too much or too little, will create defects, as will board shake in placement machines and coplanarity prob- lems in IC components. Many of these problems should be covered and compensated for during the design process and the qualifica- tion of SMT production equipment. Post-Reflow Inspection Final analysis of the process is performed based on the quality of the solder joints formed in the reflow process. Whatever criteria may have been followed during the overall process, solder joint quality is the final determining factor of the correctness of the various process steps. As noted earlier, the quality level of solder joint production is a major factor in successful board assembly. A primary criteria is the indication of wetting at the junction of the reflowed solder and the part termination. This same criteria shown in Fig. 26.15 applies to both through- hole and SMDs, with only the inspection location being different. Note that criteria shown in Fig. 26.15 are for any solderable surface, whether component or board, SMT or THT. Some lead surfaces are defined as not solderable, e.g., the cut and not-tinned end of an SO or QFP lead is not considered solderable. Parts manufacturers will define whether a given surface is designed to be solderable. FIGURE 26.15 Solder joint inspection criteria. FIGURE 26.14Solder bridge risk due to mis- alignment. (Source: Phillips Semiconductors, Surface Mount Process and Application Notes, Sunnyvale, Calif.: Phillips Semiconductors, 1991. With permission.) ? 2000 by CRC Press LLC Presentation of criteria for all the various SMD package types and all the possible solder joint problems is beyond the scope of this chapter. The reader is directed to Hollomon [1995], Hwang [1989], Lau [1991], Klein- Wassink [1989], and Prasad [1997] for an in-depth discussion of these issues. 26.11 Cleaning Cleaning, like all other parts of the process, should be considered during the design phase. Cleaning require- ments are determined largely by the flux in the solder paste, and should be determined before production is ever started. Design issues may effect the choice of flux, which determines cleaning. For example, low clearance (close to the substrate) parts are difficult to clean under, and the use of no-clean flux may be suggested. Rosin Mildly Activated (RMA) is the old standard, and if cleaning is needed with RMA, either solvent-based cleaners or water with saponifiers must be used. (Saponifiers are alkaline materials that react with the rosin so that it becomes water-soluble.) RMA tends to be non-active at “room” temperatures, and may not need to be cleaned on commercial products designed for indoor use. The major limitation on RMA at this point is the need for chemicals in the cleaning process. Water-soluble fluxes are designed to be cleaned with pure water. They remain active at room temperatures, and therefore must be cleaned when used. Beyond their activity, the other disadvantage to water soluble fluxes is that their higher surface tension relative to solvent-based cleaners means there is more difficulty cleaning under low-clearance components. No-clean fluxes are designed to not be cleaned, and this means they are of low activity (they don’t reduce oxides as well as other types of flux) and when used they should not be cleaned. No-clean fluxes are designed so that after reflow they microscopically encapsulate themselves, sealing in any active components. If the substrate is subsequently cleaned, the encapsulants may be destroyed, leaving the possibility of active flux components remaining on the board. 26.12 Prototype Systems Systems for all aspects of SMT assembly are available to support low-volume/prototype needs. These systems will typically have manual solder-paste deposition and parts placement systems, with these functions being assisted for the user. Syringe solder paste deposition may be as simple as a manual medical-type syringe dispenser which must be guided and squeezed freehand. More sophisticated systems will have the syringe mounted on an X–Y arm to carry the weight of the syringe, and will apply air pressure to the top of the syringe with a foot- pedal control, freeing the operator’s arm to guide the syringe to the proper location on the substrate and perform the negative z-axis maneuver which will bring the syringe tip into the proper location and height above the substrate. Dispensing is then accomplished by a timed air pressure burst applied to the top of the syringe under foot-pedal control. Paste volume is likewise determined by trial-and-error with the time/pressure relation and depends on the type and manufacturer of paste being dispensed. Parts placement likewise may be as simple as tweezers and may progress to hand-held vacuum probes to allow easier handling of the components. As mentioned in the Section 26.9, X–Y arm/tables are available which have vacuum-pick nozzles to allow the operator to pick a part from a tray, reel, or stick, and move the part over the correct location on the substrate. The part is then moved down into the solder paste, the vacuum is turned off manually or automatically, and the nozzle is raised away from the substrate. Soldering of prototype/low-volume boards may be done by contact soldering of each component, by a manually guided hot-air tool, or in a small batch or conveyorized oven. Each step up in soldering sophistication is, of course, accompanied by an increase in the investment required. For manufacturers with large prototype requirements, it is possible to set up an entire line that would involve virtually no hardware changes from one board to another: ? ECAD design and analysis, producing Gerber files. ? CNC circuit board mill takes Gerber files and mills out two-sided boards. ? Software translation package generates solder-pad centroid information. ? 2000 by CRC Press LLC ? Syringe solder paste deposition system takes translated Gerber file and dispenses appropriate amount at each pad centroid. ? Software translation package generates part centroid information. ? Parts placement equipment places parts based on translated part centroid information ? Assembly is reflow soldered. The only manual process in the above system is adjustment of the reflow profile based on the results of soldering an assembly. The last step in the process would be to test the finished prototype board. This system could also be used for very small volume production runs, and all components as described are available. With a change from milled boards to etched boards, the system can be used as a flexible assembly system. Defining Terms Coefficient of thermal expansion (CTE, a.k.a. TCE): A measure of the ratio between the measure of a material and its expansion as temperature increases. May be different in X-, Y-, and Z-axes. Expressed in PPM/°C. A measure that allows comparison of materials that are to be joined. Coplanarity: A simplified definition of planarity, which is difficult to measure. Coplanarity is the distance between the highest and lowest leads, and is easily measured by placing the IC on a flat surface such as a glass plate. The lowest leads will then rest on the plate, and the measured difference to the lead highest above the plate is the measurement of coplanarity. Glass transition temperature (T g ): Below T g a polymer substance, such as fiberglass, is relatively linear in its expansion/contraction due to temperature changes. Above T g , the expansion rate increases dramatically and becomes non-linear. The polymer will also lose its stability, i.e., an FR-4 board “droops” above T g . Gull wing: An SMD lead shape as shown in Fig. 26.4 for SOPs and QFPs, and in Fig. 26.11b. So called because it looks like a gull’s wing in flight. J-Lead: An SMD lead shape as shown in the PLCC definition. So called because it is in the shape of the capital letter J. Land: A metallized area intended for the placement of one termination of a component. Lands may be tinned with solder, or be bare copper in the case of SMOBC circuit board fabrication. PLCC: Plastic leaded chip carrier. Shown in Fig. 26.4, it is a common SMT IC package and is the only package that has the leads bent back under the IC itself. Planarity: Lying in the same plane. A plane is defined by the exit of the leads from the body of the IC (arrow #1 above). A second plane is defined as the average of the lowest point all leads are below the first plane (arrow #2 above). Non-planarity is the maximum variation in mils or mm of any lead of an SMD from the lowest point plane. Quad flat pack: Any flat pack IC package that has gull-wing leads on all four sides. Through-hole: Also a plate-through-hole (PTH). A via that extends completely through a substrate and is solder-plated. SMOBC: An acronym for “solder mask on bare copper”, a circuit board construction technique that does not tin the copper traces with solder prior to the placement of the solder mask on the board. Through-Hole Technology (THT): The technology of using leaded components that require holes through the substrate for their mounting (insertion) and soldering. ? 2000 by CRC Press LLC Related Topics 25.2 Layout, Placement, and Routing ? 33.3 Chip Module Thermal Resistance References F. M. Mims, III, “Surface mount technology: an introduction to the packaging revolution,” Radio Electronics, pp 58-90, 1987. S. H. Leibson, “The promise of surface mount technology,” EDN Magazine, pp 165-174, 1987. C. Higgins, Signetics Corp., presentation, November 1991. J. G. Holmes, “Surface mount solution for power devices,” Surface Mount Technol., 18-20, 1993. IPC, Proceedings, National Electronics Production and Packaging Conference-West (NEPCON West), Reed Exhibition Companies, Norwallk, Conn., 1996. J. K. Hollomon, Jr., Surface Mount Technology for PC Board Design, Indianapolis, Ind.: Prompt Publishing, 1995, chapt. 2. C. Capillo, Surface Mount Technology, Materials, Processes and Equipment, New York: McGraw-Hill, 1990, chapt. 3. C. Capillo, “Conduction heat transfer measurements for an array of surface mounted heated components,” Am. Soc. Mech. Eng., Heat Transfer Div., Proceedings of the 1993 ASME Annual Meeting, 263, 69-78, 1993. Flotherm, “Advanced thermal analysis of packaged electronic systems,” Westborough, Mass.: Flomerics, Inc., 1995. C. Y. Choi, S. J. Kim, A. Ortega, “Effects of substrate conductivity on convective cooling of electronic compo- nents,” J. Electron. Packaging, 116(3), 198-205, 1994. L. C. Lee et al., “Micromechanics of multilayer printed circuit board,” IBM J. Res. Dev., 28(6), 1984. L. C. Lee et al., Linear/Interface IC Device Databook, vol. 1, Section 3 Addendum, Motorola, 1993. T. Y. Lee, “Application of a CFD tool for system-level thermal simulation,” IEEE Trans. Components, Packaging, and Manufacturing Technol., Part A, 17(4), 564-571, 1994. J. H. Lau, Solder Joint Reliability, New York: Van Nostrand Reinhold, 1991. C. Capillo, Surface Mount Technology Materials, Processes and Equipment. New York: McGraw Hill, 1990, chapts. 7 and 8. Electronic Packaging and Production, Highlands Ranch, Colo.: Cahners Publishing Co. Intel, Packaging, Santa Clara, Calif.: intel Corporation, 1994. N. R. Cox, Reflow Technology Handbook, Minneapolis, Minn.: Research, Inc., 1992. F. Classon, Surface Mount Technology for Concurrent Engineering and Manufacturing, New York: McGraw-Hill, 1993. J. S. Hwang, Solder Paste in Electronics Packaging, New York: Van Nostrand Reinhold, 1989. C. Lea, A Scientific Guide to SMT, Electrochemical Publishing Co. Ltd, 1988. R. J. Klein-Wassink, Soldering in Electronics, Electrochemical Publishing Co. Ltd, 1989. P. P. Marcoux, Fine Pitch Surface Mount Technology, New York: Van Nostrand Reinhold, 1992. R. P. Prasad, Surface Mount Technology Principles and Practice, 2nd ed., New York: Van Nostrand Reinhold, 1997. R. Rowland, Applied Surface Mount Assembly, New York: Van Nostrand Reinhold, 1993. S. G. Shina, Concurrent Engineering and Design for Manufacture of Electronic Products, New York: Van Nostrand Reinhold, 1991. Phillips Semiconductor, Signetics Surface Mount Process and Application Notes, Sunnyvale, Calif.: Phillips Semiconductor, 1991. A. Bar-Cohen, A. D. Kraus, Advances in Thermal Modelling of Electronic Components and Systems, New York: ASME Press, 1988. Further Information Specific journal references are available on any aspect of SMT. A search of the COMPENDEX Engineering Index 1987–present will show over 1500 references specifically to SMT topics. ? 2000 by CRC Press LLC Education/Training: a partial list of organizations that specialize in education and training directly related to issues in surface mount technology: Electronic Manufacturing Productivity Facility (a joint operation of the U.S. Navy-Naval Avionics Center and Purdue University in Indianapolis). 714 North Senate Ave., Indianapolis, IN 46202-3112. 317-226-5607 SMT Plus, Inc. 5403-F Scotts Valley Drive, Scotts Valley, CA 95066; 408-438-6116 Surface Mount Technology Association (SMTA), 5200 Wilson Rd, Ste 100, Edina, MN 55424-1338. 612-920-7682. Conferences directly related to SMT: Surface Mount International (SMI). Sponsered by SMTA. National Electronics Packaging and Production Conference (NEPCON). Coordinated by Reed Exhibition Co., P.O. Box 5060, Des Plaines, IL 60017-5060. 708-299-9311. ? 2000 by CRC Press LLC