Bar-Cohen, A. “Thermal Management of Electronics” The Electrical Engineering Handbook Ed. Richard C. Dorf Boca Raton: CRC Press LLC, 2000 33 Thermal Management of Electronics 33.1 Introduction Motivation?Requirements 33.2 Heat Transfer Fundamentals 33.3 Chip Module Thermal Resistance Definition?Internal Resistance?External Resistance?Total Resistance?Multichip Modules 33.1 Introduction Motivation In the thermal control of microelectronic components, it is necessary to provide an acceptable microclimate for a diversity of devices and packages, which vary widely in size, power dissipation, and sensitivity to temperature. Although the thermal management of all electronic components is motivated by a common set of concerns, this diversity often leads to the design and development of distinct thermal control systems for different types of electronic equipment. Moreover, due to substantial variations in the performance, cost, and environmental specifications across product categories, the thermal control of similar components may require widely differing thermal management strategies. The prevention of catastrophic thermal failure, defined as an immediate, thermally induced, total loss of electronic function, must be viewed as the primary and foremost aim of electronics thermal control. Cata- strophic failure may result from a significant deterioration in the performance of the component/system or from a loss of structural integrity at one of the relevant packaging levels. In early microelectronic systems, catastrophic failure was primarily functional and thought to result from changes in the bias voltage, thermal runaway produced by regenerative heating, and dopant migration, all occurring at elevated transistor junction temperatures. While these failure modes may still occur during the device development process, improved silicon simulation tools and thermally compensated integrated circuits have largely quieted these concerns and substantially broadened the operating temperature range of today’s silicon-based logic and memory devices. Similar concerns do still exist in the use of CMOS devices for high-performance systems. Because of the dependence of CMOS circuit speed on temperature, it may be necessary to limit the maximum chip temperature to achieve a desired cycle time and/or to maintain timing margins in the system. More generally, however, thermal design in the 1990s is aimed at preventing thermally induced physical failures, through reduction of the temperature rise above ambient and minimization of temperature variations within the packaging structure(s). The use of many low-temperature materials and the structural complexity of chip packages and printed circuit boards has increased the risk of catastrophic failures associated with the vaporization of organic materials, the melting of solders, and thermal-stress fracture of leads, joints, and seals, as well as the fatigue-induced delamination and fracture or creep-induced deformation of encapsulants and Avram Bar-Cohen University of Minnesota ? 2000 by CRC Press LLC laminates. To prevent catastrophic thermal failure, the designer must know the maximum allowable tempera- tures, acceptable internal temperature differences, and the power consumption/dissipation of the various components. This information can be used to select the appropriate fluid, heat transfer mode, and inlet temperature for the coolant and to thus establish the thermal control strategy early in the design process. After the selection of an appropriate thermal control strategy, attention can be turned to meeting the desired system-level reliability and the target failure rates of each component and subassembly. Individual solid-state electronic devices are inherently reliable and can typically be expected to operate, at room temperature, for some 100,000 years, i.e., with a base failure rate of 1 FIT (failures in 10 9 h). However, since the number of devices in a typical logic component is rapidly approaching 1 million and since an electronic system may consist of many tens to several hundreds of such components, achieving a system Mean Time Between Failures of several thousand hours in military equipment and 40,000–60,000 hours in commercial electronics is a most formidable task. Many of the failure mechanisms, which are activated by prolonged operation of electronic components, are related to the local temperature and/or temperature gradients, as well as the thermal history of the package [Pecht et al., 1992]. Device-related functional failures often exhibit a strong relationship between failure rate and operating temperature. This dependence, illustrated in Fig. 33.1, is exponential in nature and commonly represented in the form of an Arrhenius relation, with unique, empirically determined coefficients for each component type. In the normal operating range of microelectronic components, a 10–20°C increase in chip temperature is thought to double the component failure rate, and even a 1°C decrease may lower the predicted failure rate associated with such mechanisms by 2–4% [Morrison et al., 1982]. Unfortunately, it is not generally possible to characterize thermally induced structural failures, which develop as a result of differential thermal expansion among the materials constituting an electronic package, in the form of an Arrhenius relation. Although these mechanical stresses may well increase as the temperature of the component is elevated, thermal stress failures are, by their nature, dependent on the details of the local temperature fields, as well as the assembly, attachment, and local operating history of the component. Further- more, thermal stress generation in packaging materials and structures is exacerbated by power transients, as well as by the periodically varying environmental temperatures, experienced by most electronic systems, during both qualification tests and actual operation. However, stress variations in the elastic domain or in the range below the fatigue limit may have little effect on the component failure rate. Consequently, the minimization or elimination of thermally induced failures often requires careful attention to both the temperature and stress FIGURE 33.1 Exponential dependence of failure rate on component temperature. ? 2000 by CRC Press LLC fields in the electronic components and necessitate the empirical validation of any proposed thermostructural design criteria. To initiate the development of a thermal design for a specified electronic product, it is first necessary to define the relevant packaging level. The commonly accepted categorization places the chip package, which houses and protects the chip, at the bottom of the packaging hierarchy (Level 1), the printed circuit board, which provides for chip-to-chip interconnect, as Level 2, the backplane, or “motherboard,” which interconnects the printed circuit boards, as Level 3, and defines the box, rack, or cabinet, which houses the entire system, as Level 4. The primary thermal transport mechanisms and commonly used heat removal techniques vary substantially from one packaging level to the next. While Level 1 thermal packaging is primarily concerned with conducting heat from the chip to the package, at Level 2 attention must be devoted to heat spreading by conduction in the printed circuit board and convection of the heat tot he ambient air, and/or transport of the heat to the board edge. Many of today’s electronic systems, as might be surmised from the frequently cited “computer-on-a-chip” or “computer-on-a-board” terminology, can be adequately packaged at Level 1 or 2. Heat sinks, or finned surfaces protruding into the air stream, are often used at Level 1 and 2 to aid in the transfer of heat into the ambient air. When Level 3 and/or 4 are present, thermal packaging generally involves the use of active thermal control measures, such as air handling systems, refrigeration systems, or water channels, heat exchangers, and pumps. Requirements Consideration of the Arrhenius relationship has resulted in peak allowable temperatures of 110–120°C for most military equipment [Morrison et al., 1982] and has led designers of commercial equipment to specify average chip operating temperatures in the 65–85°C range [Bar-Cohen, 1987, 1988]. Theoretical predictions of dramatic reductions in component failure rates have been used to justify the use of refrigerated avionics [Morrison, 1982] and cryogenic electronics [Jaeger, 1986; Vacca et al., 1987]. To accomodate rising power dissipation, commercial chip operating temperatures are expected to increase past 100°C in the coming decade. The stabilization of component temperature and minimization of the temperature differences between adjacent devices, components, and various packaging levels have long been known to reduce failure rates in electronic systems [Hilbert and Kube, 1969]. In layered structures, such as chip packages and printed circuit boards, and in the joints of surface mounted components, temperature nonuniformities, in all but the most clever designs, accentuate the differences in the thermal expansion coefficients among the various materials and can frequently result in thermal stresses that threaten the integrity of these components and joints [Engle- mier, 1984; Suhir, 1988]. The growing integration on a single chip of functionally distinct and thermally diverse devices, as in the power-integrated chips of the late 1980s and in the microsensor, RF, and in optoelectronic chips under development today, can be expected to focus renewed attention on the minimization of transient temperature and stress fields produced by localized heat sources. Despite the precipitous drop in transistor switching energy from more than 10 –9 J in 1960 to nearly 10 –13 J in devices used during the late 1980s and down to 10 –14 J in the early 1990s, the cooling requirements of microelectronic packages have not diminished. Because of increased device densities and higher operating speeds, chip heat removal requirements have actually risen from 0.1 to 0.3 W, typical of the SSI devices used in the early 1960s, to 1 to 5 W in the LSI ECL components and VLSI CMOS devices of the mid-1980s, and to values in the range of 15 to 30 W for commercial equipment in the early 1990s. Projections of current trends suggest that by the year 2000, the thermal designer will have to contend with chip power dissipations in excess of 150 W, producing surface heat fluxes of nearly 80 W/cm 2 for the smaller chips and approximately 40 W/cm 2 for the larger (2 ′ 2 cm) chips likely to be available in that time period. It may be anticipated that, by the turn of the century, substrate heat fluxes of more than 25 W/cm 2 will be encountered in both large (30 ′ 30 ′ 5 cm) and small (5 ′ 5 ′ 2 cm) multichip modules. The successful removal of these heat fluxes, in the presence of severe electrical, manufacturing cost, and reliability constraints, poses a formidable challenge to the packaging community. Nevertheless, it must be noted that the heat fluxes encountered in today’s “cutting edge technology” chips already pose a significant challenge to the thermal packaging engineer. Chip heat fluxes in the mid-1980s typically ranged from 5 W/cm 2 to nearly ? 2000 by CRC Press LLC 30 W/cm 2 , for both single-chip packages and multichip modules [Bar-Cohen, 1987]. Recently released com- mercial computers often include chips dissipating 15 to 30 W/cm 2 [e.g., Kaneko et al., 1990; Pei et al., 1990], and laboratory prototypes have extended the chip heat flux range to nearly 65 W/cm 2 . These heat fluxes are comparable, at the upper end, to the thermal loading experienced by reentry vehicles and even, at the lower end, to heat fluxes imposed on rocket motor cases. The anticipated peak heat flux in the year 2000 of approx- imately 100 W/cm 2 is in the range of thermal loadings associated with nuclear blasts. Design Procedure Generation of an appropriate thermal design begins with tabulation of the specified critical temperatures (source and sink) and the heat generation rate. These parameters can be used to define the target thermal resistance, as R target = (T source – T sink )/q gen [K/W] The electronics thermal control literature, as well as subsequent sections of this chapter, present much of the relevant thermal packaging information in the form of thermal resistances. At its most fundamental level, the thermal packaging task involves selecting a combination of heat removal mechanisms which yield an overall thermal resistance that is not greater than the target value. The implementation of such a system will assure that the heat source, typically a microprocessor or memory chip, will operate at an acceptable temperature. As will be discussed later in this chapter, in nearly all modes of heat transfer the geometry of the heat flow path, i.e., length and area, play an important role in determining the heat source temperature. Consequently, it is desirable to obtain the relevant geometric details (lengths, thicknesses, areas, volumes) at this early stage in the design process. Combining the geometric information with the target thermal resistance, it is often convenient to define an area- specific or volume-specific target thermal resistance in units of K/(W/cm 2 ) and K/(W/cm 3 ), respectively. When the target thermal resistance is known, first-order (or “back-of-the-envelope”) calculations are performed to evaluate the severity of the thermal management problem. Although some designs can be completed at this stage, often more precise calculations are needed to verify that the proposed approach does indeed meet the target thermal resistance value. Such calculations can be performed analytically by drawing on the wealth of knowledge in the thermal sciences, numerically using commercial general purpose software, or with commercial software specifically tailored to the thermofluid and thermostructural configurations encountered in packaging. Due to the difficulty in predicting thermal contact resistances at lightly and variably loaded mechanical interfaces and in determining the convective resistances associated with irregular package and printed circuit board geometries, some experimental data is generally needed to establish key parameters or verify system performance. The search for an adequate thermal packaging strategy generally begins with consideration of passive transfer modes—conduction, natural convection, and radiation, which require no external motive power and no moving parts. Due to its near-universal availability, air is the most common and preferred cooling fluid. Many electronic systems can be successfully cooled by passive means and especially by natural convection in air. When such passive means are incapable of properly controlling the heat source temperature, the designer must examine the use of active thermal control techniques, including blown air, pumped water, and circulated refrigerants. Immersion of the electronic components directly in dielectric liquids, which can then be pumped or allowed to circulate naturally, provides an additional, though less common, alternative. 33.2 Heat Transfer Fundamentals To determine the temperature differences encountered in the flow of heat within electronic systems, it is necessary to recognize several different heat transfer mechanisms and their governing relations. In a typical system, heat removal from the active regions of the chip(s) requires the use of several mechanisms, some operating in series and others in parallel, to transport the generated heat to the coolant. Thermal transport through solids is governed by the Fourier equation, which, in one-dimensional form, is expressible as q = kAdT/dx [W] (33.1) ? 2000 by CRC Press LLC where q is the heat flow, k is the thermal conductivity of the medium, A is the cross-sectional area for heat flow, and dT/dx the temperature gradient. The temperature difference resulting from the conduction of heat is thus related to the thermal conductivity of the material, the cross-sectional area, and the path length, Dx, or (T 1 – T 2 ) cond = q(Dx/kA) [K] (33.2) The form of this equation suggests that, by analogy to electrical current flow in a conductor, it is possible to define a conduction thermal resistance as [Kraus, 1958] R cond = (T 1 – T 2 )/q = Dx/kA [K/W] (33.3) Using the thermal conductivities tabulated in Table 33.1, conduction resistance values for packaging materials with typical dimensions can be found by use of Eq. 33.3 or by inspection of Fig. 33.2. Values are seen to range from 2K/W for a 100 mm 2 by 1 mm thick layer of epoxy encapsulant to 0.0006 K/W for a 100 mm 2 by 25 micron (1 mil) thick layer of copper. Similarly, the values of the conduction resistance for typical “soft” bonding materials are found to lie in the range of 0.1 K/W for solder and 1–3K/W for epoxies and thermal pastes, for Dx/A ratios of 0.25 to 1 m –1 . TABLE 33.1 Thermal Conductivities of Typical Packaging Materials at Room Temperature Materials Thermal Conductivity (W/m K) Air 0.024 Mylar 0.19 Silicone rubber 0.19 Solder mask 0.21 Epoxy (dielectric) 0.23 Ablefilm 550 dielectric 0.24 Nylon 0.24 Polytetrafluorethylene 0.24 RTV 0.31 Polyimide 0.33 Epoxy (conductive) 0.35 Water 0.59 Mica 0.71 Ablefilm 550 K 0.78 Thermal greases/pastes 1.10 Borosilicate glass 1.67 Glass epoxy 1.70 Stainless steel 15 Kovar 16.60 Solder (Pb-In) 22 Alumina 25 Solder 80-20 Au-Sn 52 Silicon 118 Molybdenum 138 Aluminum 156 Beryllia 242 Gold 298 Copper 395 Silver 419 Diamond 2000 ? 2000 by CRC Press LLC Thermal transport from a surface to a fluid in motion is called convective heat transfer and can be related to the heat transfer coefficient, h, the surface-to-fluid temperature difference, and the “wetted” area, in the form q = hA(T surf – T fluid ) [W] (33.4) The differences among convection to a fast-moving fluid, a slowly flowing fluid, and a stagnant fluid, as well as variations in the convective heat transfer rate among various fluids, are reflected in the value of h. Some theoretical and many empirical correlations are available for determining this convective heat transfer coefficient (e.g., Kraus and Bar-Cohen, 1983). Using Eq. (33.4), it is possible to define the convective thermal resistance, as R conv = (hA) –1 [K/W] (33.5) Values of this convective resistance, for a variety of coolants and heat transfer mechanisms, are shown in Fig. 33.3 for a typical heat source area of 10 cm 2 and a velocity range of 2–8 m/s. These resistances are seen to vary from 100 K/W for natural convection in air to 33 K/W for forced convection in air, to 1 K/W in fluorocarbon liquid in forced convection to less than 0.5 K/W for boiling in fluorocarbon liquids. Unlike conduction and convection, radiative heat transfer between two surfaces or between a surface and its surroundings is not linearly dependent on the temperature difference and is expressed instead as q = sAF(T 1 4 – T 2 4 )[W] (33.6) FIGURE 33.2 Conductive thermal resistances for packaging materials. 10 1 10 -1 10 -2 10 -2 10 -1 10 2 110 10 -3 Thermal Conductivity (W/m . K) ABC/GJS R cond (K/W) Epoxy Alumina Silicon Copper R cond = ?X/A ?X/A = 1.0 m -1 ?X/A = .75 m -1 ?X/A = .5 m -1 ?X/A = .25 m -1 ? 2000 by CRC Press LLC where F includes the effect of surface properties and geometry and s is the Stefan-Boltzmann constant, which equals 5.67 ′ 10 –8 W/m 2 K 4 . For an ideal, or black, radiating surface in a perfectly absorbing environment, F equals unity. For modest temperature differences, this equation can be linearized to the form q r = h r A(T 1 – T 2 ) [W] (33.7) where h r is the effective “radiation” heat transfer coefficient and is approximately equal to 4s F (T 1 T 2 ) 1.5 . It is of interest to note that for temperature differences on the order of 10 K, the radiative heat transfer coefficient, h r , for a radiationally ideal surface in an absorbing environment, is approximately equal to the heat transfer coefficient in natural convection of air. Noting the form of Eq. (33.7), the radiational thermal resistance, analogous to the convective resistance, is seen to equal (h r A) –1 . Ebullient thermal transport displays a complex dependence on the temperature difference between the heated surface and the saturation temperature (boiling point) of the liquid. In nucleate boiling, the primary region of interest, the ebullient heat transfer rate can be approximated by a relation of the form q b = C￠ sf A(T surf – T sat ) 3 [W] (33.8) where C￠ sf is a function of the surface/fluid combination and T sat is the boiling point of the liquid. For comparison purposes, it is possible to define a boiling heat transfer coefficient, h b , equal to C￠ sf (T 1 – T sat ) 2 , which, however, will vary strongly with surface temperature. In the thermal design of electronic equipment, frequent use is made of heat sinks, involving finned or extended surfaces (Kraus and Bar-Cohen, 1995). While such finning can substantially increase the surface area in contact with the coolant, conduction in the thermal fin reduces the average temperature of the exposed surface relative FIGURE 33.3External thermal resistances for various fluids and cooling modes. ? 2000 by CRC Press LLC to the fin base. In the analysis of such finned surfaces, it is thus common to define a fin efficiency, h, equal to the ratio of the average temperature rise of the fin (above the coolant) to the temperature rise of the fin base. Using this approach, heat transfer by a fin or fin structure can be expressed in the form q f = hAh(T o – T f ) [W] (33.9) where T o is the temperature of the fin base. The thermal resistance of a finned surface is given by (hhA) –1 and for a properly designed surface, the fin efficiency can be expected to lie between 0.5 and 0.8. The transfer of heat to a flowing gas or liquid, not undergoing a phase change, results in an increase in the coolant temperature, according to q = m . c p (T out – T in ) = rQ ? c p (T out – T in ) [W] (33.10) where m · is the mass flow rate of the coolant, r is the density, and Q ? is the volumetric flow rate. Based on this relation, it is possible to define an effective flow resistance, R f , as R f = (mc p · ) –1 [K/W] (33.11) In a first-order thermal model, it is generally appropriate to relate the heat source temperature to the average (rather than the outlet) coolant temperature. In such calculations the flow resistance should be taken to equal one-half of the value given by Eq. (33.11). These average flow resistances for the three common coolants in electronics thermal management, i.e., air, water, and FC-72 (3M Trade Name), are shown in Figure 33.4. The expression of the governing heat transfer relations in the form of thermal resistances greatly simplifies the first-order thermal analysis of electronic systems. Following the established rules for resistance networks, thermal resistances that occur sequentially along a thermal path can be simply summed to establish the overall thermal resistance for that path. Similarly, the reciprocal of the effective overall resistance of several parallel heat transfer paths can be found by summing the reciprocals of the individual resistances. In refining the thermal design of an electronic system, prime attention should, then, be devoted to reducing the largest resistances along a specified thermal path and/or providing parallel paths for heat removal from a critical area. While the thermal resistances associated with various paths and thermal transport mechanisms constitute the building blocks in performing a detailed thermal analysis, they have also found widespread application as figures-of-merit in evaluating and comparing the thermal efficacy of various packaging techniques and thermal management strategies. The determination of the relevant thermal resistances is, thus, the key task in the thermal design of an electronic system. 33.3 Chip Module Thermal Resistance Definition The thermal performance of chip packaging techniques is commonly compared on the basis of the overall (junction-to-coolant) thermal resistance, R T . This packaging figure-of-merit is generally defined in a purely empirical fashion to equal R T = (T j – T f )/q c [K/W] (33.12) where T j and T f are the junction and coolant (fluid) temperatures, respectively, and q c is the chip heat dissipation. Unfortunately, however, most measurement techniques are incapable of detecting the actual junction tem- perature, i.e., the temperature of the small volume at the interface of p-type and n-type semiconductors, and, hence, this term generally refers to the average temperature or a representative temperature on the chip. Because ? 2000 by CRC Press LLC many of the failure mechanisms of integrated circuits are accelerated by an increase in the average chip temperature, low thermal resistances are to be preferred in nearly all categories of electronic packaging. Single-chip packages can be characterized by their internal, or so-called junction-to-case, resistance. The con- vective heat removal techniques applied to the external surfaces of the package, including the effect of finned heat sinks and other thermal enhancements, can be compared on the basis of the external thermal resistance. The complexity of heat flow and coolant flow paths in a multichip module generally requires that the thermal capability of these packaging configurations be examined on the basis of overall, or chip-to-coolant, thermal resistance. Examination of various packaging techniques reveals that the junction-to-coolant thermal resistance is, in fact, composed of an internal, largely conductive, resistance and an external, primarily convective, resistance. As shown in Fig. 33.5, the internal resistance, R jc , is encountered in the flow of dissipated heat from the active chip surface, through the materials used to support and bond the chip, and on to the case of the integrated circuit package. The flow of heat from the case directly to the coolant, or indirectly through a fin structure and then to the coolant, must overcome the external resistance, R ex . Internal Resistance As previously noted, conductive thermal transport is governed by the Fourier equation (Eq. 33.1). For com- posite, rectilinear structures, as encountered in many chip modules, the Fourier equation (with temperature and time invariant properties), takes the form (33.13) FIGURE 33.4Flow thermal resistances for typical electronic coolants. 0 0 0.1 0.2 m (kg/s) m 3 / s R ? (K/W) 0.3 0 100 200 300 400 1000 10 -3 10 -2 10 -1 200 300 400 500 0 0.1 0.2 0.3 0.4 0.5 0 0 Water FC-72 Air Water FC-72 Air qTT xkA ie p =- ? ()()] / D/[W ? 2000 by CRC Press LLC where T i and T e are the temperatures internal and external to the composite structure, respectively, Dx is the thickness of each material in the direction of heat flow, and the summation sign pertains to p distinct layers of material. The thermal conductivities of typical packaging materials are tabulated in Table 33.1. Assuming that power is dissipated uniformly across the chip surface and that heat flow is largely one- dimensional, Eq. (33.13) can be used to provide a first-order approximation for the internal chip module resistance, as (33.14) where the summed terms represent the thermal resistances of the individual layers of silicon, solder, copper, alumina, etc. It is to be noted that the contact resistances that occur at the interfaces between pairs of materials can be added, as appropriate, to this summation. As may be seen in Fig. 32.2, decreasing the thickness of each layer and/or increasing the thermal conductivity and cross-sectional area, reduce the resistance of the individual layers. In chip packages that provide for lateral spreading of the heat generated in the chips, the increasing cross- sectional area for heat flow at successive layers reduces the internal thermal resistance. Unfortunately, however, there is an additional resistance associated with the lateral flow of the heat, which must be taken into account in determining the chip-to-case temperature difference. Following Yovanovich and Antonetti [1988], the spreading resistance for a small heat source on a thick substrate (typically 3–5 times thicker than the square root of the heat source area) can be expressed as R c = (0.475 – 0.62e + 0.13e 3 )/k (A c ) 0.5 [K/W] (33.15) where e is the square root of the ratio of the heat source area to the substrate area, k the thermal conductivity of the substrate, and A c the area of the heat source. For relatively thin layers on thicker substrates, Eq. (33.15) cannot provide an acceptable prediction of R c . Instead, use can be made of the numerical results plotted in Fig. 33.6 to obtain the requisite value of the spreading resistance. The internal thermal resistance of a chip package can be expected to vary from approximately 50 K/W for a plastic package with no heat spreader, to 10 to 15 K/W for a plastic package with heat spreader, and to 3 to FIGURE 33.5Thermal resistances in a single-chip package. RTTq xkA jc j c c p =- = ? ()()[//K/W]D ? 2000 by CRC Press LLC 8 K/W for a ceramic package or a specially designed plastic chip package. Carefully designed chip packages can attain even lower values of R jc , but the conductive thermal resistances at the interfaces between materials, and especially along the chip surfaces where the heat fluxes are highest, can typically reach 1 K/W for epoxied interfaces and impose a lower bound on the internal package resistance. External Resistance To precisely determine the resistance to thermal transport from a surface to a fluid in motion, i.e., the convective resistance, it is necessary to quantify the heat transfer coefficient, h. For a particular geometry and flow regime, h may be found from available empirical correlations and/or theoretical relations. For flow along plates and in the inlet zones of parallel-plate channels, as may well be encountered in electronic cooling applications, the low velocity, or laminar flow, average convective heat transfer coefficient is given by [Kraus and Bar-Cohen, 1983] h = 0.664(k/l)(Re) 0.5 (Pr) 0.333 [W/m 2 K] (33.16) for Re < 2 ′ 10 5 where k is the fluid thermal conductivity, l the length (in the flow direction) of the surface, Re the Reynolds number (equal to the product of velocity, density, and length divided by the fluid viscosity), and Pr the Prandtl number (equal to the product of specific heat and viscosity divided by the thermal conductivity of the fluid). Inserting the various parameters associated with the Re and Pr in Eq. (33.16), the laminar heat transfer coefficient is found to be directly proportional to the square root of fluid velocity and inversely proportional to the square root of the length. Furthermore, increases in the thermal conductivity of the fluid and in the Pr, as are encountered in replacing air with a liquid coolant, can be expected to result in higher heat transfer coefficients. In studies of low-velocity convective air cooling of simulated integrated circuit packages, h has been found to depend somewhat more strongly on Re than suggested in Eq. (33.16), and to display an Re exponent of 0.54-0.72 [Buller and Kilburn, 1981; Sparrow et al., 1982; Wirtz and Dykshoorn, 1984]. In higher velocity turbulent flow, the dependence of the convective heat transfer coefficient on the Re increases and is typically given by [Kraus and Bar-Cohen, 1983]: h = 0.036(k/l) (Re) 0.8 (Pr) 0.333 , W/m 2 K (33.17) for Re > 3 ′10 5 FIGURE 33.6The thermal resistance for a circular heat source on a two-layer substrate. (Source: M.M. Yovanovich and V.W. Antonetti, “Application of Thermal Contact Resistance Theory toElectronic Packages,” in Advances in Thermal Modeling of Electronic Components and Systems, vol. 1, A. Bar-Cohen and A.D. Kraus, Eds., New York: Hemisphere, 1988, pp. 79–128. With permission.) ? 2000 by CRC Press LLC In this flow regime, the convective heat transfer coefficient is, thus, found to vary directly with the velocity to the 0.8 power and inversely with the characteristic dimension to the 0.2 power. The dependence on fluid conductivity and Pr remains unchanged. Applying Eq. (33.16) or (33.17) to the transfer of heat from the case of a chip module to the coolant, the external resistance, R ex = 1/hA, is found to be inversely proportional to the wetted area and to the coolant velocity to the 0.5 to 0.8 power and directly proportional to the length in the flow direction to the 0.5 to 0.2 power. It may, thus, be observed that the external resistance can be strongly influenced by the fluid velocity and package dimensions and that these factors must be addressed in any meaningful evaluation of the external thermal resistances offered by various packaging technologies. As previously noted, values of the external resistance, for a variety of coolants and heat transfer mechanisms, are shown in Fig. 33.3 for a typical component wetted area of 10 cm 2 and a velocity range of 2 m/s to 8 m/s. Clearly, larger chip packages will experience proportionately lower external resistances than the tabulated values, and conduction of heat through the leads and package base into the printed circuit board or substrate will serve to further reduce the effective thermal resistance. When the direct cooling of the package surface is inadequate to maintain the desired chip temperature, it is common to attach finned heat sinks, or compact heat exchangers, to the chip package. These heat sinks can considerably increase the wetted area but may act to reduce the convective heat transfer coefficient and most definitely introduce additional conductive resistances in the adhesive used to bond the heat sink to the package and in the body of the heat sink. Typical air-cooled heat sinks for a single chip package with a base area of 3.3 ′ 3.3 cm on one side can reduce the external resistance to approximately 15 K/W in natural convection and as low as 5 K/W for moderate forced convection velocities. When a heat sink or compact heat exchanger is attached to the package, the external resistance can be modified to account for the bond-layer conduction and fin efficiency as R ex = (T c – T f )/q c = (Dx/kA) b + (hhA) –1 (33.18) In properly designed fin structure, h can be expected to fall in the range of 0.5 to 0.8 [Kraus and Bar-Cohen, 1983]. Relatively thick fins in a low velocity flow of gas are likely to yield fin efficiencies approaching unity. This same unity value would be appropriate, as well, for an unfinned surface and, thus, serve to generalize the use of Eq. (33.18) to all package configurations. Total Resistance Based on the accuracy of the assumptions used in the preceding development, the overall chip module resistance, relating the chip temperature to the inlet temperature of the coolant, can be found by summing the internal, external, and flow resistances to yield: (33.19) In evaluating the thermal resistance by this relation, care must be taken to determine the effective cross-sectional area for heat flow at each layer in the module. For single-chip modules, the requisite areas can be readily obtained, although care must be taken to consider possible voidage in solder and adhesive layers. As previously noted in the development of the relations for external and internal resistances, Eq. (33.19) shows R T to be a strong function of the convective heat transfer coefficient, the flowing heat capacity of the coolant, and geometric parameters (thickness and cross-sectional area of each layer). Thus, the introduction of a superior coolant, use of thermal enhancement techniques that increase the local heat transfer coefficient, and selection of a heat transfer mode with inherently high heat transfer coefficients (e.g., boiling) will all be reflected in appropriately lower external and total thermal resistances. Similarly, improvements in the thermal conductivity of and reduction in the thickness of the relatively low conductivity bonding materials (e.g., soft solder, epoxy, silicone) would act to reduce the internal and total thermal resistances. R R R R R xkA hA mc Tjcexf c p p =++= + + + ? [()]() ˙ – D/ h 1 2 ? 2000 by CRC Press LLC Frequently, however, even more dramatic reductions in the total resistance can be achieved simply by increasing the cross-sectional area for heat flow, within the chip module (e.g., chip, substrate, heat spreader) as well as along the wetted exterior surface. The implementation of such a scale-up generally results in a larger module footprint and/or lower volumetric packaging density, both of which are highly undesirable, and yet is rewarded with a lower thermal resistance. In evaluating packaging approaches, it must, therefore, be understood that the thermal resistance is a somewhat flawed figure-of-merit and that a better reflection of the efficacy of a thermal management technique can be obtained by normalizing R T with respect to the packaging density, using the number of chips on a substrate or number of chips/packages on a printed circuit board. Multichip Modules The thermostructural complexity of the multichip modules in current use hampers effective thermal charac- terization and introduces significant uncertainty in any attempt to compare the thermal performance of these packaging configurations. Variations in heat generation patterns across the active chips (e.g., devices versus drivers), as well as nonuniformities in heat dissipation among the chips assembled in a single module, further complicate this task. To establish a common, though approximate, basis for comparison of multichip modules, it is possible to neglect these variations and consider that the heat generated by each chip flows through a unit cell of the module structure to the external coolant [Bar-Cohen, 1987, 1988]. For a given structure, increasing the area of the unit cell allows heat to spread from the chip to a larger cross section, reducing the heat flux at some of the thermally critical interfaces and at the convectively cooled surfaces. Consequently, the thermal performance of a multichip module can be best represented by the area-specific thermal resistance, i.e., the temperature difference between the chip and the coolant divided by the substrate heat flux. This figure-of- merit is equivalent to the inverse of the overall heat transfer coefficient, U, commonly used in the compact heat exchanger literature. Despite significant variation in design and fabrication, all the late-1980s water-cooled modules and one air-cooled module provide a specific thermal resistance of approximately 20°C for every watt per square centimeter at the substrate. In cutting-edge multichip modules in use in the 1990s, this value was reduced to 5–10 K/(W/cm 2 ). Nomenclature A area, m 2 c p specific heat, W/kgK C￠ sf boiling surface parameter, W/m 2 K 3 F radiational factor h heat transfer coefficient, W/m 2 K k thermal conductivity, W/mK l path length, m m mass flow, kg/s Pr Prandtl Number, @ c p m/k q heat flow, W R thermal resistance, K/W Re Reynolds Number, o rvl/m T temperature, K v velocity, m/s x length, m s Stefan-Boltzmann constant, 5.67 2 10–8 W/m 2 K 4 h fin efficiency r density, kg/m 3 Q ? volumetric flow rate, m 3 /s e ratio of heater to substrate size m viscosity, kg/ms Subscripts b bond layer b boiling c constriction or spreading cond conduction conv convection f, fluid fluid i internal in inlet j junction jc junction to case o base, external out outlet r radiation sat thermodynamic saturation surf surface T total ? 2000 by CRC Press LLC Defining Terms Catastrophic thermal failure: An immediate, thermally induced total loss of electronic function by a com- ponent or system. Conductive heat transfer: The process by which heat diffuses through a solid or stationary fluid. Convective heat transfer: The process by which a moving fluid transfers heat to or from a wetted surface. Ebullient heat transfer: The heat transfer process associated with the formation and release of vapor bubbles on a heated surface. Fin efficiency: A thermal characteristic of an extended surface that relates the heat transfer ability of the additional area to that of the base area. Heat transfer coefficient: A characteristic parameter of convective heat transfer that determines the heat flux that can be transported from a wetted surface with a specified temperature difference. Prandtl number: A nondimensional characteristic of fluids, relating the rate of momentum diffusion to heat diffusion. Radiative heat transfer: The process by which long-wave electromagnetic radiation transports heat from a surface to its surroundings. Reynolds number: A nondimensional parameter used to determine the transition to turbulence in a fluid flowing in pipes or past surfaces. Thermal fin: An extension of the surface area in contact with a heat transfer fluid, usually in the form of a cylinder or rectangular prism protruding from the base surface. Thermal management or control: The process or processes by which the temperature of a specified compo- nent or system is maintained at the desired level. Thermal resistance: A thermal characteristic of a heat flow path, establishing the temperature drop required to transport heat across the specified segment or surface; analogous to electrical resistance. Related Topics 1.1 Resistors ? 30.2 Power Conversion References A. Bar-Cohen, “Thermal management of air- and liquid-cooled multichip modules,” IEEE CHMT Transactions, vol. CHMT-10, no. 2, pp. 159–175, 1987. A. Bar-Cohen, “Thermal Design and Control,” in Physical Architecture of VLSI Systems, R.J. Hannemann, A.D. Kraus, and M. Pecht, Eds., New York: John Wiley & Sons, 1994, Chapter 9, pp. 541–605. A. Bar-Cohen, “Addendum and correction to thermal management of air- and liquid-cooled multichip mod- ules,” IEEE CHMT Transactions, vol. CHMT-11, no. 3, pp. 333–334, 1988. M.L. Buller and R.F. Kilburn, “Evaluation of surface heat transfer coefficients for electronic module packages,” Heat Transfer in Electronic Equipment, vol. HTD-20, ASME, New York, 1981. W. Englemier, “Functional cycles and surface mounting attachment reliability,” in Thermal Management Con- cepts in Microelectronic Packaging, R.T. Howard, et al., Eds., ISHM Technical Monograph Series, 6984- 003, ISHM, New York, 1984, pp. 83–109. C.A. Harper, Ed., Electronic Packaging and Interconnection Handbook, New York: McGraw-Hill, 1991, p. 2.7. W.F. Hilbert and F.H. Kube, “Effects on electronic equipment reliability of temperature cycling in equipment,” Final Report, Grumman Aircraft Engineering Co., Report No. EC-69-400, Bethpage, N.Y., 1969. R.C. Jaeger, “Development of low temperature CMOS for high performance computer systems,” IEEE Interna- tional Conference on Computer Design: VLSI in Computers, 1986, pp. 128–130. A. Kaneko, K. Seyama, and M. Suzuki, “LSI packaging and cooling technologies for Fujitsu VP-2000 Series,” Fujitsu, vol. 41, no. 1, pp. 12–19, 1990. A.D. Kraus, “The use of steady state electrical network analysis in solving heat flow problems,” 2nd National Heat Transfer Conference, Chicago, Ill., 1958. A.D. Kraus and A. Bar-Cohen, Thermal Analysis and Control of Electronic Equipment, New York: Hemisphere Publishing Corporation, 1983. ? 2000 by CRC Press LLC A.D. Kraus and A. Bar-Cohen, Design and Analysis of Heat Sinks, New York: John Wiley & Sons, 1995. G.N. Morrison, J.M. Kallis, L.A. Strattan, I.R. Jones, and A.L. Lena, “RADC thermal guide for reliability engineers,” Report Number RADC-TR-82-172, Rome Air Development Center, Air Force Systems Com- mand, Griffis Air Force Base, New York, 1982. R.A. Morrison, “Improved avionics reliability through phase change conductive cooling,” Proceedings, IEEE National Telesystems Conference, pp. B5.6.1–B5.6.5, 1982. W. Nakayama, “Thermal management of electronic equipment: A review of technology and research topics,” in Advances in Thermal Modeling of Electronic Components and Systems, vol. 1, A. Bar-Cohen and A.D. Kraus, Eds., New York: Hemisphere Publishing Corporation, 1988, pp. 1–78. M. Pecht, P. Lall, and E. Hakim, “The influence of temperature on integrated circuit failure mechanisms,” Advances in Thermal Modeling of Electronic Components and Systems, vol. 3, A. Bar-Cohen and A.D. Kraus, Eds., New York: ASME Press, 1992. J. Pei, S. Heng, R. Charlantini, and P. Gildea, “Cooling components used in the Vax 9000 family of computers,” Proceedings, 1990 International Electronic Packaging Society Conference, 1990, pp. 587–601. E.M. Sparrow, J.E. Niethhammer, and A. Chaboki, “Heat transfer and pressure drop characteristics of arrays of rectangular modules encountered in electronic equipment,” Int. J. Heat & Mass Transfer, vol. 25, no. 7, pp. 961–973, 1982. E. Suhir, “Thermal stress in electronic components,” in Advances in Thermal Modeling of Electronic Components and Systems, vol. 1, A. Bar-Cohen and A.D. Kraus, Eds., New York: Hemisphere Publishing Corporation, 1988, pp. 337–412. R.R. Tummala and E.J. Rymaszewski, Microelectronics Packaging Handbook, New York: Van Nostrand Reinhold, 1989, p. 174. A. Vacca, D. Resnick, D. Frankel, R. Bach, J. Kreilich, and D. Carlson, “A cryogenically cooled CMOS VLSI supercomputer,” VLSI Systems Design, pp. 80–88, 1987. R.A. Wirtz and P. Dykshoorn, “Heat transfer from arrays of flat packs in channel flow,” Proceedings, 4th International Electronic Packaging Society Conference, New York, 1984, pp. 318–326. M.M. Yovanovich and V.W. Antonetti, “Application of thermal contact resistance theory to electronic packages,” in Advances in Thermal Modeling of Electronic Components and Systems, vol. 1, A. Bar-Cohen and A.D. Kraus, Eds., New York: Hemisphere Publishing Corporation, 1988, pp. 79–128. ? 2000 by CRC Press LLC