设计中心 电子设计自动化技术 教师：李平教授（博导） Email: pli@uestc.edu.cn Tel: 83201794 设计中心 电子设计自动化技术 第六章 设计中心 Designing Hierarchically 设计中心 Design Hierarchically - Multiple Design Files ? VHDL hierarchical design requires Component Declarations and Component Instantiations top.vhd entity-architecture “top” component “mid_a”，component “mid_b” mid_a. vhd entity-architecture “mid_a” component “bottom_a” mid_b. vhd entity-architecture “mid_b” component “bottom_a” component “bottom_b” bottom_a. vhd entity-architecture “bottom_a” bottom_b. vhd entity-architecture “bottom_b” 设计中心 Component Declaration and Instantiation ? Component Declaration - Used to declare the Port types and the Data Types of the ports for a lower-level design. COMPONENT <lower-level_design_name> PORT ( <port_name> : <port_type> <data_type>; ……); END COMPONENT; ? Component Instantiation - Used to map the ports of a lowerlevel design to that of the current-level design <instance_name> : <lower-level_design_name> PORT MAP(<lower-level_port_name> => <current_level_port_name>, …); 设计中心 Component Declaration and Instantiation ? Next-level of hierarchy design must have a Component Declaration for a lower-level design before it can be Instantiated ARCHITETURE structure_view OF Full_adder IS COMPONENT half_adder PORT (a, b : IN BIT ;s ,c : OUT BIT); END COMPONENT; SIGNAL a,b,c:BIT; BEGIN u1: half_adder PORT MAP (x,y,a,b); …… END structure_view; 设计中心 Benefits of Hierarchical Designing 1. In a design group, each designer can create separate functions (components) in separate design files. 2. These components can be shared by other designers or can be used for future projects. 3. Therefore, designing hierarchically can make designs more modular and portable 4. Designing Hierarchically can also allow easier and faster alternative implementations 设计中心 Example of hierarchical design bottom_inv.VHD middle.VHD top.VHD 设计中心 ENTITY top IS END top; ARCHITECTURE struc OF top IS COMPONENT middle GENERIC ( n : POSITIVE ); PORT(input : IN BIT; output : OUT BIT ); END COMPONENT; SIGNAL s1,s2 : BIT ; BEGIN U1: middle GENERIC MAP (n=>9) PORT MAP (input=>s1, output=>s2); END struc; top.VHD 标点符号 设计中心 Example of hierarchical design bottom_inv.VHD middle.VHD top.VHD 设计中心 ENTITY middle IS GENERIC (n : POSITIVE); PORT(input : IN BIT; output : OUT BIT); END middle; ARCHITECTURE struc OF middle IS COMPONENT bottom_inv PORT (in1 : IN BIT; out1 : OUT BIT); END COMPONENT; SIGNAL s : BIT_VECTOR(1 TO n-1); middle.VHD 设计中心 BEGIN g1 : FOR i IN 1 TO n GENERATE g2 : IF i = 1 GENERATE u1 : bottom_inv PORT MAP (input, s(i)); END GENERATE; g3 : IF i>1 AND i<n GENERATE u2 : bottom_inv PORT MAP (s(i-1), s(i)); END GENERATE; g4 : IF i = n GENERATE u3 : bottom_inv PORT MAP (s(n-1), output); END GENERATE; END GENERATE; END struc; 设计中心 Example of hierarchical design bottom_inv.VHD middle.VHD top.VHD 设计中心 entity bottom_inv IS port (a : IN bit; b : OUT bit); end bottom_inv; architecture rtl OF bottom_inv IS begin process(a) begin if(a = '1') then b <= '0'; else b <= '1'; end if; end process; end rtl; Bottom_inv.VHD 设计中心 GENERIC 设计中心 ?意义：待定参数不同层次间信息传递 ? GENERIC的说明 GENERIC<参数表>；--实体中说明(只定义名称/数据类型) ?参数化元件的例示 标号：component_name GENERIC MAP(参数值) --引用时指定参数值 PORT MAP (……)；--初始化后才能仿真综合 Note: GENERIC语句所涉及数据除integer外不可综合 GENERIC 设计中心 参数化实体 ?所谓参数化实体，是指在定义实体时，有些 待定参数，这些参数只有在该实体被引用时 才指定参数值。 ?待定参数应是实体外观说明的一部分，由参 数说明语句generic说明。该语句的形式为： GENERIC <参数表>； 所有参数只需定义名称及数据类型。 设计中心 ENTITY invert_link IS GENERIC (n : POSITIVE); PORT( input : IN BIT; output : OUT BIT); END invert_link; ……(P.65-66 ) 该构造中反相器的个数和信号线的数目均由待 定参数n决定。 【例5-19】反相器链 设计中心 参数化元件 ?与参数化实体相对应，也有参数化元件。 ?参数化元件说明与参数化实体格式相似。 ?参数化元件的例示： 标号：component_name GENERIC MAP(参数值) --引用时指定参数值 PORT MAP (……)；--初始化后才能仿真综合 设计中心 ENTITY design IS END design ; ARCHITECTURE design1 OF design IS COMPONENT invert_link GENERIC（n:POSITIVE）； PORT(input:IN BIT；output:OUT BIT)； END COMPONENT; SIGNAL s1,s2 : BIT ; BEGIN U1: invert_link GENERIC MAP (n=>9) PORT MAP (input=>s1,output=>s2); END design1; 【例5-20】参数化元件的说明与引用 标点符号 设计中心 LIBRARY 设计中心 ?类似文件的目录管理 VHDL中包含已验证(编译)的entites, architectures和 packages ?利于重配置（reconfiguration）和更新 ?每一个库有一个逻辑名 用户当前的设计单元，其库名为WORK WORK库和STD库是缺省打开的 其它库可由设计者或EDA厂商提供 比如IP（Intellectual Property）库，IEEE标准库等 Libraries 设计中心 Model Referencing of Library/Package ? All packages must be compiled ? Implicit Libraries –Work –STD Note: Items in these packages do not need to be referenced, they are implied. ? LIBRARY Clause – Defines the library name that can be referenced. – Is a symbolic name to path/directory. – Defined by the Compiler Tool. ? USE Clause – Specifies the package and object in the library that you have specified in the Library clause. 设计中心 Example LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY test IS PORT ( a, b, sel : IN std_logic; x : OUT std_logic ); END cmpl_sig; ARCHITECTURE logic OF test IS BEGIN x <= (a AND NOT sel) OR b; END logic; LIBRARY <name>, <name> ; – name is symbolic and define by compiler tool. Note: Remember that WORK and STD do not need to be defined. USE lib_name.pack_name.object; – ALL is a reserved word. Placing the Library/Use clause 1st will allow all following design units to access it. 设计中心 LIBRARY STD ; ? Contains the following packages: standard ( Types: Bit, Boolean, Integer, Real, and Time. All operator functions to support types) textio (File operations) ? An implicit library (built-in) Does not need to be referenced in VHDL design 设计中心 Types defined in Standard Package ? Type BIT – 2 logic value system (‘0’, ‘1’) signal a_temp : bit; – BIT_VECTOR array of bits signal temp : bit_vector(3 downto 0); signal temp : bit_vector(0 to 3) ; ? Type BOOLEAN – (false, true) ? Integer – Positive and negative values in decimal signal int_tmp : integer; --32 bit number signal int_tmp1 : integer range 0 to 255; --8 bit number Note: Standard package has other types 设计中心 LIBRARY IEEE; ? Contains the following packages: std_logic_1164 std_logic types & related functions std_logic_arith arithmetic functions std_logic_signed signed arithmetic functions std_logic_unsigned unsigned arithmetic functions 设计中心 Types defined in std_logic_1164 Package Type STD_LOGIC – 9 logic value system (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’) ? ‘W’, ‘L’, ‘H” weak values (Not supported by Synthesis) ? ‘X’ - used for unknown ? ‘Z’ - (not ‘z’) used for tri-state ? ‘-’ Don’t Care – Resolved type: supports signals with multiple drives. Type STD_ULOGIC – Same 9 value system as STD_LOGIC – Unresolved type: Does not support multiple signal drives. Error will occur. 设计中心 IEEE库的包集合内容 包集合 STD_LOGIC_1164 STD_LOGIC_ARITH STD_LOGIC_UNSIGNED 包 含 内 容 STD_LOGIC STD_ULOGIC STD_LOGIC_VECTOR Rising_edge Falling_edge To_STDLOGICVECTOR(A) To_BITVECTOR(A) To_STDLOGIC(A) TO_BIT(A) And, or, … … +, -, *, ABS, <, <=, >, >=, =, /=, SHL Conv_STD_LOGIC_V ECTOR(A,位长) Conv_INTEGER(A) Conv_INTEGER(A) 设计中心 元件配置（configuration） p.73~p.81 设计中心 作业