设计中心 电子设计自动化技术 教师：李平教授（博导） Email: pli@uestc.edu.cn Tel: 83201794 设计中心 电子设计自动化技术 第五章 设计中心 本章要点 设计中心 What is VHDL ? Very high speed integrated circuit Hardware Description Language (VHDL) – is an industry standard hardware description language – description the hardware in language instead of graphic ? easy to modify ? easy to maintain – very good for ? complex combinational logic – BCD to 7 Segment converter – address decoding ? state machine ? more than you want…….. 设计中心 VHDL描述的总体结构 Wait语句 ——later… --IF语句 - - case语句 --for循环语句 --while循环语句 -- conditional signal assignment -- selected signal assignment -- Component instantiations 设计中心 VHDL的三大要点 ? VHDL程序的基本结构 ? Signal与 Variable的比较 ? 并行语句（Concurrent Statement） 与进程语句（ Process Statement） 设计中心 Learning VHDL must learn What is Combinatorial Logic ? What is Sequential Logic ? What is Concurrent Statement What is Process Statement 设计中心 Combinatorial Logic ? Combinatorial Logic if – Outputs at a specified time are a function only of the inputs at that time ? e.g. decoders, multiplexers and adders Output change instantly when input change 设计中心 Sequential Logic ? Sequential Logic if – Outputs at a specified time are a function of the inputs at that time and at all preceding times – All sequential circuits must include one or more registers ? e.g. State Machine, Counters, Shift Register and Controllers Outputs depends on inputs and previous output Register is used to hold the previous value 设计中心 ? Now everyone should know what is – Combinational Logic – Sequential Logic Q : Then how about Concurrent or Process Statement ? What is it ? 设计中心 Concurrent Statement ? All the Concurrent Statement is executed in parallel ? Concurrent Statement does not care the position within the coding ? Concurrent Statement is : OUTPUT depends on INPUT only 设计中心 Entity test1 Is Port ( a, b : in bit; c, d : out bit); end test1; architecture test1_a of test1 is begin c <= a and b; d <= a or b; end test1_a; Entity test1 Is Port ( a, b : in bit; c, d : out bit); end test1; architecture test1_a of test1 is begin d <= a or b; c <= a and b; end test1_a; This two excute in parallel Does not care the position within the coding Output depends on Input only without any conditional constraint 设计中心 THE SAME C = A and B D = A OR B c <= a and b; d <= a or b; d <= a or b; c <= a and b; 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 1 1 1 设计中心 Process Statement ? All the Process Statement is executed in parallel ? Within the Process Statement, the coding is execute in sequential ? Process Statement is : OUTPUT depends on INPUT with Sensitivity List to control the event happen 设计中心 进程语句一般格式 [进程标号:] PROCESS [(敏感信号表)][IS] 〈说明〉； BEGIN 〈顺序语句〉 ； END PROCESS ； ?PROCESS 是进程语句的标示符， PROCESS前可以加进程标号，也可以 没有标号。 ?进程内部〈说明〉部分用于定义本 进程所需的局部数据环境，在这里 可以说明数据类型、子程序和变量 ， 在此说明区说明的变量，仅在当前 进程内可对其进行读/写。 ?BEGIN以后的〈顺序语句〉为进程 的执行语句部分。 设计中心 Entity test1 is Port ( clk, d1, d2 : in bit; q1, q2 : out bit); end test1; architecture test1_body of test1 is begin Process (clk, d1) begin if (clk’event and clk = ‘1’) then q1 <= d1; end if; end process; Process (clk, d2) begin if (clk’event and clk= ‘1’) then q2 <= d2; end if; end process; end test1_body; Entity test1 is Port ( clk, d1, d2 : in bit; q1, q2 : out bit); end test1; architecture test1_body of test1 is begin Process (clk, d2) begin if (clk’event and clk = ‘1’) then q2 <= d2; end if; end process; Process (clk, d1) begin if (clk’event and clk= ‘1’) then q1 <= d1; end if; end process; end test1_body; This two processes execute in parallel The coding is execute in sequential within the process The output depends on input with conditional constraint 设计中心 The two process statement execute in parallel 设计中心 ? Now, I know what is – combinational logic – sequential logic – concurrent statement – process statement Q : What is the usage of this in VHDL ? A : Engineer can use the mixture of combinational logic, sequential logic, concurrent statement and process statement to do the design 设计中心 How to ... ? ? Now I know what is Combinational Logic but Q : How to implement of Combinational Logic in VHDL? ? Combinational Logic can be implemented by – Concurrent Signal Assignment Statements – Process Statement that describe purely combinational behavior i.e. behavior that does not depends on any CLOCK EDGE 设计中心 Concurrent Statements for Combinational Logic 设计中心 Concurrent Statements ? There are several different kinds of Concurrent Statements – (1) Simple Signal Assignments – (2) Conditional Signal Assignments – (3) Selected Signal Assignments 设计中心 Putting it all together 设计中心 (1) Simple Signal Assignment ? This kind of statements are executed in Parallel Entity test1 is port ( a, b, e : in bit; c, d : out bit); end test1; architecture test1_body of test1 is begin c <= a and b; d <= e; end test1_body; 设计中心 What kind of logic support ?AND ?NAND ?OR ?NOR ?XOR ?NOT ? more ....... 设计中心 I want 5 Input AND Gate Q :AND is only a two input, if I want more input, what can I do ? A : It is easy, we are due with Language not Graphic Entity test1 is port ( a, b, c, d, e : in bit; f : out bit); end test1; architecture test1_body of test1 is begin f <= a and b and c and d and e; end test1_body; 设计中心 (2) Conditional Signal Assignments ? The output get the value when the condition is true – e.g. 2 to 1 multiplexer Entity test1 is port (in1, in2, sel : in bit; d : out bit); end test1; architecture test1_body of test1 is begin d <= in1 WHEN sel = ‘0’ ELSE in2; end test1_body; 设计中心 If I want more -- 4 to 1 Mux ? Once again, you are due with Language not Graphic, so it is easy Entity test1 is port (in1, in2, in3, in4 : in bit; sel1, sel2 : in bit; d : out bit); end test1; architecture test1_body of test1 is begin d <= in1 WHEN sel1 = ‘0’ and sel2 = ‘0’ ELSE in2 WHEN sel1 = ‘0’ and sel2 = ‘1’ ELSE in3 WHEN sel1 = ‘1’ and sel2 = ‘0’ ELSE in4; end test1_body; 设计中心 (3) Select Signal Assignments ? The output get value when matching with the selected item Entity test1 is port (a, b: in bit; sel : in bit; c : out bit); end test1; architecture test1_body of test1 is begin WITH sel SELECT c <= a WHEN ‘1’, --逗号 b WHEN ‘0’; --分号 end test1_body; 设计中心 If I want more choice --- ? It is easy Entity test1 is port (in1, in2, in3, in4 : in bit; sel : in integer; out1 : out bit); end test1; architecture test1_body of test1 is begin with sel select out1 <= in1 when 0 , in2 when 1 , in3 when 2 , in4 when 3; end test1_body; 设计中心 Review ? Concurrent Statement for – combinational logic (without Flip-flop circuit) ? eg. decoder, multiplexer, multiplier, adder ? Understand the usage of the – Concurrent Statement ? for Combinational Logic – simple signal assignment statement – conditional signal assignment statement – selected signal assignment statement 设计中心 作业