电子设计自动化 电子设计自动化 授课教师：何 授课教师：何 旭 旭 第六章 第六章 全局考虑 全局考虑 第一节范围和可视性 第二节重载 第一节范围和可视性 信号和变量的作用域，从其声明的 地方到其所在描述单元的结束。 ARCHITECTURE overall OF test IS 例1 SIGNAL first_sig: bit; BEGIN process1: PROCESS VARIABLE process_sig: bit; PROCEDURE inside (VARIABLE data: OUT bit); PROCEDURE inside (VARIABLE data: OUT bit) IS VARIABLE procedure_var: bit; BEGIN …… END inside; BEGIN inside (in_data); …… END PROCESS process1; -- part of architecture body END overall; ARCHITECTURE overall OF test IS 例2 SIGNAL first_sig : bit; BEGIN process1: PROCESS VARIABLE: process_sig: bit; VARIABLE：first_sig : bit; PROCEDURE inside (VARIABLE data: OUT bit); PROCEDURE inside (VARIABLE data: OUT bit) IS VARIABLE procedure_var: bit; BEGIN …… END inside; ARCHITECTURE overall OF test IS 例2 SIGNAL first_sig : bit; BEGIN 隐藏 process1: PROCESS VARIABLE: process_sig: bit; VARIABLE：first_sig : bit; PROCEDURE inside (VARIABLE data: OUT bit); PROCEDURE inside (VARIABLE data: OUT bit) IS VARIABLE procedure_var: bit; BEGIN …… END inside; BEGIN inside (in_data); first_sig := process_sig; overall.first_sig <= first_sig ; END PROCESS process1; -- part of architecture body END overall; BEGIN inside (in_data); first_sig := process_sig; overall.first_sig <= first_sig ; END PROCESS process1; -- part of architecture body END overall; 第二节重载 重用预定义名 一、重载枚举字 枚举定义中有交叠 例： TYPE wire_color IS (green, black, red); TYPE traffic_lt IS (red, yellow, green, flashing); 一、重载枚举字 枚举定义中有交叠 例： TYPE wire_color IS (green, black, red); TYPE traffic_lt IS (red, yellow, green, flashing); ____ ___ __ ____ ARCHITECTURE physical OF hardware IS SIGNAL sig1 : bit; TYPE wire_color is (green, black, red); TYPE traffic_lt IS (red, yellow, green, flashing); BEGIN example: PROCESS (sig1) VARIABLE pwr_hot, pwr_neutral : wire_color; VARIABLE top_lt, middle_lt, bottom_lt : traffic_lt; BEGIN pwr_hot := red; top_lt := red; END PROCESS example; END hardware; 二、重载子程序 例： PACKAGE my_qsim_logic IS TYPE my_qsim_state IS (‘X’, ‘0’, ‘1’, ‘Z’); SUBTYPE my_qsim_value IS my_qsim_state RANGE ‘X’ TO ‘1’; TYPE my_qsim_12state IS (SXR, SXZ, SXS, SXI, S0R, S0Z, S0S, S0I, S1R, S1Z, S1S, S1I); TYPE my_qsim_strength IS (‘Z’, ‘R’, ‘S’, ‘I’); TYPE my_qsim_state_vector IS ARRAY (positive RANGE<>) OF my_qsim_state; TYPE my_qsim_value_vector IS ARRAY (positive RANGE<>) OF my_qsim_value; TYPE my_qsim_12state_vector IS ARRAY (natural RANGE<>) OF my_qsim_12state; TYPE my_qsim_strength_vector IS ARRAY (natural RANGE<>) OF my_qsim_strength; FUNCTION my_to_qsim_12state (val : my_qsim_value; str : my_qsim_strength) RETURN my_qsim_12state; FUNCTION my_to_qsim_12state (val : my_qsim_state) RETURN my_qsim_12state; FUNCTION my_to_qsim_12state (val : my_qsim_value_vector; str : my_qsim_strength_vector) RETURN my_qsim_12state_vector; FUNCTION my_to_qsim_12state (val : my_qsim_state_vector) RETURN my_qsim_12state_vector; END my_qsim_logic; 例： example2 : PROCESS (sig1) USE my_lib. My_qsim_logic. ALL; CONSTANT Sig_strngth : my_qsim_strength := ‘S’; VARIABLE var1 : my_qsim_value := ‘0’; VARIABLE var2 : my_qsim_state := ‘Z’; VARIABLE var3 : bit := ‘0’; VARIABLE reg_in_a : my_qsim_12state; BEGIN reg_in_a := my_to_qsim_12state (var1, Sig_strngth); reg_in_a := my_to_qsim_12state (var2); reg_in_a := my_to_qsim_12state (var3, Sig_strngth); END PROCESS example2; 三、重载算子 预定义算子优先级列表(从上到下） 算子类双边算子单边算子 杂项 ** Abs not 乘法 * / mod rem 符号 + - 加法 + - & 关系算子 = /= < <= > >= 逻辑算子 And or nand nor xor 算子重载与其它重载稍有不同，符号“=”需要用 双引号括起来。 例： PACKAGE my_qsim_state IS (‘X’, ‘0’, ‘1’, ‘Z’); TYPE my_qsim_state IS (‘X’, ‘0’, ‘1’, ‘Z’); FUNCTION “=” (l, r : my_qsim_state) RETURN my_qsim_state; FUNCTION “=” (l, r : my_qsim_state) RETURN boolean; END my_qsim_logic; exam3: PROCESS (sig1) USE my_lib. qsim_logic. ALL; VARIABLE var1 : my_qsim_state := ‘0’; VARIABLE var2 : my_qsim_state := ‘1’; VARIABLE result1 : my_qsim_state; VARIABLE result2 : boolean; BEGIN result1 := (var1 = var2); result2 := (var1 = var2); var2 := ‘0’; result1 := (var1 = var2); result2 := (var1 = var2); sig1 <= result1; END PROCESS exam3; “=”运算也可写为: result1 := “=” (var1, var2);