设计中心 电子设计自动化技术 教师：李平教授（博导） Email: pli@uestc.edu.cn Tel: 83201794 设计中心 补充内容 设计中心 基本术语 ?EDA（Electronic Design Automation） ? ASIC（Application Specific Integrated Circuit） ?FPGA（Field Programmable Gate-Array） ?CPLD（Complex Programmable Logic Device） ?SOC（System On a Chip） ?IP（Intellectual Property） ?ISP（In-System Programmable） 设计中心 基本术语 ? Front-end（前端） ? Back-end（后端） ? PCB（Printed Circuit Board） ? MPU（MicroProcessor Unit） ? DSP（Digital Signal Processor/Processing） ? ROM （Read Only Memory） ? SRAM （Static Random Access Memory） ? EEPROM （Electrically Erasable Programmable ROM） 设计中心 VHDL的三大要点 ? VHDL程序的基本结构 ? Signal与Variable的比较 ?并行语句（Concurrent Statement） 与进程语句（Process Statement） 设计中心 Signal vs Variable 设计中心 Signal vs Variable ? Signal Assignment (<=) – receive the assign value after a period of time ? Variable Assignment – happens immediately when the statement is executed, no delay (: =) 设计中心 Example LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux4 IS PORT (i0, i1, i2, i3, a, b : IN STD_LOGIC; q : OUT STD_LOGIC); END mux4; ARCHITECTURE body_mux4 OF mux4 IS signal muxval : integer; BEGIN process(i0,i1,i2,i3,a,b) begin muxval <= 0; if (a = '1') then muxval <= muxval + 1; end if; if (b = '1') then muxval <= muxval + 2; end if; case muxval is when 0 => q <= i0; when 1 => q <= i1; when 2 => q <= i2; when 3 => q <= i3; when others => null; end case; end process; END body_mux4; Why ???? 设计中心 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux4 IS PORT (i0, i1, i2, i3, a, b : IN STD_LOGIC; q : OUT STD_LOGIC); END mux4; ARCHITECTURE body_mux4 OF mux4 IS BEGIN process(i0,i1,i2,i3,a,b) variable muxval : integer; begin muxval := 0; if (a = '1') then muxval := muxval + 1; end if; if (b = '1') then muxval := muxval + 2; end if; case muxval is when 0 => q <= i0; when 1 => q <= i1; when 2 => q <= i2; when 3 => q <= i3; when others => null; end case; end process; END body_mux4; 设计中心 Key points to remember ? Function – Variables represent local storage ? Variables is updated immediately – the updated value can be used later in the model for further computations – Signals represent circuit interconnect ? Place of Declare – Variables : allow within Process structure – Signal : allow within Architecture structure 设计中心 ? Visible – Variable : only with the process – Signal : if define within Entity - visible within the whole Entity if define within Architecture - visible within the whole Architecture ? Make sure that you must have the correct Signal or Variable declaration 设计中心 Data Type VHDL is a strongly DATA TYPE ORIENT LANGUAGE 设计中心 Type Data ? VHDL is a very rigid Type Data Oriented Language Q : What is it means? A : Different type can not do any assignment e.g. a : in belongs to TYPE A b : out belongs to TYPE B b <= a; ----- ERROR because a and b is belonging to different types Q : Why VHDL does not allow this ? A : This is a kind of protection, so engineer will not do different TYPE assignment by mistake 设计中心 Q : Is that any solution for this ? A : VHDL is a powerful language, so no doubt about it, solution is available. Q : How ? A : It is easy ........... Wake up, don’t sleep 设计中心 VHDL Data Type ? Data Type in VHDL – Built In Data Type ? designer can free to use it, it comes with VHDL – Customer Create Data Type ? designer need to create his own Data Type 设计中心 Built In Data Type ? There are some commonly used built in Data Type available –BIT – STD_LOGIC –INTEGER ? What is the different ? ? How to use it ? 设计中心 BIT ? Example : a : in BIT; ? BIT can only have two value – ‘0’ and ‘1’ Entity example is Port (a : in bit; b, c, d, e, f : out bit); end example; Architecture example_body of example is begin b <= a; c <= ‘1’; d <= ‘0’; e <= ‘Z’; f <= ‘X’; end example_body; OK! a and b are the same type BIT OK! c and d can take value ‘1’or ‘0’ ERROR! ‘Z’ and ‘X’ is not allow in BIT type 设计中心 STD_LOGIC ? Example : a : in STD_LOGIC; ? STD_LOGIC can have value – ‘0’, ‘1’, ‘X’, ‘Z’ – ‘X’ - - used for unknown – ‘Z’ - - high impedance used for tri-state (capital Z, not z) ? There is some trick to use STD_LOGIC 设计中心 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; Entity example is port ( a : in STD_LOGIC; b, c, d, e, f : out STD_LOGIC); end example; Architecture example_body of example is begin b <= a; c <= ‘1’; d <= ‘0’; e <= ‘X’; f < = ‘Z’; end example_body; Must have this statement use before any ENTITY Define a and b are STD_LOGIC type OK! a and b are the same type OK! ‘0’, ‘1’, ‘X’ and ‘Z’ are valid STD_LOGIC data type 设计中心 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; Entity example is port ( a : in STD_LOGIC; b, c : out STD_LOGIC); end example; Architecture example_body of example is signal VCC : std_logic := ‘1’; signal GND : std_logic := ‘0’; begin process (a) if (a = ‘1’) then b <= VCC; c <= GND; else B <= GND; c <= VCC; end if; end process; end example_body; Mo re f o r ST D _ L O G I C 设计中心 INTEGER ? Example : a : in integer; b : in integer range 0 to 15; ? INTEGER can take any integer value – Negative, Zero, Positive ? e.g. -7, 0, 100 Entity test is port ( a : in integer; b,c : out integer); end test; architecture test_body of test is begin b <= a; c <= 8; end test_body; OK! a and b are the same type OK! c can accept Integer value 设计中心 Something more on INTEGER data type Q : How many bit will be use for a : in integer ? A : It depend on the VHDL compiler. Altera VHDL compiler will take 32 bits Q : Can I have more control on the INTEGER DATA TYPE ? A : Yes. You can control the RANGE of the INTEGER a : in integer range 0 to 15; b : in integer range -7 to 0; c : out integer range -10 to 10; a can accept 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 b can accept -7, -6, -5, -4, -3, -2, -1, 0 only c can accept -10, -9, -8.....0.....1, 2, 3, ......10 设计中心 ? How many bits use for 0 to 15 ? ? How many bits use for -7 to 0 ? ? How many bits use for -10 to 10 ? 4 bits - Why ? (have 16 value) 3 bits - Why ? (have 8 value) 5 bits - Why ? (have 32 value) 设计中心 Bus Implementation ? VHDL offers vector types to implement buses ? Common vector types are – BIT_VECTOR – STD_LOGIC_VECTOR ? Example of Bus Implementation a : in bit; b : out std_logic; BIT OPERATION a : in bit_vector(7 downto 0); b : out std_logic_vector (0 to 3); BUS OPERATION Define the size of the vector (how many bits) 设计中心 INTEGER VECTOR Integer a : in integer; Bus Integer ? a : in integer_vector ? Note : there is no INTEGER_VECTOR ? But you can create your own INTEGER VECTOR – VHDL allow you to create your own DATA TYPE ?How ? ? Later......... 设计中心 Bus Assignment ? a : out bit_vector(3 downto 0) – a <= “1011”; – a(2) <= ‘0’; – a(0 to 1) <= “10” – a(3 downto 1) <= “100” – a(3 downto 0) <= x”A” – a <= (others=> ‘1’) a(0) <= ‘1’ a(1) <= ‘1’ a(2) <= ‘0’ a(3) <= ‘1’ a(2) <= ‘0’ a(0) <= ‘1’ a(1) <= ‘0’ a(3) <= ‘1’ a(2) <= ‘0’ a(1) <= ‘0’ a(3) <= ‘1’ a(2) <= ‘1’ a(1) <= ‘1’ a(0) <= ‘1’ a(3) <= ‘1’ a(2) <= ‘0’ a(1) <= ‘1’ a(0) <= ‘0’ 设计中心 Different Data Type Assignment a : in std_logic_vector(3 downto 0); b : in integer range 0 to 15; c : out std_logic_vector(3 downto 0); d : out integer range 0 to 15; c <= a; d <= b; c <= b; d <= a; OK because c and a are the same std_logic type OK because d and b are the same integer type ERROR because c and b are different type ERROR because d and a are different type 设计中心 作业