设计中心 电子设计自动化技术 教师：李平教授（博导） Email: pli@uestc.edu.cn Tel: 83201794 设计中心 电子设计自动化技术 补充内容 Model Referencing of Library/Package Implied Process and Explicit Process Combinatorial Process and Sequential Process 设计中心 VHDL ? VHSIC (Very High Speed Integrated Circuit) ? Hardware ? Description ? Language 设计中心 VHDL描述的总体结构 设计中心 Behavior Modeling ? Only the functionality of the circuit, no structure ? No specific hardware intent ? For the purpose of synthesis, as well as simulation IN1，…，IN n OUT1，…，OUT n IF in1 THEN FOR j IN high DOWNTO low LOOP shft(j) := shft(j); END LOOP; out1 <= shft AFTER 5ns 设计中心 Structural Modeling ? Functionality and structure of the circuit ? Call out the specific hardware ? For the purpose of synthesis Lower-level Component1 Lower-level Component2 IN1 INn OUT1 OUTn Higher-level Component 设计中心 Model Referencing of Library/Package 设计中心 VHDL Operators Operator Type Operator Name/Symbol Logical and or nand nor xor xnor(93) Relational = /= < <= > >= Adding + - & Signing + - Multiplying * / mod rem Miscellaneous ** abs not 设计中心 VHDL Operators ? VHDL defines Arithmetic & Boolean functions only for built-in data types (defined in Standard package) – Arithmetic operators such as +, -, <, >, <=, >= are defined only for INTEGER type. – Boolean operators such as AND, OR, NOT are defined only for BIT type. 设计中心 Recall: VHDL implicit library (built-in) – Library STD ? Types defined in the Standard package: – BIT, BOOLEAN, INTEGER Note: Items in this package do not need to be referenced, they are implied. Q: Library IEEE do need to be referenced, whenever? 设计中心 Libraries LIBRARY IEEE; – Contains the following packages: ? std_logic_1164 (std_logic types & related functions) ? std_logic_arith (arithmetic functions) ? std_logic_signed (signed arithmetic functions) ? std_logic_unsigned (unsigned arithmetic functions) 设计中心 IEEE库的包集合内容 包集合 STD_LOGIC_1164 STD_LOGIC_ARITH STD_LOGIC_UNSIGNED 包 含 内 容 STD_LOGIC STD_ULOGIC STD_LOGIC_VECTOR Rising_edge Falling_edge To_STDLOGICVECTOR(A) To_BITVECTOR(A) To_STDLOGIC(A) TO_BIT(A) And, or, … … +, -, *, ABS, <, <=, >, >=, =, /=, SHL Conv_STD_LOGIC_V ECTOR(A,位长) Conv_INTEGER(A) Conv_INTEGER(A) 设计中心 Arithmetic Function ENTITY opr IS PORT ( a : IN INTEGER RANGE 0 TO 16; b : IN INTEGER RANGE 0 TO 16; sum : OUT INTEGER RANGE 0 TO 32); END opr; ARCHITECTURE example OF opr IS BEGIN adder_body:PROCESS (a, b) BEGIN sum <= a + b; END PROCESS adder_body; END example; The VHDL compiler can understand this operation because an arithmetic operation is defined for the built-in data type INTEGER 设计中心 Operator Overloading ? How do you use Arithmetic & Boolean functions with other data types? – Operator Overloading - defining Arithmetic & Boolean functions with other data types. 设计中心 Operator Overloading Function/Package ? Packages that define these operator overloading functions can be found in the LIBRARY IEEE. ? For example, the package std_logic_unsigned defines some of the following functions package std_logic_unsigned is function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR; function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR; function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR; function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR; function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR 设计中心 Use of Operator Overloading LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY overload IS PORT ( a : IN STD_LOGIC_VECTOR (3 downto 0); b : IN STD_LOGIC_VECTOR (3 downto 0); sum : OUT STD_LOGIC_VECTOR (4 downto 0)); END overload; Include these statements at the beginning of a design file 设计中心 ARCHITECTURE example OF overload IS BEGIN PROCESS (a, b) BEGIN sum <= a + b; END PROCESS; END example; This allows us to perform arithmetic on non-built-in data types. 设计中心 Implied Process and Explicit Process 设计中心 Conditional Signal Assignments Example: q <= a WHEN sela = ‘1’ ELSE b WHEN selb = ‘1’ ELSE c; implied process sela c b a selb q 设计中心 Selected Signal Assignments Example: WITH sel SELECT q <= a WHEN “00”, b WHEN “01”, c WHEN “10”, d WHEN OTHERS; implied process sel a b c d 2 q 设计中心 设计中心 Sequential Statements ? IF-THEN statement ? CASE statement ? Looping Statements 设计中心 If-Then Statements Format: IF <condition1> THEN {sequence of statement(s)} ELSIF <condition2> THEN {sequence of statement(s)} . . ELSE {sequence of statement(s)} END IF; 设计中心 If-Then Statements (continue) Example: PROCESS(sela, selb, a, b, c) BEGIN IF sela=‘1’ THEN q <= a; ELSIF selb=‘1’ THEN q <= b; ELSE q <= c; END IF; END PROCESS; sela c b a selb q 设计中心 q <= a WHEN sela = ‘1’ ELSE b WHEN selb = ‘1’ ELSE c; If-Then Statements (continue) ? Similar to Conditional Signal Assignment Implied Process Explicit Process PROCESS(sela, selb, a, b, c) BEGIN IF sela=‘1’ THEN q <= a; ELSIF selb=‘1’ THEN q <= b; ELSE q <= c; END IF; END PROCESS; sela c b a selb q 设计中心 Case Statement Format: CASE {expression} IS WHEN <condition1> => {sequence of statements} WHEN <condition2> => {sequence of statements} …… WHEN OTHERS => -- (optional) {sequence of statements} END CASE; 设计中心 Case Statement (continue) Example: PROCESS(sel, a, b, c, d) BEGIN CASE sel IS WHEN “00” => q <= a; WHEN “01” => q <= b; WHEN “10” => q <= c; WHEN OTHERS => q <= d; END CASE; END PROCESS; sel a b c d 2 q 设计中心 If-Then Statements (continue) ? Similar to Selected Signal Assignment Implied Process Explicit Process PROCESS(sela, selb, a, b, c) BEGIN CASE sel IS WHEN “00” => q <= a; WHEN “01” => q <= b; WHEN “10” => q <= c; WHEN OTHERS => q <= d; END CASE; END PROCESS; WITH sel SELECT q <= a WHEN “00”, b WHEN “01”, c WHEN “10”, d WHEN OTHERS; sel a b c d 2 q 设计中心 If-Then Statements ? Conditions are evaluated in order from top to bottom – Prioritization ? The first condition, that is true, causes the corresponding sequence of statements to be executed. ? If all conditions are false, then the sequence of statements associated with the “ELSE” clause is evaluated. 设计中心 Case Statement ? Conditions are evaluated at once – No Prioritization ? All possible conditions must be considered ? WHEN OTHERS clause evaluates all other possible conditions that are not specifically stated. 设计中心 Sequential LOOPS ? Infinite Loop – Loops infinitely unless EXIT statement exists ? While Loop – Conditional test to end loop ? FOR Loop – Iteration Loop [loop_label] LOOP --sequential statement EXIT loop_label ; END LOOP; WHILE <condition> LOOP --sequential statements END LOOP; FOR <identifier> IN <range> LOOP --sequential statements END LOOP; 设计中心 LAB 4-bit Left Shifter FOR LOOP using a Variable 设计中心 d_ind_out shft_lft 7 6 5 4 3 2 1 0 设计中心 LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY shift4 IS PORT ( shft_lft : in std_logic; d_in : in std_logic_vector(3 downto 0); q_out : out std_logic_vector(7 downto 0)); END shift4; - - to be continue 设计中心 ARCHITECTURE logic OF shift4 IS BEGIN PROCESS (d_in, shft_lft) VARIABLE shft_var : std_logic_vector (7 DOWNTO 0); BEGIN shft_var(7 downto 4) := "0000"; shft_var(3 downto 0) := d_in; - - to be continue Variable Declaration Variable is initialized 设计中心 IF shft_lft = '1' THEN FOR i IN 7 DOWNTO 4 LOOP shft_var(i) := shft_var(i-4); END LOOP; shft_var(3 downto 0) := “0000”; ELSE shft_var := shft_var; END IF; q_out <= shft_var; END PROCESS; END logic; Enables shift-left i is the index for the FOR LOOP and does not need to be declared Shifts left by 4 Fills the LSBs with zeros No shifting Variable is assigned to a Signal before the end of the Process to synthesize to a piece of hardware 设计中心 Combinatorial Process and Sequential Process 设计中心 Two Types of Process Statements ? Combinatorial Process – Sensitive to all inputs used in the combinatorial logic Example: PROCESS(a, b, sel) ? Sequential Process – Sensitive to a clock or/and control signals Example: PROCESS(clr, clk) sel b a q d clk clr q D Q ENA CLRN 设计中心 Recall: Combinatorial Logic ? Combinatorial Logic if – Outputs at a specified time are a function only of the inputs at that time ? e.g. decoders, multiplexers and adders Output change instantly when input change 设计中心 Recall: Sequential Logic ? Sequential Logic if – Outputs at a specified time are a function of the inputs at that time and at all preceding times – All sequential circuits must include one or more registers ? e.g. State Machine, Counters, Shift Register and Controllers Outputs depends on inputs and previous output Register is used to hold the previous value 设计中心 Example of Sequential Process 设计中心 How Many Registers? ENTITY reg1 IS PORT ( d, clk : in BIT; q : out BIT); END reg1; ARCHITECTURE reg1 OF reg1 IS SIGNAL a, b : BIT; BEGIN PROCESS (clk) BEGIN IF rising_edge(clk) THEN a <= d; b <= a; q <= b; END IF; END PROCESS; END reg1; rising_edge – IEEE function that is defined in the std_logic_1164 package – specifies that the signal value must be 0 to 1 – X, Z to 1 transition is not allowed 设计中心 ? clk’event and clk=‘1’ – clk is the signal name (any name) – ‘event is a VHDL attribute, specifying that there needs to be a change in signal value – event is a change in value: from 0 to 1; or from X to 1, etc – clk=‘1’ means positive-edge triggered RECALL 设计中心 How Many Registers? ? Signal Assignments inside the IF-THEN statement that checks the clock condition infer registers. D Q ENA CLRN D Q ENA CLRN D Q ENA CLRN d ba q clk clk clk 设计中心 How Many Registers? ENTITY reg1 IS PORT ( d, clk : in BIT; q : out BIT); END reg1; ARCHITECTURE reg1 OF reg1 IS SIGNAL a, b : BIT; BEGIN PROCESS (clk) BEGIN IF rising_edge(clk) THEN a <= d; b <= a; END IF; END PROCESS; q <= b; END reg1; Signal assignment moved 设计中心 How Many Registers? ? b to q assignment is no longer edge-sensitive because it is not inside the IF-THEN statement that checks the clock condition D Q ENA CLRN D Q ENA CLRN d a q clk clk b 设计中心 How Many Registers? ENTITY reg1 IS PORT ( d, clk : in BIT; q : out BIT); END reg1; ARCHITECTURE reg1 OF reg1 IS BEGIN PROCESS (clk) VARIABLE a, b : BIT; BEGIN IF rising_edge(clk) THEN a := d; b := a; q <= b; END IF; END PROCESS; END reg1; Signals changed to variables 设计中心 How Many Registers? ? Variable assignments are updated immediately ? Signal assignments are updated on clock edge D Q ENA CLRN dq clk ab 设计中心 作业