第 4章 电子系统设计实践（一）
<EDA技术 与应用 > 课程讲义
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合肥工业大学 彭良清
上一章
本章内容
一,4位加法计数器设计
二,8位数码管显示扫描电路设计
三,13分频器电路设计
一,4位加法计数器设计（一）
1,--LIBARY IEEE;
2,--USE IEEE.STD_LOGIC_1164.ALL;
3,ENTITY CNT4 IS
4,PORT ( CLK, IN BIT;
5,Q, BUFFER INTEGER RANGE 15 DOWNTO 0
6,);
7,END ENTITY CNT4;
8,ARCHITECTURE bhv OF CNT4 IS
9,BEGIN
10,PROCESS(CLK)
11,BEGIN
12,IF CLK'EVENT AMD CLK = '1' THEN
13,Q <= Q + 1;
14,END IF;
15,END PROCESS;
16,END ARCHITECTURE bhv;
参见：
p108_ex5_1_CNT4
4位加法计数器设计（一）,图
4位加法计数器设计（二）
1,LIBARY IEEE;
2,USE IEEE.STD_LOGIC_1164.ALL;
3,USE IEEE.STD_LOGIC_UNSIGNED.ALL;
4,ENTITY CNT402 IS
5,PORT ( CLK, IN STD_LOGIC;
6,Q, OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
7,);
8,END ENTITY CNT402;
9,ARCHITECTURE bhv OF CNT402 IS
10,SIGNAL Q1, STD_LOGIC_VECTOR(3 DOWNTO 0);
11,BEGIN
12,PROCESS(CLK)
13,BEGIN
14,IF CLK'EVENT AMD CLK = '1' THEN
15,Q1 <= Q1 + 1;
16,END IF;
17,-- Q <= Q1;
18,END PROCESS;
19.
20,Q <= Q1;
21,END ARCHITECTURE bhv;
参见：
p110_ex5_2_CNT402
4位加法计数器设计（二）,图
4位加法计数器
设计（三 ）
1,LIBARY IEEE;
2,USE IEEE.STD_LOGIC_1164.ALL;
3,USE IEEE.STD_LOGIC_UNSIGNED.ALL;
4,ENTITY CNT10 IS
5,PORT ( CLK,RST,EN, IN STD_LOGIC;
6,CQ, OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
7,COUT, OUT STD_LOGIC
8,);
9,END ENTITY CNT10;
10,ARCHITECTURE bhv OF CNT10 IS
11,BEGIN
12,PROCESS(CLK,RST,EN)
13.
14,VARIABLE CQI,STD_LOGIC_VECTOR( 3 DOWNTO 0);
15,BEGIN
16,IF RST = '1' THEN
17,CQI,= (OTHERS >='0' );
18,ELSIF CLK'EVENT AMD CLK = '1' THEN
19,IF EN = '1' THEN
20,IF CQI < 9 THEN
21,CQI,= CQI + 1;
22,ELSE
23,CQI,= (OTHERS >='0' );
24,END IF;
25,END IF;
26,END IF;
27.
28,IF CQI = 9 THEN
29,COUT <= '1' ;
30,ELSE
31,COUT <= '0';
32,END IF;
33,CQ <= CQI
34.
35,END PROCESS;
36.
37,END ARCHITECTURE bhv;
具有异步
复位 (RST)
时钟使能 (EN)
参见,p113_ex5_3_CNT10
4位加法计数器设计（三）,图
三,8位数码管显示扫描电路设计
二,8位数码管显示扫描电路设计
K1…K8 为数码管的位控信号，对应 FPGA
的 PIO41,40,39,38,37,36,35,34a…g 为数码管的段控信号，对应 FPGA的 PIO49,48,47,46,45,44,43,42
实验
电路
1,LIBRARY IEEE;
2,USE IEEE.STD_LOGIC_1164.ALL;
3,USE IEEE.STD_LOGIC_UNSIGNED.ALL;
4,ENTITY SCAN_LED IS
5,PORT ( CLK, IN STD_LOGIC;
6,SG, OUT STD_LOGIC_VECTOR(6 DOWNTO 0); --段控制信号输出
7,BT, OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );--位控制信号输出
8,END;
9,ARCHITECTURE one OF SCAN_LED IS
10,SIGNAL CNT8, STD_LOGIC_VECTOR(2 DOWNTO 0);
11,SIGNAL A, INTEGER RANGE 0 TO 15;
12,BEGIN
13,P1,PROCESS( CNT8 )
14,BEGIN
15,CASE CNT8 IS
16,WHEN "000" => BT <= "00000001" ; A <= 1 ;
17,WHEN "001" => BT <= "00000010" ; A <= 3 ;
18,WHEN "010" => BT <= "00000100" ; A <= 5 ;
19,WHEN "011" => BT <= "00001000" ; A <= 7 ;
20,WHEN "100" => BT <= "00010000" ; A <= 9 ;
21,WHEN "101" => BT <= "00100000" ; A <= 11 ;
22,WHEN "110" => BT <= "01000000" ; A <= 13 ;
23,WHEN "111" => BT <= "10000000" ; A <= 15 ;
24,WHEN OTHERS => NULL ;
25,END CASE ;
26,END PROCESS P1;
27,P2,PROCESS(CLK)
28,BEGIN
29,IF CLK'EVENT AND CLK = '1' THEN CNT8 <= CNT8 + 1;
30,END IF;
31,END PROCESS P2 ;
32,P3,PROCESS( A ) --译码电路
33,BEGIN
34,CASE A IS
35,WHEN 0 => SG <= "0111111"; WHEN 1 => SG <= "0000110";
36,WHEN 2 => SG <= "1011011"; WHEN 3 => SG <= "1001111";
37,WHEN 4 => SG <= "1100110"; WHEN 5 => SG <= "1101101";
38,WHEN 6 => SG <= "1111101"; WHEN 7 => SG <= "0000111";
39,WHEN 8 => SG <= "1111111"; WHEN 9 => SG <= "1101111";
40,WHEN 10 => SG <= "1110111"; WHEN 11 => SG <= "1111100";
41,WHEN 12 => SG <= "0111001"; WHEN 13 => SG <= "1011110";
42,WHEN 14 => SG <= "1111001"; WHEN 15 => SG <= "1110001";
43,WHEN OTHERS => NULL ;
44,END CASE ;
45,END PROCESS P3;
46,END;
设计
编码
参见,
p145_ex5_22_SCAN_LED
译码进程
计数进程
位选进程
端口定义
端口定义
1,LIBARY IEEE;
2,USE IEEE.STD_LOGIC_1164.ALL;
3,USE IEEE.STD_LOGIC_UNSIGNED.ALL;
4,ENTITY scan_led IS
5,PORT ( CLK, IN STD_LOGIC;
6,SG, OUT STD_LOGIC_VECTOR ( 6 DOWNTO 0 );
-- segment control
7,BT, OUT STD_LOGIC_VECTOR ( 6 DOWNTO 0 )
-- bit control
8,);
9,END ENTITY scan_led;
位选进程
10,ARCHITECTURE BEHAV OF scan_led IS
11,SGINAL CNT8 STD_LOGIC_VECTOR ( 2 DOWNTO 0 );
12,SIGNAL A, INTEGER RANGE 0 TO 15;
13,BEGIN
14,P1:
15,PROCESS ( CNT8 )
16,BEGIN
17,CASE CNT8 IS
18,WHEN "000" => BT <= "00000001"; A <=1;
19,WHEN "001" => BT <= "00000010"; A <=3;
20,WHEN "010" => BT <= "00000100"; A <=5;
21,WHEN "011" => BT <= "00001000"; A <=7;
22,WHEN "100" => BT <= "00010000"; A <=9;
23,WHEN "101" => BT <= "00100000"; A <=11;
24,WHEN "110" => BT <= "01000000"; A <=13;
25,WHEN "111" => BT <= "10000000"; A <=15;
26,WHEN OTHERS => NULL;
27,END CASE;
28.
29,END PROCESS ledcoding;
计数进程
30,P2:
31,PROCESS ( CLK )
32,BEGIN
33.
34,IF CLK'EVENT AND CLK = '1' THEN
35,CNT8 <= CNT8 + 1;
36,END IF;
37.
38,END PROCESS P2;
译码进程
39,P3:
40,PROCESS ( A )
41,BEGIN
42,CASE A IS
43,WHEN 0 => BT <= "0111111"; -- 0
44,WHEN 1 => BT <= "0000110"; -- 1
45,WHEN 2 => BT <= "1011011"; -- 2
46,WHEN 3 => BT <= "1001111"; -- 3
47,WHEN 4 => BT <= "1100110"; -- 4
48,WHEN 5 => BT <= "1101101"; -- 5
49,WHEN 6 => BT <= "1111101"; -- 6
50,WHEN 7 => BT <= "0000111"; -- 7
51,WHEN 8 => BT <= "1111111"; -- 8
52,WHEN 9 => BT <= "1101111"; -- 9
53,WHEN 10 => BT <= "1110111"; -- A
54,WHEN 11 => BT <= "1111100"; -- B
55,WHEN 12 => BT <= "0111001"; -- C
56,WHEN 13 => BT <= "1011110"; -- D
57,WHEN 14 => BT <= "1111001"; -- E
58,WHEN 15 => BT <= "1110001"; -- F
59,WHEN OTHERS => NULL;
60,END CASE;
61.
62,END PROCESS P3:
63,END ARCHITECTURE BEHAV;
本试验思考
1,LED数码管是共阴极还是共阳极的？
2,修改 P1中的显示数据直接给出方式，增加 8
个 4位锁存器，作为显示数据缓冲器，所有
8个显示数据都必须来自缓冲器。缓冲器的
输入数据可设置为常数量。
3,修改 P1编码，用开关 8个开关控制显示 8位
不同的数据。
二,13分频器电路设计
三,13分频器电路设计
设计要求,
在 4位计数器的基础上实现 13
分频器,输出周期信号的占空
比不作要求,
The end.
以下内容
为
正文的引用，
可不阅读。
返回
STD_LOGIC的取值
1,TYPE std_ulogic IS ( 'U',-- Uninitialized
2,'X',-- Forcing Unknown
3,'0',-- Forcing 0
4,'1',-- Forcing 1
5,'Z',-- High Impedance
6,'W',-- Weak Unknown
7,'L',-- Weak 0
8,'H',-- Weak 1
9,'-' -- Don't care
10,);
返回
详细参见
STD1164.VHD
<EDA技术 与应用 > 课程讲义
下一章
合肥工业大学 彭良清
上一章
本章内容
一,4位加法计数器设计
二,8位数码管显示扫描电路设计
三,13分频器电路设计
一,4位加法计数器设计（一）
1,--LIBARY IEEE;
2,--USE IEEE.STD_LOGIC_1164.ALL;
3,ENTITY CNT4 IS
4,PORT ( CLK, IN BIT;
5,Q, BUFFER INTEGER RANGE 15 DOWNTO 0
6,);
7,END ENTITY CNT4;
8,ARCHITECTURE bhv OF CNT4 IS
9,BEGIN
10,PROCESS(CLK)
11,BEGIN
12,IF CLK'EVENT AMD CLK = '1' THEN
13,Q <= Q + 1;
14,END IF;
15,END PROCESS;
16,END ARCHITECTURE bhv;
参见：
p108_ex5_1_CNT4
4位加法计数器设计（一）,图
4位加法计数器设计（二）
1,LIBARY IEEE;
2,USE IEEE.STD_LOGIC_1164.ALL;
3,USE IEEE.STD_LOGIC_UNSIGNED.ALL;
4,ENTITY CNT402 IS
5,PORT ( CLK, IN STD_LOGIC;
6,Q, OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
7,);
8,END ENTITY CNT402;
9,ARCHITECTURE bhv OF CNT402 IS
10,SIGNAL Q1, STD_LOGIC_VECTOR(3 DOWNTO 0);
11,BEGIN
12,PROCESS(CLK)
13,BEGIN
14,IF CLK'EVENT AMD CLK = '1' THEN
15,Q1 <= Q1 + 1;
16,END IF;
17,-- Q <= Q1;
18,END PROCESS;
19.
20,Q <= Q1;
21,END ARCHITECTURE bhv;
参见：
p110_ex5_2_CNT402
4位加法计数器设计（二）,图
4位加法计数器
设计（三 ）
1,LIBARY IEEE;
2,USE IEEE.STD_LOGIC_1164.ALL;
3,USE IEEE.STD_LOGIC_UNSIGNED.ALL;
4,ENTITY CNT10 IS
5,PORT ( CLK,RST,EN, IN STD_LOGIC;
6,CQ, OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
7,COUT, OUT STD_LOGIC
8,);
9,END ENTITY CNT10;
10,ARCHITECTURE bhv OF CNT10 IS
11,BEGIN
12,PROCESS(CLK,RST,EN)
13.
14,VARIABLE CQI,STD_LOGIC_VECTOR( 3 DOWNTO 0);
15,BEGIN
16,IF RST = '1' THEN
17,CQI,= (OTHERS >='0' );
18,ELSIF CLK'EVENT AMD CLK = '1' THEN
19,IF EN = '1' THEN
20,IF CQI < 9 THEN
21,CQI,= CQI + 1;
22,ELSE
23,CQI,= (OTHERS >='0' );
24,END IF;
25,END IF;
26,END IF;
27.
28,IF CQI = 9 THEN
29,COUT <= '1' ;
30,ELSE
31,COUT <= '0';
32,END IF;
33,CQ <= CQI
34.
35,END PROCESS;
36.
37,END ARCHITECTURE bhv;
具有异步
复位 (RST)
时钟使能 (EN)
参见,p113_ex5_3_CNT10
4位加法计数器设计（三）,图
三,8位数码管显示扫描电路设计
二,8位数码管显示扫描电路设计
K1…K8 为数码管的位控信号，对应 FPGA
的 PIO41,40,39,38,37,36,35,34a…g 为数码管的段控信号，对应 FPGA的 PIO49,48,47,46,45,44,43,42
实验
电路
1,LIBRARY IEEE;
2,USE IEEE.STD_LOGIC_1164.ALL;
3,USE IEEE.STD_LOGIC_UNSIGNED.ALL;
4,ENTITY SCAN_LED IS
5,PORT ( CLK, IN STD_LOGIC;
6,SG, OUT STD_LOGIC_VECTOR(6 DOWNTO 0); --段控制信号输出
7,BT, OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );--位控制信号输出
8,END;
9,ARCHITECTURE one OF SCAN_LED IS
10,SIGNAL CNT8, STD_LOGIC_VECTOR(2 DOWNTO 0);
11,SIGNAL A, INTEGER RANGE 0 TO 15;
12,BEGIN
13,P1,PROCESS( CNT8 )
14,BEGIN
15,CASE CNT8 IS
16,WHEN "000" => BT <= "00000001" ; A <= 1 ;
17,WHEN "001" => BT <= "00000010" ; A <= 3 ;
18,WHEN "010" => BT <= "00000100" ; A <= 5 ;
19,WHEN "011" => BT <= "00001000" ; A <= 7 ;
20,WHEN "100" => BT <= "00010000" ; A <= 9 ;
21,WHEN "101" => BT <= "00100000" ; A <= 11 ;
22,WHEN "110" => BT <= "01000000" ; A <= 13 ;
23,WHEN "111" => BT <= "10000000" ; A <= 15 ;
24,WHEN OTHERS => NULL ;
25,END CASE ;
26,END PROCESS P1;
27,P2,PROCESS(CLK)
28,BEGIN
29,IF CLK'EVENT AND CLK = '1' THEN CNT8 <= CNT8 + 1;
30,END IF;
31,END PROCESS P2 ;
32,P3,PROCESS( A ) --译码电路
33,BEGIN
34,CASE A IS
35,WHEN 0 => SG <= "0111111"; WHEN 1 => SG <= "0000110";
36,WHEN 2 => SG <= "1011011"; WHEN 3 => SG <= "1001111";
37,WHEN 4 => SG <= "1100110"; WHEN 5 => SG <= "1101101";
38,WHEN 6 => SG <= "1111101"; WHEN 7 => SG <= "0000111";
39,WHEN 8 => SG <= "1111111"; WHEN 9 => SG <= "1101111";
40,WHEN 10 => SG <= "1110111"; WHEN 11 => SG <= "1111100";
41,WHEN 12 => SG <= "0111001"; WHEN 13 => SG <= "1011110";
42,WHEN 14 => SG <= "1111001"; WHEN 15 => SG <= "1110001";
43,WHEN OTHERS => NULL ;
44,END CASE ;
45,END PROCESS P3;
46,END;
设计
编码
参见,
p145_ex5_22_SCAN_LED
译码进程
计数进程
位选进程
端口定义
端口定义
1,LIBARY IEEE;
2,USE IEEE.STD_LOGIC_1164.ALL;
3,USE IEEE.STD_LOGIC_UNSIGNED.ALL;
4,ENTITY scan_led IS
5,PORT ( CLK, IN STD_LOGIC;
6,SG, OUT STD_LOGIC_VECTOR ( 6 DOWNTO 0 );
-- segment control
7,BT, OUT STD_LOGIC_VECTOR ( 6 DOWNTO 0 )
-- bit control
8,);
9,END ENTITY scan_led;
位选进程
10,ARCHITECTURE BEHAV OF scan_led IS
11,SGINAL CNT8 STD_LOGIC_VECTOR ( 2 DOWNTO 0 );
12,SIGNAL A, INTEGER RANGE 0 TO 15;
13,BEGIN
14,P1:
15,PROCESS ( CNT8 )
16,BEGIN
17,CASE CNT8 IS
18,WHEN "000" => BT <= "00000001"; A <=1;
19,WHEN "001" => BT <= "00000010"; A <=3;
20,WHEN "010" => BT <= "00000100"; A <=5;
21,WHEN "011" => BT <= "00001000"; A <=7;
22,WHEN "100" => BT <= "00010000"; A <=9;
23,WHEN "101" => BT <= "00100000"; A <=11;
24,WHEN "110" => BT <= "01000000"; A <=13;
25,WHEN "111" => BT <= "10000000"; A <=15;
26,WHEN OTHERS => NULL;
27,END CASE;
28.
29,END PROCESS ledcoding;
计数进程
30,P2:
31,PROCESS ( CLK )
32,BEGIN
33.
34,IF CLK'EVENT AND CLK = '1' THEN
35,CNT8 <= CNT8 + 1;
36,END IF;
37.
38,END PROCESS P2;
译码进程
39,P3:
40,PROCESS ( A )
41,BEGIN
42,CASE A IS
43,WHEN 0 => BT <= "0111111"; -- 0
44,WHEN 1 => BT <= "0000110"; -- 1
45,WHEN 2 => BT <= "1011011"; -- 2
46,WHEN 3 => BT <= "1001111"; -- 3
47,WHEN 4 => BT <= "1100110"; -- 4
48,WHEN 5 => BT <= "1101101"; -- 5
49,WHEN 6 => BT <= "1111101"; -- 6
50,WHEN 7 => BT <= "0000111"; -- 7
51,WHEN 8 => BT <= "1111111"; -- 8
52,WHEN 9 => BT <= "1101111"; -- 9
53,WHEN 10 => BT <= "1110111"; -- A
54,WHEN 11 => BT <= "1111100"; -- B
55,WHEN 12 => BT <= "0111001"; -- C
56,WHEN 13 => BT <= "1011110"; -- D
57,WHEN 14 => BT <= "1111001"; -- E
58,WHEN 15 => BT <= "1110001"; -- F
59,WHEN OTHERS => NULL;
60,END CASE;
61.
62,END PROCESS P3:
63,END ARCHITECTURE BEHAV;
本试验思考
1,LED数码管是共阴极还是共阳极的？
2,修改 P1中的显示数据直接给出方式，增加 8
个 4位锁存器，作为显示数据缓冲器，所有
8个显示数据都必须来自缓冲器。缓冲器的
输入数据可设置为常数量。
3,修改 P1编码，用开关 8个开关控制显示 8位
不同的数据。
二,13分频器电路设计
三,13分频器电路设计
设计要求,
在 4位计数器的基础上实现 13
分频器,输出周期信号的占空
比不作要求,
The end.
以下内容
为
正文的引用，
可不阅读。
返回
STD_LOGIC的取值
1,TYPE std_ulogic IS ( 'U',-- Uninitialized
2,'X',-- Forcing Unknown
3,'0',-- Forcing 0
4,'1',-- Forcing 1
5,'Z',-- High Impedance
6,'W',-- Weak Unknown
7,'L',-- Weak 0
8,'H',-- Weak 1
9,'-' -- Don't care
10,);
返回
详细参见
STD1164.VHD
