第 9章第 2节
Quartus II中的优化设计
配置、仿真和报告
<EDA技术 与应用 > 课程讲义
下一章
合肥工业大学 彭良清
上一章
本节内容
一,时序分析的基本概念和术语
二,Quartus II中的时序约束设置
三,Quartus II中的时序分析
四,Quartus II中的编译报告
五,FPGA芯片的时序指标举例
有关时序分析更多的资料请参见
http://www.altera.com/quartushelp/list.jsp?keyw
ord=verificationanalysis
时序分析的基本概念和术语
1,时钟建立时间 (tSU:clock setup time)
2,时钟保持时间 (th:clock hold time)
3,时钟输出延时 (tCO,Clock to output delay)
4,时钟偏斜（ Clock Skew）
5,引脚到引脚的延时 (tPD,Pin-to-Pin Delay)
6,时序裕量（ Slack）
7,独立时钟和衍生时钟 （ Absolute Clock &
Derived Clock）
8,占空比 （ Duty Cycle）
9,行波时钟 （ Ripple Clock）
建立时间 和 保持时间
tSU= Data Delay + Micro tSU - Clock Delay
tSU (clock setup time)
tH=Clock Delay + Micro tH - Data Delay
tH (clock hold time)
tCO (Clock to output delay)
tCO=Clock Delay+Micro Tco+Data Delay
时钟偏斜（ clock skew）,图示
时钟偏斜（ clock skew）
?The difference in the arrival time of a clock
signal at two different registers,
?which can be caused by path length
differences between two clock paths,
?or by using gated or rippled clocks,
?Clock skew is the most common cause of
internal hold violations,as shown in figure
1
引脚间延时 tPD (pin-to-pin delay)
? The time required for a signal from an input pin to
propagate through combinational logic and appear
at an external output pin.
? In the Quartus? II software,you can specify the
required tPD for the entire project and/or for any
? input pin,
? output pin,
? bidirectional pin.
? You can also assign a point-to-point tPD
assignment to specify the required delay between
? an input pin and a register,
? a register and a register,
? a register and an output pin.
时序裕量（ Slack）
1,Slack is the margin by which a timing requirement
was met or not met,
2,A positive slack value,displayed in black,indicates
the margin by which a requirement was met,
3,A negative slack value,displayed in red,indicates
the margin by which a requirement was not met.
4,Slack time is calculated using the following equation:
slack = <required maximum P2P time> -
<actual maximum P2P time>
Timing Analyzer Summary
Type Slack Required
Time
Actual Time
Worst-case tsu N/A None 4.500 ns
Worst-case tco N/A None 10.900 ns
Worst-case th N/A None 1.000 ns
Worst-case Minimum tco N/A None 9.600 ns
Clock Setup,'clk' N/A None 96.15 MHz
独立时钟和衍生时钟
（ absolute clock & derived clock）
? 概念：
1,absolute clock
不依赖于 其他时钟信号而存在的时钟
2,derived clock
由某个 absolute clock 经过 相移、分频、倍频
而得到的时钟
? 时序分析的处理：
1,一个设计可以 允许 有 多个独立时钟 存在
2,只对 一个独立时钟内 相关的所有信号进行 时序分
析
占空比（ Duty cycle (%) ）
? Indicates the percentage of time that the signal
is high or low during the time period,
行波时钟（ Ripple Clock）
不建议使用
D触发器 输出 作为 驱动时钟
Quartus II中的时序约束设置：目的
? 目的：
1,时序约束对设计的 编译过程 起着重要作
用
2,布局布线工具 将对 最差的时序路径 进
行最多的努力
3,对于 不满足 时序设置 的 路径 将以,红色,
显示出来
Quartus II中的时序约束设置：内容
? 可以进行 那些 时序约束设置？
1,内部 时序约束设置
2,I/O 时序约束设置
3,最大 时序约束设置
4,最小 时序约束设置
5,全局 时序约束设置
6,单个节点或模块 时序约束设置
Quartus II中的时序约束设置：步骤
1,先 进行全局设置,再 进行单个设置
2,单个设置的 优先级别 高于 全局设置（在 2
者冲突的情况下）
3,方法：
I,通过 菜单窗口 设置,
Assignments->Time Setings
Assignments->Setings-> Timing Require & Options
II,通过修改,,QSF”文件 设置
全局时序设置建立延时
输出延时
引脚间延时
时钟频率
最小输出延时
最小保持延时
最小引脚间延时
剪除选项
Cut Options
1,Cut Off Feedback from I/O Pins
2,Cut Off Clear and Preset Signal Paths
3,Cut Off Read During Write Signal Paths
4,Cut Paths between Unrelated Clock
Domains
单个时钟设置（ Invididual Clock）
独立时钟设置
衍生时钟设置
Quartus II中的时序分析
报告类型 文件扩展名
Analysis & Synthesis 分析与综合,map.rpt
Assembler, asm.rpt
Compilation（ This report file is a single file that
combines the information of the individual
module compilation report files.）编译
.cmp.rpt
Design Assistant,drc.rpt
EDA Netlist Writer,eda.rpt
Fitter,fit.rpt
Flow,flow.rpt
Simulator,sim.rpt
Timing Analyzer,tan.rpt
Quartus II中的编译报告文件
FPGA芯片的时序指标
The end
The end.
以下内容
为
正文的引用，
可不阅读。
建立时间 和 保持时间
返回
Cut Off Clear and Preset Signal Paths
?Cuts off the timing paths for all clear and
preset signals in the current design,When
you turn this option on,the Timing
Analyzer does not consider the delay
along these paths during timing analysis.
?When you turn Cut off clear and preset
signal paths on,the Timing Analyzer does
not include clear and preset signals to a D
flipflop in the timing analysis,Cutting off
these paths may help eliminate invalid paths
from the timing analysis,返回
Cut Off Feedback from I/O Pins
? Cuts off the delay that is fed back from a bidirectional
pin during timing analysis,You can use a bidirectional pin
as both an input pin and output pin,When you turn on Cut
off feedback from I/O pins,the timing analysis does not
include signal feedback from within the device,thus
eliminating invalid paths.
? Cut off feedback from I/O pins is especially useful when
you connect a bidirectional pin directly or indirectly to
both the input and the output of a latch,This type of
feedback path is continuous because clocked logic
primitives cannot interrupt the path,As the Timing Analyzer
encounters additional,interconnected latch-to-pin loops,
the number of hidden paths grows exponentially,for
example,when you use latches with bidirectional buses,
Cut off feedback from I/O pins allows you to easily
eliminate the false paths caused by latch-to-pin loops.返回
Cut Off Read During Write Signal Paths
? Cuts off the delay from the write enable register
through the Embedded System Block (ESB) to any
destination register during timing analysis,When
you turn Cut off read during write signal paths
on,the Timing Analyzer does not consider the
delay along these paths during timing analysis.
? If your design reads the data from the ESB as it is
written,you may want to turn off Cut off read
during write signal paths,However,if your
design does not read the data from the ESB as it
is written,the delay from these paths can cause
misleading results in your timing analysis unless
you turn on Cut off read during write signal
paths.
返回
Cut Paths between Unrelated Clock Domains
?Eliminates the paths between unrelated
clock domains from the timing analysis.
? When you turn Cut paths between
unrelated clock domains on,the Timing
Analyzer ignores the delay along these
paths during timing analysis.
返回
Using I/O Timing Requirements
? The Quartus II Timing Analyzer provides two methods for specifying
I/O timing requirements,You can specify I/O timing requirements using
the traditional tsu Requirement,tco Requirement,and/or th
Requirement timing assignments (results reported in the tsu,th,and
tco Timing Analyzer reports),or you can include these paths as part of
the clock analysis by using the Input Maximum Delay,Input
Minimum Delay,Output Maximum Delay,or Output Minimum
Delay assignments to specify delays based on external device timing
(results reported in Clock Setup or Clock Hold Timing Analyzer reports),
Both types of I/O timing requirements ultimately produce similar results
through different methods,The following example illustrates this
similarity by showing how assigning either a tsu Requirement or Input
Maximum Delay requirement achieves a required clock period,The
example assumes a 10ns clock period requirement,4ns external delay,
and zero clock delay (for simplification).
? 参见图示
two methods for
specifying I/O timing requirements.
Two or More Register Outputs in Cascade Should Not
Directly Drive Clock Ports of Following Registers (Design
Assistant Rule)
? A design should not contain ripple clock structures,that is,structures
where the outputs of two or more registers in a cascade each directly
drives the input clock port of the following register in the cascade,The
following image shows an example of a ripple clock structure
? Each stage of a ripple clock structure causes phase delay,which
accumulates and results in large skews in the structure's output signal;
the large skew can cause problems when you use the ripple clock
structure as a clock signal for other circuits,Each stage of a ripple
clock structure also causes a new clock domain to be defined; the
additional clock domains make timing analysis of the design more
complex and time-consuming.
? Ripple clock structures are often used to make counters out of the
smallest amount of logic possible,However,in all Altera? devices
supported by the Quartus? II software,using a ripple clock structure to
reduce the amount of logic used for a counter is unnecessary because
the device allows you to construct a counter using one logic element
per counter bit.
返回
tSU (clock setup time)
? The length of time for which data that feeds a register via
its data or enable input(s) must be present at an input pin
before the clock signal that clocks the register is asserted
at the clock pin.
? In the Quartus? II software,you can specify a required
tSU for the entire project and/or for any input pin,
bidirectional pin,input register,or clock,
? You can also specify a point-to-point tSU requirement
between an input pin and a register.
? The Timing Analyzer calculates tSU using the following
equation:
tSU = <pin to register delay>
+ <micro setup delay>
- <clock to destination register delay>
返回
tH (clock hold time)
? The minimum length of time for which data that feeds a
register via its data or enable input(s) must be retained
at an input pin after the clock signal that clocks the
register is asserted at the clock pin.
? In the Quartus? II software,you can specify a required tH
for the entire project and/or for any input pin,bidirectional
pin,input register,or clock,
? You can also specify a point-to-point tH requirement
between an input pin and a register.
? The Timing Analyzer calculates tH using the following
equation:
tH = <clock to destination register delay>
+ <micro hold delay of destination register>
- <pin to register delay> 返回
tCO (Clock to output delay)
? The maximum time required to obtain a valid output at an
output pin that is fed by a register after a clock signal
transition on an input pin that clocks the register,This time
always represents an external pin-to-pin delay.
? In the Quartus? II software,you can specify the required
tCO for the entire project and/or any clock signal,any
register driving an output or bidirectional pin,or any output
or bidirectional pin driven by a register,You can also
specify a point-to-point tCO requirement between a clock
and a register,a clock and an output pin,or a register and
an output pin.
? tCO is calculated using the following equation:
tCO = <clock to source register delay>
+ <micro clock to output delay>
+<register to pin delay> 返回
Design Assistant Rules
? Clock
? Combinational logic used as clock signal should be implemented according to Altera? standard scheme
? Inverter should not be implemented in logic cell
? Input clock pin should fan out to only one set of combinational logic used as clock signal
? Clock signal source should drive only input clock ports
? Clock signal should be a global signal
? Clock signal source should not drive registers that are triggered by different clock edges
? Reset
? Combinational logic used as reset signal should be synchronized
? External reset should be synchronized using two cascaded registers
? External reset should be correctly synchronized
? Reset signal source should drive only input reset ports
? Reset signal that is generated in one clock domain and used in other,asynchronous clock domains should be
synchronized
? Reset signal that is generated in one clock domain and used in other,asynchronous clock domains should be
correctly synchronized
? Timing Closure
? Nodes with more than specified number of fan-outs,<n>
? Top nodes with highest fan-out,<n>
? Register output directly drives input of another register when both registers are triggered at same time
? Registers in direct data transfer between clock domains are triggered by clock edges at the same time
? Non-synchronous design structure
? Design should not contain combinational loops
? Register output should not drive its own control signal directly or through combinational logic
? Design should not contain delay chains
? Two or more register outputs in cascade should not directly drive clock ports of following registers
? Pulses should be implemented according to Altera standard scheme
? Multiple pulses should not be generated in design
? Design should not contain SR latches
? Design should not contain latches
? Combinational logic should not directly drive write enable signal of asynchronous RAM
? Design should not contain asynchronous memory
? Signal race
? Output enable and input of tri-state node should not be driven by same signal source
? Asynchronous clock domains
保
持
时
间
关
系：
图
1
保
持
时
间
关
系：
图
2
保持时间关系：图 2
hold relationship（ 1）
? The assumed hold timing relationship between the source
and destination clocks in a multicycle path,The Timing
Analyzer assumes the most stringent hold relationship (0
ns by default) when analyzing paths between registers,
The Timing Analyzer performs the following two hold
checks to verify that each design meets the conditions of
the default hold relationship,The Timing Analyzer reports
an internal hold violation in the Clock Hold section of the
Compilation Report when a receiving clock is presented
with data that does not meet these hold relationship
checks,Guidelines
hold relationship （ 2）
? Hold relationship check 1Verifies that data from
the source clock edge,which follows the setup
launch edge,is not latched by the setup latch
edge
?,Hold relationship check 2Verifies that data from
the setup launch edge is not latched by the
destination clock edge that precedes the setup
latch edge.The following illustration shows the
default hold relationship for a multifrequency path.
hold relationship （ 3）
? You can relax the default hold relationship in various ways
by assigning the Hold Relationship,Minimum Delay,
Multicycle Hold,Source Multicycle Hold,Clock Enable
Multicycle Hold,or Clock Enable Source Multicycle
Hold timing assignments,Figure 2 shows how assigning a
Multicycle Hold value of 2 affects the hold relationship,
? By default,the Timing Analyzer assumes that the Default
Multicycle Hold setting is the same as the Multicycle
setting,Therefore,if you assign a Multicycle,Source
Multicycle,Clock Enable Multicycle,or Clock Enable
Source Multicycle assignment,the corresponding hold
requirement is similarly changed unless you specify a
specific value for the hold requirement,For example,figure
3 shows how the hold requirement is affected by both an
implied and specified hold requirement,
内部保持时间违规：图 1
内部保持时间违规：图 2
Cause of Internal Hold Violations
? An internal hold violation occurs when a receiving clock is presented
with data that has not met the hold requirement,This condition usually
occurs because of clock skew introduced by gated clocks in the design,
The example shown in figure 1 is unlikely to produce an internal hold
violation because the global non-gated clock has zero skew,Therefore,
the data path would have to be less than zero in order to cause a hold
violation,However,gated clocks may add delay to the destination clock
path,producing clock skew that can lead to internal hold violations,as
shown in figure 2
? In figure 2,the 3 ns clock skew caused by the gated clock imposes a
point-to-point hold requirement of 3 ns (accounting for clock delay),If
the data delay is less than the 3 ns clock skew,the clock is presented
with data that has not met the hold requirement,thus producing an
internal hold violation,
修正保持时间违规方法之一,
不用门控时钟，改用时钟使能信号
修正保持时间违规方法之一,
不用门控时钟，改用时钟使能信号
? Correcting Internal Hold Violations
? Use one or more of the following guidelines to correct detected internal
hold violations:
? Remove gated clocks and use a clock enable instead
? This guideline is the preferred method of eliminating clock skew and
hold violations; however,it may not always be possible,Replacing
gated clocks with clock enables eliminates clock skew by ensuring that
all clocks are on the main clock tree,When converting from a gated
clock to a clock enable,it is important to note that a gated clock is
edge-sensitive,while a clock enable is level-sensitive,Therefore,a
clock enable should only be active for one cycle before the gated
clock's edge,and it should be active for only one clock cycle per gated
clock's rising edge,In order for the clock enable to emulate the desired
behavior of the gated clock,a single pulse must be generated once per
clock cycle before the gated clock is asserted,as shown in figure 3.
Quartus II中的优化设计
配置、仿真和报告
<EDA技术 与应用 > 课程讲义
下一章
合肥工业大学 彭良清
上一章
本节内容
一,时序分析的基本概念和术语
二,Quartus II中的时序约束设置
三,Quartus II中的时序分析
四,Quartus II中的编译报告
五,FPGA芯片的时序指标举例
有关时序分析更多的资料请参见
http://www.altera.com/quartushelp/list.jsp?keyw
ord=verificationanalysis
时序分析的基本概念和术语
1,时钟建立时间 (tSU:clock setup time)
2,时钟保持时间 (th:clock hold time)
3,时钟输出延时 (tCO,Clock to output delay)
4,时钟偏斜（ Clock Skew）
5,引脚到引脚的延时 (tPD,Pin-to-Pin Delay)
6,时序裕量（ Slack）
7,独立时钟和衍生时钟 （ Absolute Clock &
Derived Clock）
8,占空比 （ Duty Cycle）
9,行波时钟 （ Ripple Clock）
建立时间 和 保持时间
tSU= Data Delay + Micro tSU - Clock Delay
tSU (clock setup time)
tH=Clock Delay + Micro tH - Data Delay
tH (clock hold time)
tCO (Clock to output delay)
tCO=Clock Delay+Micro Tco+Data Delay
时钟偏斜（ clock skew）,图示
时钟偏斜（ clock skew）
?The difference in the arrival time of a clock
signal at two different registers,
?which can be caused by path length
differences between two clock paths,
?or by using gated or rippled clocks,
?Clock skew is the most common cause of
internal hold violations,as shown in figure
1
引脚间延时 tPD (pin-to-pin delay)
? The time required for a signal from an input pin to
propagate through combinational logic and appear
at an external output pin.
? In the Quartus? II software,you can specify the
required tPD for the entire project and/or for any
? input pin,
? output pin,
? bidirectional pin.
? You can also assign a point-to-point tPD
assignment to specify the required delay between
? an input pin and a register,
? a register and a register,
? a register and an output pin.
时序裕量（ Slack）
1,Slack is the margin by which a timing requirement
was met or not met,
2,A positive slack value,displayed in black,indicates
the margin by which a requirement was met,
3,A negative slack value,displayed in red,indicates
the margin by which a requirement was not met.
4,Slack time is calculated using the following equation:
slack = <required maximum P2P time> -
<actual maximum P2P time>
Timing Analyzer Summary
Type Slack Required
Time
Actual Time
Worst-case tsu N/A None 4.500 ns
Worst-case tco N/A None 10.900 ns
Worst-case th N/A None 1.000 ns
Worst-case Minimum tco N/A None 9.600 ns
Clock Setup,'clk' N/A None 96.15 MHz
独立时钟和衍生时钟
（ absolute clock & derived clock）
? 概念：
1,absolute clock
不依赖于 其他时钟信号而存在的时钟
2,derived clock
由某个 absolute clock 经过 相移、分频、倍频
而得到的时钟
? 时序分析的处理：
1,一个设计可以 允许 有 多个独立时钟 存在
2,只对 一个独立时钟内 相关的所有信号进行 时序分
析
占空比（ Duty cycle (%) ）
? Indicates the percentage of time that the signal
is high or low during the time period,
行波时钟（ Ripple Clock）
不建议使用
D触发器 输出 作为 驱动时钟
Quartus II中的时序约束设置：目的
? 目的：
1,时序约束对设计的 编译过程 起着重要作
用
2,布局布线工具 将对 最差的时序路径 进
行最多的努力
3,对于 不满足 时序设置 的 路径 将以,红色,
显示出来
Quartus II中的时序约束设置：内容
? 可以进行 那些 时序约束设置？
1,内部 时序约束设置
2,I/O 时序约束设置
3,最大 时序约束设置
4,最小 时序约束设置
5,全局 时序约束设置
6,单个节点或模块 时序约束设置
Quartus II中的时序约束设置：步骤
1,先 进行全局设置,再 进行单个设置
2,单个设置的 优先级别 高于 全局设置（在 2
者冲突的情况下）
3,方法：
I,通过 菜单窗口 设置,
Assignments->Time Setings
Assignments->Setings-> Timing Require & Options
II,通过修改,,QSF”文件 设置
全局时序设置建立延时
输出延时
引脚间延时
时钟频率
最小输出延时
最小保持延时
最小引脚间延时
剪除选项
Cut Options
1,Cut Off Feedback from I/O Pins
2,Cut Off Clear and Preset Signal Paths
3,Cut Off Read During Write Signal Paths
4,Cut Paths between Unrelated Clock
Domains
单个时钟设置（ Invididual Clock）
独立时钟设置
衍生时钟设置
Quartus II中的时序分析
报告类型 文件扩展名
Analysis & Synthesis 分析与综合,map.rpt
Assembler, asm.rpt
Compilation（ This report file is a single file that
combines the information of the individual
module compilation report files.）编译
.cmp.rpt
Design Assistant,drc.rpt
EDA Netlist Writer,eda.rpt
Fitter,fit.rpt
Flow,flow.rpt
Simulator,sim.rpt
Timing Analyzer,tan.rpt
Quartus II中的编译报告文件
FPGA芯片的时序指标
The end
The end.
以下内容
为
正文的引用，
可不阅读。
建立时间 和 保持时间
返回
Cut Off Clear and Preset Signal Paths
?Cuts off the timing paths for all clear and
preset signals in the current design,When
you turn this option on,the Timing
Analyzer does not consider the delay
along these paths during timing analysis.
?When you turn Cut off clear and preset
signal paths on,the Timing Analyzer does
not include clear and preset signals to a D
flipflop in the timing analysis,Cutting off
these paths may help eliminate invalid paths
from the timing analysis,返回
Cut Off Feedback from I/O Pins
? Cuts off the delay that is fed back from a bidirectional
pin during timing analysis,You can use a bidirectional pin
as both an input pin and output pin,When you turn on Cut
off feedback from I/O pins,the timing analysis does not
include signal feedback from within the device,thus
eliminating invalid paths.
? Cut off feedback from I/O pins is especially useful when
you connect a bidirectional pin directly or indirectly to
both the input and the output of a latch,This type of
feedback path is continuous because clocked logic
primitives cannot interrupt the path,As the Timing Analyzer
encounters additional,interconnected latch-to-pin loops,
the number of hidden paths grows exponentially,for
example,when you use latches with bidirectional buses,
Cut off feedback from I/O pins allows you to easily
eliminate the false paths caused by latch-to-pin loops.返回
Cut Off Read During Write Signal Paths
? Cuts off the delay from the write enable register
through the Embedded System Block (ESB) to any
destination register during timing analysis,When
you turn Cut off read during write signal paths
on,the Timing Analyzer does not consider the
delay along these paths during timing analysis.
? If your design reads the data from the ESB as it is
written,you may want to turn off Cut off read
during write signal paths,However,if your
design does not read the data from the ESB as it
is written,the delay from these paths can cause
misleading results in your timing analysis unless
you turn on Cut off read during write signal
paths.
返回
Cut Paths between Unrelated Clock Domains
?Eliminates the paths between unrelated
clock domains from the timing analysis.
? When you turn Cut paths between
unrelated clock domains on,the Timing
Analyzer ignores the delay along these
paths during timing analysis.
返回
Using I/O Timing Requirements
? The Quartus II Timing Analyzer provides two methods for specifying
I/O timing requirements,You can specify I/O timing requirements using
the traditional tsu Requirement,tco Requirement,and/or th
Requirement timing assignments (results reported in the tsu,th,and
tco Timing Analyzer reports),or you can include these paths as part of
the clock analysis by using the Input Maximum Delay,Input
Minimum Delay,Output Maximum Delay,or Output Minimum
Delay assignments to specify delays based on external device timing
(results reported in Clock Setup or Clock Hold Timing Analyzer reports),
Both types of I/O timing requirements ultimately produce similar results
through different methods,The following example illustrates this
similarity by showing how assigning either a tsu Requirement or Input
Maximum Delay requirement achieves a required clock period,The
example assumes a 10ns clock period requirement,4ns external delay,
and zero clock delay (for simplification).
? 参见图示
two methods for
specifying I/O timing requirements.
Two or More Register Outputs in Cascade Should Not
Directly Drive Clock Ports of Following Registers (Design
Assistant Rule)
? A design should not contain ripple clock structures,that is,structures
where the outputs of two or more registers in a cascade each directly
drives the input clock port of the following register in the cascade,The
following image shows an example of a ripple clock structure
? Each stage of a ripple clock structure causes phase delay,which
accumulates and results in large skews in the structure's output signal;
the large skew can cause problems when you use the ripple clock
structure as a clock signal for other circuits,Each stage of a ripple
clock structure also causes a new clock domain to be defined; the
additional clock domains make timing analysis of the design more
complex and time-consuming.
? Ripple clock structures are often used to make counters out of the
smallest amount of logic possible,However,in all Altera? devices
supported by the Quartus? II software,using a ripple clock structure to
reduce the amount of logic used for a counter is unnecessary because
the device allows you to construct a counter using one logic element
per counter bit.
返回
tSU (clock setup time)
? The length of time for which data that feeds a register via
its data or enable input(s) must be present at an input pin
before the clock signal that clocks the register is asserted
at the clock pin.
? In the Quartus? II software,you can specify a required
tSU for the entire project and/or for any input pin,
bidirectional pin,input register,or clock,
? You can also specify a point-to-point tSU requirement
between an input pin and a register.
? The Timing Analyzer calculates tSU using the following
equation:
tSU = <pin to register delay>
+ <micro setup delay>
- <clock to destination register delay>
返回
tH (clock hold time)
? The minimum length of time for which data that feeds a
register via its data or enable input(s) must be retained
at an input pin after the clock signal that clocks the
register is asserted at the clock pin.
? In the Quartus? II software,you can specify a required tH
for the entire project and/or for any input pin,bidirectional
pin,input register,or clock,
? You can also specify a point-to-point tH requirement
between an input pin and a register.
? The Timing Analyzer calculates tH using the following
equation:
tH = <clock to destination register delay>
+ <micro hold delay of destination register>
- <pin to register delay> 返回
tCO (Clock to output delay)
? The maximum time required to obtain a valid output at an
output pin that is fed by a register after a clock signal
transition on an input pin that clocks the register,This time
always represents an external pin-to-pin delay.
? In the Quartus? II software,you can specify the required
tCO for the entire project and/or any clock signal,any
register driving an output or bidirectional pin,or any output
or bidirectional pin driven by a register,You can also
specify a point-to-point tCO requirement between a clock
and a register,a clock and an output pin,or a register and
an output pin.
? tCO is calculated using the following equation:
tCO = <clock to source register delay>
+ <micro clock to output delay>
+<register to pin delay> 返回
Design Assistant Rules
? Clock
? Combinational logic used as clock signal should be implemented according to Altera? standard scheme
? Inverter should not be implemented in logic cell
? Input clock pin should fan out to only one set of combinational logic used as clock signal
? Clock signal source should drive only input clock ports
? Clock signal should be a global signal
? Clock signal source should not drive registers that are triggered by different clock edges
? Reset
? Combinational logic used as reset signal should be synchronized
? External reset should be synchronized using two cascaded registers
? External reset should be correctly synchronized
? Reset signal source should drive only input reset ports
? Reset signal that is generated in one clock domain and used in other,asynchronous clock domains should be
synchronized
? Reset signal that is generated in one clock domain and used in other,asynchronous clock domains should be
correctly synchronized
? Timing Closure
? Nodes with more than specified number of fan-outs,<n>
? Top nodes with highest fan-out,<n>
? Register output directly drives input of another register when both registers are triggered at same time
? Registers in direct data transfer between clock domains are triggered by clock edges at the same time
? Non-synchronous design structure
? Design should not contain combinational loops
? Register output should not drive its own control signal directly or through combinational logic
? Design should not contain delay chains
? Two or more register outputs in cascade should not directly drive clock ports of following registers
? Pulses should be implemented according to Altera standard scheme
? Multiple pulses should not be generated in design
? Design should not contain SR latches
? Design should not contain latches
? Combinational logic should not directly drive write enable signal of asynchronous RAM
? Design should not contain asynchronous memory
? Signal race
? Output enable and input of tri-state node should not be driven by same signal source
? Asynchronous clock domains
保
持
时
间
关
系：
图
1
保
持
时
间
关
系：
图
2
保持时间关系：图 2
hold relationship（ 1）
? The assumed hold timing relationship between the source
and destination clocks in a multicycle path,The Timing
Analyzer assumes the most stringent hold relationship (0
ns by default) when analyzing paths between registers,
The Timing Analyzer performs the following two hold
checks to verify that each design meets the conditions of
the default hold relationship,The Timing Analyzer reports
an internal hold violation in the Clock Hold section of the
Compilation Report when a receiving clock is presented
with data that does not meet these hold relationship
checks,Guidelines
hold relationship （ 2）
? Hold relationship check 1Verifies that data from
the source clock edge,which follows the setup
launch edge,is not latched by the setup latch
edge
?,Hold relationship check 2Verifies that data from
the setup launch edge is not latched by the
destination clock edge that precedes the setup
latch edge.The following illustration shows the
default hold relationship for a multifrequency path.
hold relationship （ 3）
? You can relax the default hold relationship in various ways
by assigning the Hold Relationship,Minimum Delay,
Multicycle Hold,Source Multicycle Hold,Clock Enable
Multicycle Hold,or Clock Enable Source Multicycle
Hold timing assignments,Figure 2 shows how assigning a
Multicycle Hold value of 2 affects the hold relationship,
? By default,the Timing Analyzer assumes that the Default
Multicycle Hold setting is the same as the Multicycle
setting,Therefore,if you assign a Multicycle,Source
Multicycle,Clock Enable Multicycle,or Clock Enable
Source Multicycle assignment,the corresponding hold
requirement is similarly changed unless you specify a
specific value for the hold requirement,For example,figure
3 shows how the hold requirement is affected by both an
implied and specified hold requirement,
内部保持时间违规：图 1
内部保持时间违规：图 2
Cause of Internal Hold Violations
? An internal hold violation occurs when a receiving clock is presented
with data that has not met the hold requirement,This condition usually
occurs because of clock skew introduced by gated clocks in the design,
The example shown in figure 1 is unlikely to produce an internal hold
violation because the global non-gated clock has zero skew,Therefore,
the data path would have to be less than zero in order to cause a hold
violation,However,gated clocks may add delay to the destination clock
path,producing clock skew that can lead to internal hold violations,as
shown in figure 2
? In figure 2,the 3 ns clock skew caused by the gated clock imposes a
point-to-point hold requirement of 3 ns (accounting for clock delay),If
the data delay is less than the 3 ns clock skew,the clock is presented
with data that has not met the hold requirement,thus producing an
internal hold violation,
修正保持时间违规方法之一,
不用门控时钟，改用时钟使能信号
修正保持时间违规方法之一,
不用门控时钟，改用时钟使能信号
? Correcting Internal Hold Violations
? Use one or more of the following guidelines to correct detected internal
hold violations:
? Remove gated clocks and use a clock enable instead
? This guideline is the preferred method of eliminating clock skew and
hold violations; however,it may not always be possible,Replacing
gated clocks with clock enables eliminates clock skew by ensuring that
all clocks are on the main clock tree,When converting from a gated
clock to a clock enable,it is important to note that a gated clock is
edge-sensitive,while a clock enable is level-sensitive,Therefore,a
clock enable should only be active for one cycle before the gated
clock's edge,and it should be active for only one clock cycle per gated
clock's rising edge,In order for the clock enable to emulate the desired
behavior of the gated clock,a single pulse must be generated once per
clock cycle before the gated clock is asserted,as shown in figure 3.
