-- Classic 2-Process State Machine and Test Bench -- MEALY TYPE STATE MACHINE EXAMPLE -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; ENTITY fsm IS PORT(clock,x : IN BIT; z : OUT BIT); END fsm; ------------------------------------------------- ARCHITECTURE behaviour OF fsm IS TYPE state_type IS (s0,s1,s2,s3); SIGNAL present_state,next_state : state_type; BEGIN --state register process state_reg:PROCESS BEGIN WAIT UNTIL clock'EVENT AND clock = '1'; present_state <= next_state; END PROCESS; --combinational logic feedback process fb_logic:PROCESS(present_state,x) BEGIN CASE present_state IS WHEN s0 => IF x = '0' THEN z <= '0'; next_state <= s0; ELSE z <= '1'; next_state <= s2; END IF; WHEN s1 => IF x = '0' THEN z <= '0'; next_state <= s0; ELSE z <= '0'; next_state <= s2; END IF; WHEN s2 => IF x = '0' THEN z <= '1'; next_state <= s2; ELSE z <= '0'; next_state <= s3; END IF; WHEN s3 => IF x = '0' THEN z <= '0'; next_state <= s3; ELSE z <= '1'; next_state <= s1; END IF; END CASE; END PROCESS; END behaviour; ----------------------------------------------------------- --STIMULUS GENERATOR FOR FSM ENTITY fsm_stim IS PORT (clock,x: OUT BIT; z: IN BIT); END fsm_stim; ARCHITECTURE behavioural OF fsm_stim IS BEGIN --clock pulses : __--__--__--__--__--__ --x input : _____------------_____ --each '-' represents 5 ns. clock <= '0' AFTER 0 ns, '1' AFTER 10 ns, --clock 1 '0' AFTER 20 ns, '1' AFTER 30 ns, --clock 2 '0' AFTER 40 ns, '1' AFTER 50 ns, --clock 3 '0' AFTER 60 ns, '1' AFTER 70 ns, --clock 4 '0' AFTER 80 ns, '1' AFTER 90 ns, --clock 5 '0' AFTER 100 ns; x <= '0' AFTER 0 ns, '1' AFTER 25 ns, '0' AFTER 85 ns; END behavioural; ----------------------------------------------- ENTITY fsm_bench IS END fsm_bench; ARCHITECTURE structural OF fsm_bench IS COMPONENT fsm_stim PORT (clock,x: OUT BIT; z: IN BIT); END COMPONENT; COMPONENT fsm PORT (clock,x: IN BIT; z: OUT BIT); END COMPONENT; SIGNAL clock,x,z: BIT; BEGIN generator:fsm_stim PORT MAP(clock,x,z); circuit:fsm PORT MAP(clock,x,z); END structural;