合肥工业大学：EDA技术与应用（精品课程）：hfut01_buffer4

-- 4 LEVEL BUFFER CODE DEMO -- write by : Peng liangqing library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.ALL; entity BUFFER4 is port ( RESET : in STD_LOGIC; --BIT; CLK : in STD_LOGIC; --BIT; IDATA : IN STD_LOGIC_VECTOR(7 downto 0); --BIT; ODATA : OUT STD_LOGIC_VECTOR(7 downto 0) --BIT; ); end BUFFER4; architecture RTL of BUFFER4 is SIGNAL sgIDATA1:STD_LOGIC_VECTOR(7 downto 0); SIGNAL sgIDATA2:STD_LOGIC_VECTOR(7 downto 0); SIGNAL sgIDATA3:STD_LOGIC_VECTOR(7 downto 0); SIGNAL sgIDATA4:STD_LOGIC_VECTOR(7 downto 0); BEGIN PROCESS(CLK,RESET) BEGIN IF(RESET='0') THEN sgIDATA1<=X"00"; sgIDATA2<=X"00"; sgIDATA3<=X"00"; sgIDATA4<=X"00"; ELSIF (CLK'event AND CLK='0') THEN sgIDATA1 <= IDATA; sgIDATA2 <= sgIDATA1; sgIDATA3 <= sgIDATA2; sgIDATA4 <= sgIDATA3; END IF; oDATA<=sgIDATA4; END PROCESS; END ARCHITECTURE RTL;