合肥工业大学：EDA技术与应用（精品课程）：hfut04_component_demo1_01

-- Language : VHDL -- File name : demo1_01.VHD -- Description : This is demo code for component instance -- It is inverter code -- See also : demo_02.VHD -- Top file : demo1.VHD ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY demo1_01 IS PORT ( A : IN STD_LOGIC; B : OUT STD_LOGIC ); END ENTITY demo1_01; ARCHITECTURE bhv OF demo1_01 IS BEGIN B <= not A; END ARCHITECTURE bhv;