合肥工业大学：EDA技术与应用（精品课程）：hfut04_component_demo1_02

-- Language : VHDL -- File name : demo1_02.VHD -- Description : This is demo code for component instance -- It is two and gate code -- See also : demo_01.VHD -- Top file : demo1.VHD ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY demo1_02 IS PORT ( X : IN STD_LOGIC; Y : IN STD_LOGIC; Z : OUT STD_LOGIC ); END ENTITY demo1_02; ARCHITECTURE bhv OF demo1_02 IS BEGIN Z <= X AND Y; END ARCHITECTURE bhv;