--VHDL code position: xd_p116_ex5_39_shift ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY shift IS PORT ( a, clk : IN STD_LOGIC; b : OUT STD_LOGIC ); END ENTITY shift; ARCHITECTURE bhv OF shift IS COMPONENT dff PORT ( d, clk : IN STD_LOGIC; q : OUT STD_LOGIC }; END COMPONENT dff; SIGNAL z : OUT STD_LOGIC_VECTOR ( 0 TO 4 ); BEGIN z(0) <= a; g1: FOR i IN 0 TO 3 GENERATE dffx: dff PORT MAP ( z(i), clk, z(i+1) ); END GENERATE; b <= z(4) ; END ARCHITECTURE bhv;