合肥工业大学：EDA技术与应用（精品课程）：xd_p141_ex7_11_decoder_3_to_8

--VHDL code position: xd_p141_ex7_11_decoder_3_to_8 --Note: the code is 3 to 8 decoder LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY decoder_3_to_8 IS PORT ( A, B, C : IN STD_LOGIC; G1, G2A, G2B : IN STD_LOGIC; y : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ); END ENTITY decoder_3_to_8; ARCHITECTURE RTL OF decoder_3_to_8 IS SIGNAL indata : STD_LOGIC_VECTOR ( 2 DOWNTO 0 ); BEGIN indata<= C & B & A; PROCESS ( indata, G1, G2A, G2B ) BEGIN IF ( G1= '1' AND G2A = '1' AND G2B = '1' ) THEN CASE muxval is WHEN "000" => y <= "11111110"; WHEN "001" => y <= "11111101"; WHEN "010" => y <= "11111011"; WHEN "011" => y <= "11110111"; WHEN "100" => y <= "11101111"; WHEN "101" => y <= "11011111"; WHEN "110" => y <= "10111111"; WHEN "111" => y <= "01111111"; WHEN OTHERS => y <= "XXXXXXXX"; END CASE; ELSE y <= "11111111"; END IF; END PROCESS; END ARCHITECTURE RTL;