合肥工业大学：EDA技术与应用（精品课程）：xd_p69_ex5_1A_wait

--VHDL code position: xd_p69_ex5_1A_wait ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY wait5_1a IS PORT ( a, b : IN STD_LOGIC; y : OUT STD_LOGIC ); END ENTITY wait5_1a; ARCHITECTURE bhv OF wait5_1a IS BEGIN PROCESS( a, b ) BEGIN y <= a AND b END PROCESS; END ARCHITECTURE bhv;