合肥工业大学：EDA技术与应用（精品课程）：xd_p69_ex5_3_wait

--VHDL code position: xd_p71_ex5_3_wait ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY wait5_3 IS PORT ( pA, pB : OUT STD_LOGIC ); END ENTITY wait5_3; ARCHITECTURE bhv OF wait5_3 IS SIGNAL sendA, sendB : STD_LOGIC; BEGIN sendA <= '0'; pA <= sendA; pB <= sendB; A: PROCESS BEGIN WAIT UNTIL sendB='1'; sendA <='1' AFTER 10 ns; WAIT UNTIL sendB='0'; sendA <='0' AFTER 10 ns; END PROCESS A; B: PROCESS BEGIN WAIT UNTIL sendA='0'; sendB <='0' AFTER 10 ns; WAIT UNTIL sendA='1'; sendB <='1' AFTER 10 ns; END PROCESS B; END ARCHITECTURE bhv;