--VHDL code position: xd_p35_ex3_1B_assign
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_aRITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ASSIGN2 IS
PORT ( A, B, C : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
X, Y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END ENTITY ASSIGN2;
ARCHITECTURE bhv OF ASSIGN2 IS
BEGIN
PROCESS( A, B, C )
VARIABLE D: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
D := A;
X <= B + D;
D := C;
Y <= B + D;
END PROCESS;
END ARCHITECTURE bhv;