合肥工业大学：EDA技术与应用（精品课程）：xd_p35_ex3_1A_assign.TXT

--VHDL code position: xd_p35_ex3_1A_assign ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ASSIGN1 IS PORT ( A, B, C : IN STD_LOGIC_VECTOR(3 DOWNTO 0); X, Y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END ENTITY ASSIGN1; ARCHITECTURE bhv OF ASSIGN1 IS SIGNAL D: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS( A, B, C, D ) BEGIN D <= A; X <= B + D; D <= C; Y <= B + D; END PROCESS; END ARCHITECTURE bhv;