-- TTL164 Shift Register -- download from: www.fpga.com.cn & www.pld.com.cn library IEEE; use IEEE.Std_logic_1164.all; ENTITY dev164 IS PORT(a, b, nclr, clock : IN BIT; q : BUFFER BIT_VECTOR(0 TO 7)); END dev164; ARCHITECTURE version1 OF dev164 IS BEGIN PROCESS(a,b,nclr,clock) BEGIN IF nclr = '0' THEN q <= "00000000"; ELSE IF clock'EVENT AND clock = '1' THEN FOR i IN q'RANGE LOOP IF i = 0 THEN q(i) <= (a AND b); ELSE q(i) <= q(i-1); END IF; END LOOP; END IF; END IF; END PROCESS; END version1;