-- Language : VHDL -- File name : demo1.VHD -- Description : This is demo code for component instance -- It's function as following -- -- NOT ------ -- |\ (sigIN3) | -- IN1 ------| \O---------------| 2 -- |/ | AND |-----------> OUT1 -- IN2 -------------------------| / -- | / -- ------ -- -- -- -- See also : demo_01.VHD -- demo_02.VHD -- Top file : demo1.VHD ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY demo1 IS PORT ( IN1 : IN STD_LOGIC; IN2 : IN STD_LOGIC; OUT1 : OUT STD_LOGIC ); END ENTITY demo1; ARCHITECTURE bhv OF demo1 IS COMPONENT demo1_01 IS -- inverter component PORT ( A : IN STD_LOGIC; B : OUT STD_LOGIC ); END COMPONENT demo1_01; COMPONENT demo1_02 IS -- two and gate component PORT ( X : IN STD_LOGIC; Y : IN STD_LOGIC; Z : OUT STD_LOGIC ); END COMPONENT demo1_02; SIGNAL sigIN3 : STD_LOGIC; BEGIN U1: demo1_01 PORT MAP( A => IN1, B => sigIN3 ); U2: demo1_02 PORT MAP( X => sigIN3, Y => IN2, Z =>OUT1 ); END ARCHITECTURE bhv;