LIBRARY IEEE; USE IEEE. STD_LOGIC_1164. ALL; ENTITY onehot_fsm IS PORT(ip,reset,clk : IN BIT; --DECLARES THE INPUTS op : OUT BIT); --DECLARES THE OUTPUT END onehot_fsm; ARCHITECTURE operation_onehot_fsm OF onehot_fsm IS SIGNAL state: STD_LOGIC_VECTOR(5 DOWNTO 0); --STATE SIGNAL IS STD_LOGIC_VECTOR CONSTANT S0 : STD_LOGIC_VECTOR(5 DOWNTO 0) :="000001";--GIVING CONSTANT VALUE TO S0 CONSTANT S1 : STD_LOGIC_VECTOR(5 DOWNTO 0) :="000010";--GIVING CONSTANT VALUE TO S1 CONSTANT S2 : STD_LOGIC_VECTOR(5 DOWNTO 0) :="000100";--GIVING CONSTANT VALUE TO S2 CONSTANT S3 : STD_LOGIC_VECTOR(5 DOWNTO 0) :="001000";--GIVING CONSTANT VALUE TO S3 CONSTANT S4 : STD_LOGIC_VECTOR(5 DOWNTO 0) :="010000";--GIVING CONSTANT VALUE TO S4 CONSTANT S5 : STD_LOGIC_VECTOR(5 DOWNTO 0) :="100000";--GIVING CONSTANT VALUE TO S5 BEGIN PROCESS(ip,reset,clk) --BEGINING OF PROCESS WITH SENSITIVITY LIST BEGIN IF(reset='1') THEN state<= S0; ELSIF(clk'event and clk='1') THEN --ON CLK EVENT STATE IS LOADED CASE state IS --CASE CHECKS FOR VARIOUS CONDITIONS DEPENDING ON THE STATES WHEN S0 => IF(ip='1') THEN state <= S1; ELSE state <= S0; END IF; WHEN S1 => IF(ip='0') THEN state <= S2; ELSE state <= S1; END IF; WHEN S2 => IF(ip='0') THEN state <= S3; ELSE state <= S1; END IF; WHEN S3 => IF(ip='1') THEN state <= S4; ELSE state <= S0; END IF; WHEN S4 => IF(ip='1') THEN state <= S5; ELSE state <= S2; END IF; WHEN S5 => IF(ip='1') THEN state <= S1; ELSE state <= S2; END IF; WHEN OTHERS => state <=S0; END CASE; --END CASE END IF; END PROCESS; WITH state SELECT --USE OF WITH SELECT TO GIVE OUPUT BASED ON STATE CONDITION op <= '0' WHEN S0 , '0' WHEN S1, '0' WHEN S2, '0' WHEN S3, '0' WHEN S4, '1' WHEN S5, '0' WHEN OTHERS; END operation_onehot_fsm