-- VHDL code position: p315_ex10_5_serialize_pmultadd.txt -- Note : The code is about serializing optimize design OF VHDL, -- -- -- See Also: example 10-6 -- Debug : no debug --------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY mult1 IS PORT ( clk : IN STD_LOGIC; a0, a1, a2, a3 : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ); b0, b1, b2, b3 : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ); yout : OUT STD_LOGIC_VECTOR ( 15 DOWNTO 0 ) ); END ENTITY mult1; ARCHITECTURE rt1 OF mult1 IS SIGNAL ta : STD_LOGIC_VECTOR ( 11 DOWNTO 0 ); CONSTANT tb : STD_LOGIC_VECTOR ( 11 DOWNTO 0 ) := "100110111001"; BEGIN PROCESS ( clk ) BEGIN IF ( clk'EVENT AND clk = '1' ) THEN youy <= ( ( a0 * b0 ) +( a1 * b1 ) ) + ( ( a3 * b3 ) + ( a4 * b4 ) ); END IF; END PROCESS; END ARCHITECTURE rt1;