-- VHDL code position: p299_exer9_34_vga_image_controler_VGA640480.txt -- Note : This is a VGA image control code, -- for exproment 9-2 , page 298 -- -- See Also: no -- Debug : no debug --------------------------------------------------------------------------------- LIBRAY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY vga640480 IS PORT ( clk, : IN STD_LOGIC; hs, vs, r, g, b : OUT STD_LOGIC; rgbin : IN STD_LOGIC_VECTOR( 2 downto 0 ); hcntout, vcntout : OUT STD_LOGIC_VECTOR( 9 downto 0 ) ); END vga640480; ARCHITECTURE ONE of vga640480 IS SIGNAL hcnt : STD_LOGIC_VECTOR(9 downto 0); SIGNAL vcnt : STD_LOGIC_VECTOR(9 downto 0); BEGIN -- Assign pin hcntout <= hcnt; vcntout <= vcnt; --this is Horizonal counter PROCESS ( clk ) BEGIN IF ( rising_edge( clk ) ) THEN IF( hcnt < 800) THEN hcnt <= hcnt + 1; ELSE hcnt <= (others => '0'); END IF; END IF; END PROCESS; -- this is Vertical counter PROCESS ( clk ) BEGIN IF (rising_edge(clk)) THEN IF ( hcnt = 640+8 ) THEN IF( vcnt < 525) THEN vcnt <= vcnt + 1; ELSE vcnt <= (others => '0'); END IF; END IF; END IF; END PROCESS; -- this is hs pulse PROCESS ( clk ) BEGIN IF ( rising_edge( clk ) ) THEN IF( ( hcnt>= 640+8+8 ) AND ( hcnt < 640 + 8 + 8 + 96 ) ) THEN hs <= '0'; ELSE hs <= '1'; END IF; END IF; END PROCESS; -- this is vs pulse PROCESS ( vcnt ) BEGIN IF ( ( vcnt >= 480 + 8 + 2 ) AND ( vcnt < 480 + 8 + 2 + 2 ) ) THEN vs <= '0'; ELSE vs <= '1'; END IF; END PROCESS; PROCESS ( clk ) BEGIN IF ( rising_edge ( clk ) ) THEN IF ( hcnt < 640 AND vcnt < 480 ) THEN r <= rgbin( 2 ); g <= rgbin( 1 ); b <= rgbin( 0 ); ELSE r <= '0'; g <= '0'; b <= '0'; END IF; END IF; END PROCESS; END ONE;