-- VHDL code position: p288_ex9_30_attribute_statement_value_parity.txt -- Note : This is code for explaing Attribute Specification Statement -- of VHDL -- -- See Also: see 9_29, 9_30, 9_31 -- Debug : no debug --------------------------------------------------------------------------------- -- 9 kinds of Attribute Specification Statement: -- 1) LEFT -- 2) RIGHT -- 3) HIGH -- 4) LOW -- 5) RANGE -- 6) REVERS RANGE -- 7) LENGTH -- 8) EVENT -- 9) STABLE -- Attribute Specification Statement syntax: -- Attribute test item name'Attribute Designator -- -------------------------------------------------------- -- Fellowing is example NO 1 of data value -- ...... PROCESS ( clock, a, b ) TYPE obj IS ARRAY ( 0 TO 15 ) OF BIT SIGNAL ele1, ele2, ele3, ele4 : INTEGER; BEGIN ele1 <= obj'RIGHT; -- = 0 ?? ele2 <= obj'LEFT; -- = 15 ?? ele3 <= obj'HIGH; -- = 0 ele4 <= obj'LOW; -- = 15 ...... -------------------------------------------------------- -- Fellowing is example NO 2 of data value -- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY parity IS GENERIC ( bus_size : INTEGER := 8 ); PORT ( input_bus : IN STD_LOGIC_VECTOR ( bus_size-1 DOWNTO 0 ); even_numbits, odd_numbits : OUT STD_LOGIC ); END ENTITY parity; ARCHITECTURE bhv OF parity IS BEGIN PROCESS(CLK) VARIABLE temp : STD_LOGIC; BEGIN temp := '0'; FOR i IN input_bus'LOW TO input_bus'HIGH LOOP temp := temp XOR input_bus ( i ); END LOOP; odd_numbits <= temp; even_numbits <= NOT temp; END PROCESS; END ARCHITECTURE bhv;