合肥工业大学：EDA技术与应用（精品课程）：p285_ex9_27_concurrent_statement_generate_sn373

-- VHDL code position: p285_ex9_27_concurrent_statement_generate_SN373.txt -- Note : This is code for explaing Generate Statement -- in concurrent_statement of VHDL -- -- See Also: see 9_25, 9_26, 9_27, 9_28 -- Debug : no debug --------------------------------------------------------------------------------- -- 7 kinds of concurrent statement: -- 1) Concurrent Signal Assigment -- 2) Proces Statement -- 3) Block Statement -- 4) Select Signal Assigment Statement -- 5) Component Instantiations Statement -- 6) Generate Statement -- 7) Concurrent Procedure Calls Statement -- Generate Statement syntax: -- <Generate Label> : -- <Generation Scheme> GENERATE -- [ { <Block Declarative Item> } -- BEGIN ] -- { <Concurrent Statement> } -- END GENERATE [ <Generate Label> ] ; -- -- Note: -- Generate Label : 生成语句标号 -- Generation Scheme : 生成语句方案 -- Block Declarative Item : 块说明项目 -- Concurrent Statement : 并行语句 LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY SN373 IS PORT ( D : IN STD_LOGIC_VECTOR( 8 DOWNTO 1); OEN, G : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR( 8 DOWNTO 1) ); END ENTITY SN373; -------------------------------------------------- -- Fellowing is first ARCHITECTURE of ENTITY SN373 -- ARCHITECTURE one OF SN373 IS SIGNAL sigvec_save : STD_LOGIC_VECTOR( 8 DOWNTO 1); BEGIN PROCESS( D, ENA, g, sigvec_save ) BEGIN IF OENA = '0' THEN Q <= sig_save; ELSE Q <= "ZZZZZZZZ"; END IF; IF G = '1' THEN sigvec_save <= D; END IF; END PROCESS; END ARCHITECTURE one; -------------------------------------------------- -- Fellowing is two ARCHITECTURE of ENTITY SN373 -- ARCHITECTURE two OF SN373 IS COMPONENT latch PORT ( D : IN STD_LOGIC; ENA : IN STD_LOGIC; Q : OUT STD_LOGIC ); END COMPONENT latch SIGNAL sig_mid : STD_LOGIC_VECTOR( 8 DOWNTO 1); BEGIN gelatch: FOR iNum IN 1 TO 8 GENERATE latchx: latch PORT MAP ( D( iNum ), G, sig_mid( iNum ) ); END GENERATE gelatch; Q <= sig_mid WHEN OEN = '0' ELSE "ZZZZZZZZ" END ARCHITECTURE two;