合肥工业大学：EDA技术与应用（精品课程）：p280_ex9_21_concurrent_statement_BLOCK_exp2

-- VHDL code position: p280_ex9_21_concurrent_statement_block_exp2 -- Note : This is code for explaing block statement -- in concurrent_statement of VHDL -- -- See Also: example 9_20, 9_21 -- Debug : no debug --------------------------------------------------------------------------------- -- 7 kinds of concurrent statement: -- 1) Concurrent Signal Assigment -- 2) Proces Statement -- 3) Block Statement -- 4) Select Signal Assigment Statement -- 5) Component Instantiations Statement -- 6) Generate Statement -- 7) Concurrent Procedure Calls Statement -- BLOCK Concurrent Statement Syntax: -- -- <Block Label> : -- BLOCK [ ( <Guard Expression> ) ] [ IS ] -- <Block Header> -- <Block Declarative Part> -- BEGIN -- <Block Statement Part> -- END BLOCK [ <Block Label> ] ; -- -- Notes: -- Guard Expression : 块保护表达式 -- Block Header : 接口语句 -- Block Declarative Part : 类属语句 -- Block Statement Part : 块并行语句 -- ...... b1: BLOCK SIGANL s1 : BIT; BEGIN s1 <= a AND b; b2: BLOCK SIGNAL s2 : BIT; BEGIN s2 <= c AND d; b3: BLOCK BEGIN z <= s2; END BLOCK b3; END BLOCK b2; y <= s1; -- if write " y <= s2" , then is error END BLOCK b1;