合肥工业大学：EDA技术与应用（精品课程）：p284_ex9_25_concurrent_statement_generate_exp1

-- VHDL code position: p284_ex9_25_concurrent_statement_generate_exp1 -- Note : This is code for explaing Generate Statement -- in concurrent_statement of VHDL -- -- See Also: see 9_25, 9_26, 9_27, 9_28 -- Debug : no debug --------------------------------------------------------------------------------- -- 7 kinds of concurrent statement: -- 1) Concurrent Signal Assigment -- 2) Proces Statement -- 3) Block Statement -- 4) Select Signal Assigment Statement -- 5) Component Instantiations Statement -- 6) Generate Statement -- 7) Concurrent Procedure Calls Statement -- Generate Statement syntax: -- <Generate Label> : -- <Generation Scheme> GENERATE -- [ { <Block Declarative Item> } -- BEGIN ] -- { <Concurrent Statement> } -- END GENERATE [ <Generate Label> ] ; -- -- Note: -- Generate Label : 生成语句标号 -- Generation Scheme : 生成语句方案 -- Block Declarative Item : 块说明项目 -- Concurrent Statement : 并行语句 ...... COMPONENT comp PORT ( x : IN STD_LOGIC; y : OUT STD_LOGIC ); END COMPONENT comp SIGNAL a : STD_LOGIC_VECTOR ( 0 TO 7 ); SIGNAL b : STD_LOGIC_VECTOR ( 0 TO 7 ); ...... gen: FOR i IN a'RANGE GENERATE u1: comp PORT MAP ( x => a(i), y=> b(i) ); END GENERATE gen; ......