合肥工业大学：EDA技术与应用（精品课程）：p285_ex9_26_concurrent_statement_generate_latch

-- VHDL code position: p285_ex9_26_concurrent_statement_generate_latch.txt -- Note : This is code for explaing Generate Statement -- in concurrent_statement of VHDL -- -- See Also: see 9_25, 9_26, 9_27, 9_28 -- Debug : no debug --------------------------------------------------------------------------------- -- 7 kinds of concurrent statement: -- 1) Concurrent Signal Assigment -- 2) Proces Statement -- 3) Block Statement -- 4) Select Signal Assigment Statement -- 5) Component Instantiations Statement -- 6) Generate Statement -- 7) Concurrent Procedure Calls Statement -- Generate Statement syntax: -- <Generate Label> : -- <Generation Scheme> GENERATE -- [ { <Block Declarative Item> } -- BEGIN ] -- { <Concurrent Statement> } -- END GENERATE [ <Generate Label> ] ; -- -- Note: -- Generate Label : 生成语句标号 -- Generation Scheme : 生成语句方案 -- Block Declarative Item : 块说明项目 -- Concurrent Statement : 并行语句 LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY latch IS PORT ( D : IN STD_LOGIC; ENA : IN STD_LOGIC; Q : OUT STD_LOGIC ); END ENTITY latch; ARCHITECTURE bhv OF latch IS SIGNAL sig_save : STD_LOGIC; BEGIN PROCESS( D, ENA ) BEGIN IF ENA = '1' THEN sig_save <= D; END IF; Q <= sig_save; END PROCESS; END ARCHITECTURE bhv;