-- VHDL code position: p287_ex9_28_concurrent_statement_generate_d_ff.txt -- Note : This is code for explaing Generate Statement -- in concurrent_statement of VHDL -- -- See Also: see 9_25, 9_26, 9_27, 9_28 -- Debug : no debug --------------------------------------------------------------------------------- -- 7 kinds of concurrent statement: -- 1) Concurrent Signal Assigment -- 2) Proces Statement -- 3) Block Statement -- 4) Select Signal Assigment Statement -- 5) Component Instantiations Statement -- 6) Generate Statement -- 7) Concurrent Procedure Calls Statement -- Generate Statement syntax: -- <Generate Label> : -- <Generation Scheme> GENERATE -- [ { <Block Declarative Item> } -- BEGIN ] -- { <Concurrent Statement> } -- END GENERATE [ <Generate Label> ] ; -- -- Note: -- Generate Label : 生成语句标号 -- Generation Scheme : 生成语句方案 -- Block Declarative Item : 块说明项目 -- Concurrent Statement : 并行语句 -------------------------------------------------------- -- Fellowing is frist ENTITY -- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY d_ff IS PORT ( d, clk_s : IN_ STD_LOGIC; q : OUT STD_LOGIC; nq : OUT STD_LOGIC ); END ENTITY d_ff; -- Fellowing is ARCHITECTURE of ENTITY d_ff -- ARCHITECTURE a_rs_ff OF d_ff IS BEGIN bin_p_rs_ff: PROCESS ( clk_s ) BEGIN IF clk_s = '1' AND clk_s'EVENT THEN q <= d; np <= NOT d; END IF; END PROCESS; END ARCHITECTURE a_rs_ff; ------------------------------------------------------------------------ -- Fellowing is frist ENTITY -- -- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY cnt_bin_n IS GENERIC ( n: INTEGER := 6 ); PORT ( in_1 : IN STD_LOGIC; q : OUT STD_LOGIC ); END ENTITY cnt_bin_n; -- Fellowing is ARCHITECTURE of ENTITY cnt_bin_n -- ARCHITECTURE behv OF cnt_bin_n IS COMPONENT d_ff PORT ( d, clk_s : IN_ STD_LOGIC; q : OUT STD_LOGIC; nq : OUT STD_LOGIC ); END COMPONENT d_ff; SIGNAL s : STD_LOGIC_VECTOR ( 0 TO n ); BEGIN s( 0 ) <= in_1; q_1: FOR i IN 0 TO n-1 GENERATE dff: D_FF port map ( s( i+1 ), s( i ), q( i ), s( i+1 ) ); END GENERATE q_1; END ARCHITECTURE behv;