合肥工业大学：EDA技术与应用（精品课程）：p288_ex9_29_attribute_statement_data_range

-- VHDL code position: p288_ex9_29_attribute_statement_data_range.txt -- Note : This is code for explaing Attribute Specification Statement -- of VHDL -- -- See Also: see 9_29, 9_30, 9_31 -- Debug : no debug --------------------------------------------------------------------------------- -- 9 kinds of Attribute Specification Statement: -- 1) LEFT -- 2) RIGHT -- 3) HIGH -- 4) LOW -- 5) RANGE -- 6) REVERS RANGE -- 7) LENGTH -- 8) EVENT -- 9) STABLE -- Attribute Specification Statement syntax: -- Attribute test item name'Attribute Designator -- -------------------------------------------------------- -- Fellowing is example of data range specification -- ...... SIGNAL range1 : IN STD_LOGIC_VECTOR( 0 TO 7 ); ...... FOR i IN range1'RANGE LOOP .... END LOOP ......