合肥工业大学：EDA技术与应用（精品课程）：p291_exer9_5_dff

-- VHDL code position: p291_exer9_5_dff.txt -- Note : This is exercise code about DFF -- of VHDL -- -- See Also: no -- Debug : no debug --------------------------------------------------------------------------------- -- Please compare fellowing 3 kinds of DFF code -- --------------------------------------------------------- -- code one -- ARCHITECTURE rt1 OF ex IS SIGNAL a, b : STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); BEGIN PROCESS( clk ) BEGIN IF clk = '1' AND clk'EVENT THEN IF q (3 ) /= '1' THEN q <= a + b; END IF; END IF; END PROCESS; END ARCHITECTURE rt1; --------------------------------------------------------- -- code two -- ARCHITECTURE rt1 OF ex IS SIGNAL a, b : STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); BEGIN PROCESS( clk ) VARIABLE int : STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); BEGIN IF clk = '1' AND clk'EVENT THEN IF int (3 ) /= '1' THEN int := a + b; q <= int END IF; END IF; END PROCESS; END ARCHITECTURE rt1; -------------------------------------------------------- -- code three -- ARCHITECTURE rt1 OF ex IS SIGNAL a, b, c, d, e : STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); BEGIN PROCESS( c, d, e, en ) VARIABLE int : STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); BEGIN IF en = '1' THEN a <= c; b <= d; ELSE a<=e; END IF; END PROCESS; END ARCHITECTURE rt1;