-- VHDL code position: p313_ex10_3_logic_optimize -- Note : The code is about logic optimize OF VHDL, -- -- -- See Also: example 10-4 -- Debug : no debug --------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY mult1 IS PORT ( clk : IN STD_LOGIC; ma : IN STD_LOGIC_VECTOR ( 11 DOWNTO 0 ); mc : OUT STD_LOGIC_VECTOR ( 23 DOWNTO 0 ) ); END ENTITY mult1; ARCHITECTURE rt1 OF mult1 IS SIGNAL ta,tb : STD_LOGIC_VECTOR ( 11 DOWNTO 0 ); BEGIN PROCESS ( clk ) BEGIN IF ( clk'EVENT AND clk = '1' ) THEN ta <= ma ; tb <= "100110111001"; mc <= ta * tb; END IF; END PROCESS; END ARCHITECTURE rt1;