-- VHDL code position: p315_ex10_6_serialize_smultadd.txt -- Note : The code is about serializing optimize design OF VHDL, -- -- -- See Also: example 10-5 -- Debug : no debug --------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY smultadd IS PORT ( clk : IN STD_LOGIC; a0, a1, a2, a3 : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ); b0, b1, b2, b3 : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ); yout : OUT STD_LOGIC_VECTOR ( 15 DOWNTO 0 ) ); END ENTITY smultadd; ARCHITECTURE s_arch OF smultadd IS SIGNAL cnt : STD_LOGIC_VECTOR ( 2 DOWNTO 0 ); SIGNAL tmpa, tmpb : STD_LOGIC_VECTOR ( 7 DOWNTO 0 ); SIGNAL tmp, ytmp : STD_LOGIC_VECTOR ( 15 DOWNTO 0 ); BEGIN tempa <= a0 WHEN cnt = 0 ELSE a1 WHEN cnt = 1 ELSE a2 WHEN cnt = 2 ELSE a3 WHEN cnt = 3 ELSE a0; tempb <= b0 WHEN cnt = 0 ELSE b1 WHEN cnt = 1 ELSE b2 WHEN cnt = 2 ELSE b3 WHEN cnt = 3 ELSE b0; tmp <= tmpa * tmpb; PROCESS ( clk ) BEGIN IF ( clk'EVENT AND clk = '1' ) THEN IF start = '1' THEN cnt <= "000"; ytmp <= (others => '0' ); ELSIF ( cnt < 4 ) THEN cnt <= cnt + 1; ytmp <= ytmp + tmp; ELSIF (cnt = 4 ) THEN yout <= ytmp; END IF; END IF; END PROCESS; END ARCHITECTURE s_arch;